IS42S16100H-6BLI

IS42S16100H IS45S16100H 512K Words x 16 Bits x 2 Banks 16Mb SYNCHRONOUS DYNAMIC RAM FEATURES • Clock frequency: 200, 166, 143 MHz • Fully synchronous; all signals referenced to a positive clock edge • Two banks can be operated simultaneously and independently • Dual internal bank controlled by A11 (bank select) • Single 3.3V power supply • LVTTL interface • Programmable burst length – (1, 2, 4, 8, full page) • Programmable burst sequence: Sequential/Interleave • 2048 refresh cycles every 32ms (Com, Ind, A1 grade) or 16ms (A2 grade) • Random column address every clock cycle • Programmable CAS latency (2, 3 clocks) • Burst read/write and burst read/single write operations capability • Burst termination by burst stop and precharge command • Byte controlled by LDQM and UDQM • Packages: 400-mil 50-pin TSOP-II and 60-ball TF-BGA • Temperature Grades: Commercial (0oC to +70oC) Industrial (-40oC to +85oC) Automotive A1 (-40oC to +85oC) Automotive A2 (-40oC to +105oC) OCTOBER 2016 DESCRIPTION ISSI’s 16Mb Synchronous DRAM IS42/4516100H is organized as a 524,288-word x 16-bit x 2-bank for improved performance. The synchronous DRAMs achieve high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. Copyright © 2016 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc. — www.issi.com 1 Rev. A1 10/11/2016 IS42S16100H, IS45S16100H PIN CONFIGURATIONS 50-Pin TSOP (Type II) VDD 1 50 GND DQ0 2 49 DQ15 DQ1 3 48 DQ14 GNDQ 4 47 GNDQ DQ2 5 46 DQ13 DQ3 6 45 DQ12 VDDQ 7 44 VDDQ DQ4 8 43 DQ11 DQ5 9 42 DQ10 GNDQ 10 41 GNDQ DQ6 11 40 DQ9 DQ7 12 39 DQ8 VDDQ 13 38 VDDQ LDQM 14 37 NC WE 15 36 UDQM CAS 16 35 CLK RAS 17 34 CKE CS 18 33 NC A11 19 32 A9 A10 20 31 A8 A0 21 30 A7 A1 22 29 A6 A2 23 28 A5 A3 24 27 A4 VDD 25 26 GND PIN DESCRIPTIONS A0-A10 Row Address Input CAS Column Address Strobe Command A11 Bank Select Address WE Write Enable A0-A7 Column Address Input LDQM Lower Bye, Input/Output Mask DQ0 to DQ15 Data DQ UDQM Upper Bye, Input/Output Mask CLK System Clock Input VDD Power CKE Clock Enable GND Ground Chip Select VDDQ Power Supply for DQ Pin Row Address Strobe Command GNDQ Ground for DQ Pin CS RAS NC 2 No Connection Integrated Silicon Solution, Inc. — www.issi.com Rev. A1 10/11/2016 IS42S16100H, IS45S16100H PIN CONFIGURATION package code: B 60 bALL Tf-bga (Top View) (10.1 mm x 6.4 mm Body, 0.65 mm Ball Pitch) 1 2 3 4 5 6 7 A B C D E F G H J K L M N P R GND DQ15 DQ0 VDD DQ14 GND VDDQ DQ1 DQ13 VDDQ GNDQ DQ2 DQ12 DQ11 DQ4 DQ3 DQ10 GNDQ VDDQ DQ5 DQ9 VDDQ GNDQ DQ6 DQ8 NC NC DQ7 NC NC VDD NC LDQM WE NC UDQM NC CLK RAS CAS CKE NC NC CS A11 A9 NC NC A8 A7 A0 A10 A6 A5 A2 A1 GND A4 A3 VDD PIN DESCRIPTIONS A0-A10 Row Address Input A0-A7 Column Address Input A11 Bank Select Address DQ0 to DQ15 Data I/O CLK System Clock Input CKE Clock Enable CS Chip Select RAS Row Address Strobe Command CAS Column Address Strobe Command Integrated Silicon Solution, Inc. — www.issi.com Rev. A1 10/11/2016 WE Write Enable LDQM, UDQM x16 Input/Output Mask Vdd Power GND Ground Vddq Power Supply for I/O Pin GNDq Ground for I/O Pin NC No Connection 3 IS42S16100H, IS45S16100H PIN FUNCTIONS TSOP Pin No. Symbol Type Function (In Detail) 20 to 24 27 to 32 A0-A10 Input Pin A0 to A10 are address inputs. A0-A10 are used as row address inputs during active command input and A0-A7 as column address inputs during read or write command input. A10 is also used to determine the precharge mode during other commands. If A10 is LOW during precharge command, the bank selected by A11 is precharged, but if A10 is HIGH, both banks will be precharged. When A10 is HIGH in read or write command cycle, the precharge starts automatically after the burst access. These signals become part of the OP CODE during mode register set command input. 19 A11 Input Pin A11 is the bank selection signal. When A11 is LOW, bank 0 is selected and when high, bank 1 is selected. This signal becomes part of the OP CODE during mode register set command input. 16 CAS Input Pin CAS, in conjunction with the RAS and WE, forms the device command. See the “Command Truth Table” item for details on device commands. 34 CKE Input Pin The CKE input determines whether the CLK input is enabled within the device. When is CKE HIGH, the next rising edge of the CLK signal will be valid, and when LOW, invalid. When CKE is LOW, the device will be in either the power-down mode, the clock suspend mode, or the self refresh mode. The CKE is an asynchronous input. 35 CLK Input Pin CLK is the master clock input for this device. Except for CKE, all inputs to this device are acquired in synchronization with the rising edge of this pin. 18 CS Input Pin The CS input determines whether command input is enabled within the device. Command input is enabled when CS is LOW, and disabled with CS is HIGH. The device remains in the previous state when CS is HIGH. 2, 3, 5, 6, 8, 9, 11 DQ0 to 12, 39, 40, 42, 43, DQ15 45, 46, 48, 49 DQ Pin DQ0 to DQ15 are DQ pins. DQ through these pins can be controlled in byte units using the LDQM and UDQM pins. Input Pin LDQM and UDQM control the lower and upper bytes of the DQ buffers. In read mode, LDQM and UDQM control the output buffer. When LDQM or UDQM is LOW, the corresponding buffer byte is enabled, and when HIGH, disabled. The outputs go to the HIGH impedance state when LDQM/UDQM is HIGH. This function corresponds to OE in conventional DRAMs. In write mode, LDQM and UDQM control the input buffer. When LDQM or UDQM is LOW, the corresponding buffer byte is enabled, and data can be written to the device. When LDQM or UDQM is HIGH, input data is masked and cannot be written to the device. 17 RAS Input Pin RAS, in conjunction with CAS and WE, forms the device command. See the “Command Truth Table” item for details on device commands. 15 WE Input Pin WE, in conjunction with RAS and CAS, forms the device command. See the “Command Truth Table” item for details on device commands. 7, 13, 38, 44 VDDQ Power Supply Pin VDDQ is the output buffer power supply. 1, 25 VDD Power Supply Pin VDD is the device internal power supply. 4, 10, 41, 47 GNDQ Power Supply Pin GNDQ is the output buffer ground. 26, 50 GND Power Supply Pin GND is the device internal ground. 4 14, 36 LDQM, UDQM Integrated Silicon Solution, Inc. — www.issi.com Rev. A1 10/11/2016 IS42S16100H, IS45S16100H CLK CKE CS RAS CAS WE A11 COMMAND DECODER & CLOCK GENERATOR MODE REGISTER 11 ROW ADDRESS BUFFER ROW DECODER FUNCTIONAL BLOCK DIAGRAM 11 2048 BANK 0 DQM 11 CONTROLLER 11 ROW ADDRESS LATCH MULTIPLEXER REFRESH COUNTER 11 ROW ADDRESS BUFFER Integrated Silicon Solution, Inc. — www.issi.com Rev. A1 10/11/2016 COLUMN ADDRESS BUFFER REFRESH 11 ROW DECODER 8 BURST COUNTER SELF COLUMN ADDRESS LATCH REFRESH CONTROLLER DATA IN BUFFER SENSE AMP I/O GATE A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 MEMORY CELL ARRAY 256 16 16 DQ 0-15 COLUMN DECODER 8 256 SENSE AMP I/O GATE 16 2048 MEMORY CELL ARRAY BANK 1 DATA OUT BUFFER 16 VDD/VDDQ GND/GNDQ 5 IS42S16100H, IS45S16100H ABSOLUTE MAXIMUM RATINGS(1) Symbol Parameters Vdd max Maximum Supply Voltage –1.0 to +4.6 V Vddq Maximum Supply Voltage for Output Buffer –1.0 to +4.6 V Vin Input Voltage –1.0 to +4.6 V Vout Output Voltage –1.0 to +4.6 V Pd max Allowable Power Dissipation 1 W 50 mA Commerical Industrial A1 A2 0 to +70 -40 to +85 -40 to +85 -40 to +105 °C °C °C °C max Ics Output Shorted Current Topr Tstg Operating Temperature Storage Temperature Rating Unit –55 to +150 °C DC RECOMMENDED OPERATING CONDITION(2) (At Ta = 0oC to +70oC for Commercial temperature, Ta = -40oC to +85oC for Industrial and A1 temperature, Ta = -40oC to +105oC for A2 temperature) Symbol Vdd, Vddq Vih Vil Parameter Supply Voltage Input High Voltage(3) Input Low Voltage(4) Min. 3.0 2.0 -0.3 Typ. Max. 3.3 3.6 — Vdd + 0.3 — +0.8 Unit V V V CAPACITANCE CHARACTERISTICS(1,2) (At Ta = 0 to +25°C, VDD = VDDQ = 3.3 ± 0.3V, f = 1 MHz) Symbol Cin1 Cin2 CI/O Parameter Input Capacitance: A0-A11 Input Capacitance: (CLK, CKE, CS, RAS, CAS, WE, LDQM, UDQM) Data Input/Output Capacitance: DQ0-DQ15 Typ. Max. Unit — 4 pF — 4 pF — 5 pF Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. All voltages are referenced to GND. 3. Vih (max) = Vddq + 1.2V with a pulse width ≤ 3 ns. 4. Vil (min) = Vddq - 1.2V with a pulse width ≤ 3 ns. 6 Integrated Silicon Solution, Inc. — www.issi.com Rev. A1 10/11/2016 IS42S16100H, IS45S16100H DC ELECTRICAL CHARACTERISTICS (Recommended Operation Conditions unless otherwise noted.) Symbol Parameter Test Condition Speed Min. Iil Input Leakage Current 0V ≤ Vin ≤ VDD, with pins other than –5 the tested pin at 0V Iol Output Leakage Current Output is disabled, 0V ≤ Vout ≤ VDD –5 Voh Output High Voltage Level Iout = –2 mA 2.4 Vol Output Low Voltage Level Iout = +2 mA — Icc1 Operating Current(1,2) One Bank Operation, CAS latency = 3 Com. -5 — Burst Length=1 Com. -6 — trc ≥ trc (min.) Com. -7 — Iout = 0mA Ind, A1 -6 — A2 -6 — Ind, A1 -7 — A2 -7 — Icc2p Precharge Standby Current CKE ≤ Vil (max) tck = 15ns Com — — Ind, A1 — — Icc2ps (In Power-Down Mode) tck = ∞ Com — — Ind, A1 — — A2 — — Icc3n Active Standby Current CKE ≥ Vih (min) tck = 15ns — — Icc3ns (In Non Power-Down Mode) tck = ∞ Com — Ind, A1 — A2 — Icc4 Operating Current tck = tck (min) CAS latency = 3 Com -5 (In Burst Mode)(1) Iout = 0mA Com -6 Ind, A1 -6 A2 -6 Com -7 Ind, A1 -7 A2 -7 CAS latency = 2 Com -5 Com -6 Ind, A1 -6 A2 -6 Com -7 Ind, A1 -7 A2 -7 — — — — — — — — — — — — — — — — — Max. Unit 5 µA 5 µA — V 0.4 V 60 mA 55 50 60 65 55 60 3 4 2 3.5 3.5 40 mA m A mA 30 mA 30 30 80 mA 70 80 90 60 70 80 80 mA 70 80 90 60 70 80 Notes: 1. These are the values at the minimum cycle time. Since the currents are transient, these values decrease as the cycle time increases. Also note that a bypass capacitor of at least 0.01 µF should be inserted between Vdd and GND for each memory chip to suppress power supply voltage noise (voltage drops) due to these transient currents. 2. Icc1 and Icc4 depend on the output load. The maximum values for Icc1 and Icc4 are obtained with the output open state. Integrated Silicon Solution, Inc. — www.issi.com 7 Rev. A1 10/11/2016 IS42S16100H, IS45S16100H DC ELECTRICAL CHARACTERISTICS (Recommended Operation Conditions unless otherwise noted.) Symbol Parameter Test Condition Speed Min. Icc5 Auto-Refresh Current trc = trc (min) CAS latency = 3 Com. -5 — Com. -6 — Ind, A1 -6 — A2 -6 — Com -7 — Ind, A1 -7 — A2 -7 — CAS latency = 2 Com -5 — Com -6 — Ind, A1 -6 — A2 -6 — Com -7 — Ind, A1 -7 — A2 -7 — Icc6 Self-Refresh Current CKE ≤ 0.2V — — Max. Unit 50 mA 45 50 55 40 45 50 50 mA 45 50 55 40 45 50 2 mA Notes: 1. These are the values at the minimum cycle time. Since the currents are transient, these values decrease as the cycle time increases. Also note that a bypass capacitor of at least 0.01 µF should be inserted between Vdd and GND for each memory chip to suppress power supply voltage noise (voltage drops) due to these transient currents. 2. Icc1 and Icc4 depend on the output load. The maximum values for Icc1 and Icc4 are obtained with the output open state. 8 Integrated Silicon Solution, Inc. — www.issi.com Rev. A1 10/11/2016 IS42S16100H, IS45S16100H AC CHARACTERISTICS(1,2,3) -5 Symbol Parameter Min. Max. -6 -7 Min. Max. Min. Max. Units tck3 Clock Cycle Time tck2 CAS Latency = 3 CAS Latency = 2 5 — 8 — 6 8 tac3 Access Time From CLK(4) tac2 CAS Latency = 3 CAS Latency = 2 — — 5 6 — — 7 8 — — ns ns — 5.5 — 6 — 5.5 — 6 ns ns tchi CLK HIGH Level Width 2 — 2.5 — 2.5 — ns tcl CLK LOW Level Width 2 — 2.5 — 2.5 — ns toh3 Output Data Hold Time toh2 CAS Latency = 3 CAS Latency = 2 2 — 2.5 — 2.0 — 2.5 — 2.0 — 2.5 — ns ns 0 — 0 — — tlz Output LOW Impedance Time thz3 Output HIGH Impedance Time(5) thz2 CAS Latency = 3 CAS Latency = 2 5 6 — 0 — ns — 5.5 — 6 — 5.5 — 6 ns ns tds Input Data Setup Time 2 — 2 — 2 — ns tdh Input Data Hold Time 1 — 1 — 1 — ns tas Address Setup Time 2 — 2 — 2 — ns tah Address Hold Time 1 — 1 — 1 — ns tcks CKE Setup Time 2 — 2 — 2 — ns tckh CKE Hold Time 1 — 1 — 1 — ns tcka CKE to CLK Recovery Delay Time 1CLK+3 — 1CLK+3 — ns tcs Command Setup Time (CS, RAS, CAS, WE, DQM) 2 — 2 — 2 — ns tch Command Hold Time (CS, RAS, CAS, WE, DQM) 1 — 1 — 1 — ns trc Command Period (REF to REF / ACT to ACT) 50 — 54 — 63 — ns tras Command Period (ACT to PRE) 35 100,000 36 100,000 42 100,000 ns trp Command Period (PRE to ACT) 15 — 18 — 21 — ns trcd Active Command To Read / Write Command Delay Time 15 — 18 — 21 — ns trrd Command Period (ACT [0] to ACT[1]) 10 — 12 — 14 — ns CAS Latency = 3 2CLK — 2CLK — 2CLK — ns CAS Latency = 2 2CLK — 2CLK — 2CLK — ns Input Data To Active / Refresh CAS Latency = 3 tdal3 Command Delay time (During Auto-Precharge) tdal2 CAS Latency = 2 2CLK+trp — 2CLK+trp — 2CLK+trp — ns 2CLK+trp — 2CLK+trp — 2CLK+trp — ns 55 — 60 — 70 — ns 0.3 1.2 0.3 1.2 0.3 1.2 ns — 32 — 32 — 32 ms — — — — — 16 ms tdpl3 Input Data To Precharge Command Delay time tdpl2 txsr Exit Self-Refresh to Active Time tt Transition Time tref Refresh Cycle Time (2048) for temperature Ta ≤ 85 C tref Refresh Cycle Time (2048) for temperature Ta > 85 C (A2 only) o o 6 1CLK+3 — Notes: 1. When power is first applied, memory operation should be started 100 µs after Vdd and Vddq reach their stipulated voltages. Also note that the power-on sequence must be executed before starting memory operation. 2. Measured with tt = 1 ns. If clock rising time is longer than 1ns, (tt/2 - 0.5)ns should be added to the parameter. 3. The reference level is 1.4 V when measuring input signal timing. Rise and fall times are measured between Vih (min.) and Vil (max.). 4. Access time is measured at 1.4V with the load shown in the figure below. 5. The time thz (max.) is defined as the time required for the output voltage to transition by ± 200 mV from Voh (min.) or Vol (max.) when the output is in the high impedance state. 6. Self-Refresh Mode is not supported for A2 grade with Ta > 85oC. Integrated Silicon Solution, Inc. — www.issi.com 9 Rev. A1 10/11/2016 IS42S16100H, IS45S16100H OPERATING FREQUENCY / LATENCY RELATIONSHIPS (CAS Latency = 3) Symbol Parameter -5 -6 -7 Units — Clock Cycle Time 5 6 7 ns — Operating Frequency 200 166 143 MHz tcac CAS Latency 3 3 3 cycle trcd Active Command To Read/Write Command Delay Time 3 3 3 cycle trac RAS Latency (trcd + tcac) 6 6 6 cycle trc Command Period (REF to REF / ACT to ACT) 10 9 9 cycle tras Command Period (ACT to PRE) 7 6 6 cycle trp Command Period (PRE to ACT) 3 3 3 cycle trrd Command Period (ACT[0] to ACT [1]) 2 2 2 cycle tccd Column Command Delay Time (RE AD, READA, WRIT, WRITA) 1 1 1 cycle tdpl Input Data To Precharge Command Delay Time 2 2 2 cycle tdal Input Data To Active/Refresh Command Delay Time (During Auto-Precharge) 5 5 5 cycle trbd Burst Stop Command To Output in HIGH-Z Delay Time (Read) 3 3 3 cycle twbd Burst Stop Command To Input in Invalid Delay Time (Write) 0 0 0 cycle trql Precharge Command To Output in HIGH-Z Delay Time (Read) 3 3 3 cycle twdl Precharge Command To Input in Invalid Delay Time (Write) 0 0 0 cycle tpql Last Output To Auto-Precharge Start Time (Read) –2 –2 –2 cycle tqmd DQM To Output Delay Time (Read) 2 2 2 cycle tdmd DQM To Input Delay Time (Write) 0 0 0 cycle tmcd Mode Register Set To Command Delay Time 2 2 2 cycle AC TEST CONDITIONS (Input/Output Reference Level: 1.4V) Output Load Input tCHI tCK tCL 50 Ω 2.8V CLK 1.4V 0.0V tCS +1.4V I/O tCH 2.8V INPUT 1.4V 0.0V tAC tOH OUTPUT 10 1.4V 50 pF 1.4V Integrated Silicon Solution, Inc. — www.issi.com Rev. A1 10/11/2016 IS42S16100H, IS45S16100H COMMANDS Active Command Read Command CLK CLK CKE HIGH CKE HIGH CS CS RAS RAS CAS CAS WE WE A0-A9 ROW A0-A9 A10 ROW A10 COLUMN (1) AUTO PRECHARGE NO PRECHARGE BANK 1 A11 BANK 1 A11 BANK 0 BANK 0 Write Command Precharge Command CLK CLK CKE HIGH CKE HIGH CS CS RAS RAS CAS CAS WE WE A0-A9 COLUMN(1) A0-A9 BANK 0 AND BANK 1 AUTO PRECHARGE A10 A10 NO PRECHARGE BANK 0 OR BANK 1 BANK 1 BANK 1 A11 A11 BANK 0 BANK 0 Don't Care Notes: 1. A8-A9 = Don’t Care. Integrated Silicon Solution, Inc. — www.issi.com 11 Rev. A1 10/11/2016 IS42S16100H, IS45S16100H COMMANDS (cont.) No-Operation Command CLK CKE Device Deselect Command CLK HIGH CKE CS CS RAS RAS CAS CAS WE WE A0-A9 A0-A9 A10 A10 A11 A11 Mode Register Set Command HIGH Auto-Refresh Command CLK CLK CKE HIGH CKE HIGH CS CS RAS RAS CAS CAS WE WE A0-A9 OP-CODE A0-A9 A10 OP-CODE A10 A11 OP-CODE A11 Don't Care 12 Integrated Silicon Solution, Inc. — www.issi.com Rev. A1 10/11/2016 IS42S16100H, IS45S16100H COMMANDS (cont.) Self-Refresh Command Power Down Command CLK CLK CKE CKE CS CS NOP RAS RAS NOP CAS CAS NOP WE WE NOP A0-A9 A0-A9 A10 A10 A11 A11 Clock Suspend Command CLK CKE Burst Stop Command CLK BANK(S) ACTIVE CKE CS NOP CS RAS NOP RAS CAS NOP CAS WE NOP WE A0-A9 A0-A9 A10 A10 A11 A11 Integrated Silicon Solution, Inc. — www.issi.com Rev. A1 10/11/2016 ALL BANKS IDLE HIGH 13 IS42S16100H, IS45S16100H Mode Register Set Command (CS, RAS, CAS, WE = LOW) The IS42/4516100H product incorporates a register that defines the device operating mode. This command functions as a data input pin that loads this register from the pins A0 to A11. When power is first applied, the stipulated power-on sequence should be executed and then the IS42/4516100H should be initialized by executing a mode register set command. When the A10 pin is HIGH, this command functions as a read with auto-precharge command. After the burst read completes, the bank selected by pin A11 is precharged. When the A10 pin is LOW, the bank selected by the A11 pin remains in the activated state after the burst read completes. Note that the mode register set command can be executed only when both banks are in the idle state (i.e. deactivated). Write Command Another command cannot be executed after a mode register set command until after the passage of the period tmcd, which is the period required for mode register set command execution. When burst write mode has been selected with the mode register set command, this command selects the bank specified by the A11 pin and starts a burst write operation at the start address specified by pins A0 to A9. This first data must be input to the DQ pins in the cycle in which this command. Active Command The selected bank must be activated before executing this command. (CS, RAS = LOW, CAS, WE= HIGH) The IS42/4516100H includes two banks of 2048 rows each. This command selects one of the two banks according to the A11 pin and activates the row selected by the pins A0 to A10. This command corresponds to the fall of the RAS signal from HIGH to LOW in conventional DRAMs. Precharge Command (CS, CAS, WE = LOW, RAS = HIGH) When A10 pin is HIGH, this command functions as a write with auto-precharge command. After the burst write completes, the bank selected by pin A11 is precharged. When the A10 pin is low, the bank selected by the A11 pin remains in the activated state after the burst write completes. After the input of the last burst write data, the application must wait for the write recovery period (tdpl, tdal) to elapse according to CAS latency. (CS, RAS, WE = LOW, CAS = HIGH) This command starts precharging the bank selected by pins A10 and A11. When A10 is HIGH, both banks are precharged at the same time. When A10 is LOW, the bank selected by A11 is precharged. After executing this command, the next command for the selected bank(s) is executed after passage of the period trp, which is the period required for bank precharging. This command corresponds to the RAS signal from LOW to HIGH in conventional DRAMs Read Command (CS, CAS = LOW, RAS, WE = HIGH) This command selects the bank specified by the A11 pin and starts a burst read operation at the start address specified by pins A0 to A9. Data is output following CAS latency. Auto-Refresh Command (CS, RAS, CAS = LOW, WE, CKE = HIGH) This command executes the auto-refresh operation. The row address and bank to be refreshed are automatically generated during this operation. Both banks must be placed in the idle state before executing this command. The stipulated period (trc) is required for a single refresh operation, and no other commands can be executed during this period. The device goes to the idle state after the internal refresh operation completes. This command must be executed periodically according to tref specification (AC Characteristics). This command corresponds to CBR auto-refresh in conventional DRAMs. The selected bank must be activated before executing this command. 14 Integrated Silicon Solution, Inc. — www.issi.com Rev. A1 10/11/2016 IS42S16100H, IS45S16100H Self-Refresh Command Power-Down Command (CS, RAS, CAS, CKE = LOW, WE = HIGH) (CKE = LOW) This command executes the self-refresh operation. The row address to be refreshed, the bank, and the refresh interval are generated automatically internally during this operation.The self-refresh operation is started by dropping the CKE pin from HIGH to LOW. The self-refresh operation continues as long as the CKE pin remains LOW and there is no need for external control of any other pins. The self-refresh operation is terminated by raising the CKE pin from LOW to HIGH. The next command cannot be executed until the device internal recovery period (txsr) has elapsed. After the self-refresh, since it is impossible to determine the address of the last row to be refreshed, an auto-refresh should immediately be performed for all addresses (4096 cycles). When both banks are in the idle (inactive) state, or when at least one of the banks is not in the idle (inactive) state, this command can be used to suppress device power dissipation by reducing device internal operations to the absolute minimum. Power-down mode is started by dropping the CKE pin from HIGH to LOW. Power-down mode continues as long as the CKE pin is held low. All pins other than the CKE pin are invalid and none of the other commands can be executed in this mode.The power-down operation is terminated by raising the CKE pin from LOW to HIGH. The next command cannot be executed until the recovery period (tcka) has elapsed. Both banks must be placed in the idle state before executing this command. Since this command differs from the self-refresh command described above in that the refresh operation is not performed automatically internally, the refresh operation must be performed within the refresh period (tref). Thus the maximum time that power-down mode can be held is just under the refresh cycle time. Burst Stop Command (CS, WE, = LOW, RAS, CAS = HIGH) The command forcibly terminates burst read and write operations. When this command is executed during a burst read operation, data output stops after the CAS latency period has elapsed. No Operation (CS, = LOW, RAS, CAS, WE = HIGH) This command has no effect on the device. Device Deselect Command (CS = HIGH) This command does not select the device for an object of operation. In other words, it performs no operation with respect to the device. Integrated Silicon Solution, Inc. — www.issi.com Rev. A1 10/11/2016 Clock Suspend (CKE = LOW) This command can be used to stop the device internal clock temporarily during a read or write cycle. Clock suspend mode is started by dropping the CKE pin from HIGH to LOW. Clock suspend mode continues as long as the CKE pin is held LOW. All input pins other than the CKE pin are invalid and none of the other commands can be executed in this mode. Also note that the device internal state is maintained. Clock suspend mode is terminated by raising the CKE pin from LOW to HIGH, at which point device operation restarts. The next command cannot be executed until the recovery period (tcka) has elapsed. Since this command differs from the self-refresh command described above in that the refresh operation is not performed automatically internally, the refresh operation must be performed within the refresh period (tref). Thus the maximum time that clock suspend mode can be held is just under the refresh cycle time. 15 IS42S16100H, IS45S16100H COMMAND TRUTH TABLE(1,2) Symbol Command MRS Mode Register Set(3,4) REF Auto-Refresh(5) SREF Self-Refresh(5,6) PRE Precharge Selected Bank PALL Precharge Both Banks ACT Bank Activate(7) WRIT Write WRITA Write With Auto-Precharge(8) READ Read(8) READA Read With Auto-Precharge(8) BST Burst Stop(9) NOP No Operation DESL Device Deselect SBY Clock Suspend / Standby Mode ENB Data Write / Output Enable MASK Data Mask / Output Disable CKE n-1 n CS RAS CAS WE DQM H X L L L L X H H L L L H X H L L L L H X H X L L H L X H X L L H L X H X L L H H X H X L H L L X H X L H L L X H X L H L H X H X L H L H X H X L H H L X H X L H H H X H X H X X X X L X X X X X X H X X X X X L H X X X X X H A11 A10 A9-A0 I/On OP CODE X X X X HIGH-Z X X X HIGH-Z BS L X X X H X X BS Row Row X BS L Column(18) X BS H Column(18) X BS L Column(18) X BS H Column(18) X X X X X X X X X X X X X X X X X X X X Active X X X HIGH-Z DQM TRUTH TABLE(1,2) Symbol Command ENB Data Write / Output Enable MASK Data Mask / Output Disable ENBU Upper Byte Data Write / Output Enable ENBL Lower Byte Data Write / Output Enable MASKU Upper Byte Data Mask / Output Disable MASKL Lower Byte Data Mask / Output Disable CKE n-1 H H H H H H n X X X X X X DQM UPPER LOWER L L H H L X X L H X X H CKE TRUTH TABLE(1,2) Symbol Command SPND Start Clock Suspend Mode — Clock Suspend — Terminate Clock Suspend Mode REF Auto-Refresh SELF Start Self-Refresh Mode SELFX Terminate Self-Refresh Mode PDWN Start Power-Down Mode — Terminate Power-Down Mode 16 Current State Active Other States Clock Suspend Idle Idle Self-Refresh Idle Power-Down CKE n-1 n CS RAS CAS WE A11 A10 A9-A0 H L X X X X X X X L L X X X X X X X L H X X X X X X X H H L L L H X X X H L L L L H X X X L H L H H H X X X L H H X X X X X X H L L H H H X X X H L H X X X X X X L H X X X X X X X Integrated Silicon Solution, Inc. — www.issi.com Rev. A1 10/11/2016 IS42S16100H, IS45S16100H OPERATION COMMAND TABLE(1,2) Current State Idle Row Active Read Write Read With Auto- Precharge Command DESL NOP BST READ / READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS Operation No Operation or Power-Down(12) No Operation or Power-Down(12) No Operation or Power-Down Illegal Illegal Row Active No Operation Auto-Refresh or Self-Refresh(13) Mode Register Set No Operation No Operation No Operation Read Start(17) Write Start(17) Illegal(10) Precharge(15) Illegal Illegal Burst Read Continues, Row Active When Done Burst Read Continues, Row Active When Done Burst Interrupted, Row Active After Interrupt Burst Interrupted, Read Restart After Interrupt(16) Burst Interrupted Write Start After Interrupt(11,16) Illegal(10) Burst Read Interrupted, Precharge After Interrupt Illegal Illegal Burst Write Continues, Write Recovery When Done Burst Write Continues, Write Recovery When Done Burst Write Interrupted, Row Active After Interrupt Burst Write Interrupted, Read Start After Interrupt(11,16) Burst Write Interrupted, Write Restart After Interrupt(16) Illegal(10) Burst Write Interrupted, Precharge After Interrupt Illegal Illegal Burst Read Continues, Precharge When Done Burst Read Continues, Precharge When Done Illegal Illegal Illegal Illegal(10) Illegal(10) Illegal Illegal CS RAS CAS WE A11 A10 A9-A0 H X X X X X X L H H H X X X L H H L X X X L H L H V V V(18) L H L L V V V(18) L L H H V V V(18) L L H L V V X L L L H X X X L L L L OP CODE H X X X X X X L H H H X X X L H H L X X X L H L H V V V(18) L H L L V V V(18) L L H H V V V(18) L L H L V V X L L L H X X X L L L L OP CODE H X X X X X X L H H H X X X L H H L X X X L H L H V V V(18) L H L L V V V(18) L L H H V V V(18) L L H L V V X L L L H X X X L L L L OP CODE H X X X X X X L H H H X X X L H H L X X X L H L H V V V(18) L H L L V V V(18) L L H H V V V(18) L L H L V V X L L L H X X X L L L L OP CODE H X X X X X X L H H H X X X L H H L X X X L H L H V V V(18) L H L L V V V(18) L L H H V V V(18) L L H L V V X L L L H X X X L L L L OP CODE Integrated Silicon Solution, Inc. — www.issi.com 17 Rev. A1 10/11/2016 IS42S16100H, IS45S16100H OPERATION COMMAND TABLE(1,2) Current State Command Write With DESL Auto-Precharge NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS Row Precharge DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS Immediately DESL Following NOP Row Active BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS Operation CS RAS CAS WE A11 A10 A9-A0 Burst Write Continues, Write Recovery And Precharge When Done H X X X X X X X X Burst Write Continues, Write Recovery And Precharge L H H H X Illegal Illegal Illegal Illegal(10) Illegal(10) Illegal Illegal No Operation, Idle State After trp Has Elapsed No Operation, Idle State After trp Has Elapsed No Operation, Idle State After trp Has Elapsed Illegal(10) Illegal(10) Illegal(10) No Operation, Idle State After trp Has Elapsed(10) Illegal Illegal No Operation, Row Active After trcd Has Elapsed No Operation, Row Active After trcd Has Elapsed No Operation, Row Active After trcd Has Elapsed Illegal(10) Illegal(10) Illegal(10,14) Illegal(10) Illegal Illegal L L L L L L L H L H H H L L L L X H H L L H H L L X H L H L H L H L X H X X X (18) V V V V V V(18) V V V(18) V V X X X X OPCODE X X X X X X L H H L X L L L L L L H L L L L L L L H H L L L L X H H H H L L L L L H H L L X H H L L H H L H L H L H L X H L H L H L H V V V(18) V V V(18) V V V(18) V V X X X X OP CODE X X X X X X X X X V V V(18) V V V(18) V V V(18) X X V X V X X X Write Recovery DESL NOP L No Operation, Row Active After tdpl Has Elapsed H No Operation, Row Active After tdpl Has Elapsed L L X H L X H L X H OP CODE X X X X X X BST No Operation, Row Active After tdpl Has Elapsed L READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS Read Start Write Restart Illegal(10) Illegal(10) Illegal Illegal H H H L L L L H L L H H L L L H L H L H L X X X V V V(18) V V V(18) V V V(18) V V X X X X OP CODE 18 L L L L L L Integrated Silicon Solution, Inc. — www.issi.com Rev. A1 10/11/2016 IS42S16100H, IS45S16100H OPERATION COMMAND TABLE(1,2) Current State Command Write Recovery DESL With Auto- NOP Precharge BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS Refresh DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS Mode Register DESL Set NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS Operation No Operation, Idle State After tdal Has Elapsed No Operation, Idle State After tdal Has Elapsed No Operation, Idle State After tdal Has Elapsed Illegal(10) Illegal(10) Illegal(10) Illegal(10) Illegal Illegal No Operation, Idle State After trp Has Elapsed No Operation, Idle State After trp Has Elapsed No Operation, Idle State After trp Has Elapsed Illegal Illegal Illegal Illegal Illegal Illegal No Operation, Idle State After tmcd Has Elapsed No Operation, Idle State After tmcd Has Elapsed No Operation, Idle State After tmcd Has Elapsed Illegal Illegal Illegal Illegal Illegal Illegal CS RAS CAS WE A11 A10 A9-A0 H X X X X X X L H H H X X X L H H L X X X L H L H V V V(18) L H L L V V V(18) L L H H V V V(18) L L H L V V X L L L H X X X L L L L OP CODE H X X X X X X L H H H X X X L H H L X X X L H L H V V V(18) L H L L V V V(18) L L H H V V V(18) L L H L V V X L L L H X X X L L L L OP CODE H X X X X X X L H H H X X X L H H L X X X L H L H V V V(18) L H L L V V V(18) L L H H V V V(18) L L H L V V X L L L H X X X L L L L OP CODE Notes: 1. H: HIGH level input, L: LOW level input, X: "Don't Care" input, V: Valid data input 2. All input signals are latched on the rising edge of the CLK signal. 3. Both banks must be placed in the inactive (idle) state in advance. 4. The state of the A0 to A11 pins is loaded into the mode register as an OP code. 5. The row address is generated automatically internally at this time. The DQ pin and the address pin data is ignored. 6. During a self-refresh operation, all pin data (states) other than CKE is ignored. 7. The selected bank must be placed in the inactive (idle) state in advance. 8. The selected bank must be placed in the active state in advance. 9. This command is valid only when the burst length set to full page. 10. This is possible depending on the state of the bank selected by the A11 pin. 11. Time to switch internal busses is required. 12. The DRAM can be switched to power-down mode by dropping the CKE pin LOW when both banks in the idle state. Input pins other than CKE are ignored at this time. 13. The DRAM can be switched to self-refresh mode by dropping the CKE pin LOW when both banks in the idle state. Input pins other than CKE are ignored at this time. 14. Possible if trrd is satisfied. 15. Illegal if tras is not satisfied. 16. The conditions for burst interruption must be observed. Also note that the DRAM will enter the precharged state immediately after the burst operation completes if auto-precharge is selected. 17. Command input becomes possible after the period trcd has elapsed. Also note that the DRAM will enter the precharged state immediately after the burst operation completes if auto-precharge is selected. 18. A8,A9 = don’t care. Integrated Silicon Solution, Inc. — www.issi.com 19 Rev. A1 10/11/2016 IS42S16100H, IS45S16100H CKE RELATED COMMAND TRUTH TABLE(1) CKE Current State Operation n-1 n CS RAS CAS WE Self-Refresh Undefined H X X X X X Self-Refresh Recovery(2) L H H X X X (2) Self-Refresh Recovery L H L H H X Illegal(2) L H L H L X (2) Illegal L H L L X X Self-Refresh L L X X X X Self-Refresh Recovery Idle State After trc Has Elapsed H H H X X X Idle State After trc Has Elapsed H H L H H X Illegal H H L H L X Illegal H H L L X X Power-Down on the Next Cycle H L H X X X Power-Down on the Next Cycle H L L H H X Illegal H L L H L X Illegal H L L L X X (2) Clock Suspend Termination on the Next Cycle L H X X X X Clock Suspend L L X X X X Power-Down Undefined H X X X X X Power-Down Mode Termination, Idle After L H X X X X That Termination(2) Power-Down Mode L L X X X X Both Banks Idle No Operation H H H X X X See the Operation Command Table H H L H X X Bank Active Or Precharge H H L L H X Auto-Refresh H H L L L H Mode Register Set H H L L L L See the Operation Command Table H L H X X X See the Operation Command Table H L L H X X See the Operation Command Table H L L L H X Self-Refresh(3) H L L L L H See the Operation Command Table H L L L L L L X X X X X Power-Down Mode(3) Other States See the Operation Command Table H H X X X X Clock Suspend on the Next Cycle(4) H L X X X X Clock Suspend Termination on the Next Cycle L H X X X X Clock Suspend Termination on the Next Cycle L L X X X X A11 X X X X X X X X X X X X X X X X X X A10 A9-A0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X OP CODE X X X X X X X X X X X X OP CODE X X X X X X X X X X X X X X X Notes: 1. H: HIGH level input, L: LOW level input, X: "Don't Care" input 2. The CLK pin and the other input are reactivated asynchronously by the transition of the CKE level from LOW to HIGH. The minimum setup time (tcka) required before all commands other than mode termination must be satisfied. 3. Both banks must be set to the inactive (idle) state in advance to switch to power-down mode or self-refresh mode. 4. The input must be command defined in the operation command table. 20 Integrated Silicon Solution, Inc. — www.issi.com Rev. A1 10/11/2016 IS42S16100H, IS45S16100H TWO BANKS OPERATION COMMAND TRUTH TABLE(1,2) Previous State Next State Operation CS RAS CAS WE A11 A10 A9-A0 BANK 0 BANK 1 BANK 0 BANK 1 DESL H X X X X X X Any Any Any Any NOP L H H H X X X Any Any Any Any BST L H H L X X X R/W/A I/A A I/A I I/A I I/A I/A R/W/A I/A A I/A I I/A I READ/READA L H L H H H CA(3) I/A R/W/A I/A RP H H CA(3) R/W A A RP H L CA(3) I/A R/W/A I/A R H L CA(3) R/W A A R L H CA(3) R/W/A I/A RP I/A A R/W RP A L H CA(3) L L CA(3) R/W/A I/A R I/A L L CA(3) A R/W R A WRIT/WRITA L H L L H H CA(3) I/A R/W/A I/A WP H H CA(3) R/W A A WP H L CA(3) I/A R/W/A I/A W H L CA(3) R/W A A W L H CA(3) R/W/A I/A WP I/A L H CA(3) A R/W WP A L L CA(3) R/W/A I/A W I/A L L CA(3) A R/W W A ACT L L H H H RA RA Any I Any A L RA RA I Any A Any PRE/PALL L L H L X H X R/W/A/I I/A I I X H X I/A R/W/A/I I I H L X I/A R/W/A/I I/A I H L X R/W/A/I I/A R/W/A/I I L L X R/W/A/I I/A I I/A L L X I/A R/W/A/I I R/W/A/I REF L L L H X X X I I I I MRS L L L L OPCODE I I I I Notes: 1. H: HIGH level input, L: LOW level input, X: HIGH or LOW level input, RA: Row Address, CA: Column Address 2. The device state symbols are interpreted as follows: I Idle (inactive state) A Row Active State R Read W Write RP Read With Auto-Precharge WP Write With Auto-Precharge Any Any State 3. CA: A8,A9 = don’t care. Integrated Silicon Solution, Inc. — www.issi.com 21 Rev. A1 10/11/2016 IS42S16100H, IS45S16100H SIMPLIFIED STATE TRANSITION DIAGRAM (One Bank Operation) SELF REFRESH SREF entry SREF exit MRS MODE REGISTER SET AUTO REFRESH REF IDLE CKE_ CKE IDLE POWER DOWN ACT ACTIVE POWER DOWN CKE_ CKE BANK ACTIVE BST BST READ WRIT WRIT READ WRITA READA READ WRITE CKE_ READ CKE CLOCK SUSPEND READA WRITA WRITA CKE_ CKE READA WRITE WITH AUTO PRECHARGE POWER ON PRE CKE CKE_ READ WITH AUTO PRECHARGE PRE PRE POWER APPLIED CKE_ WRIT CLOCK SUSPEND CKE PRE PRECHARGE Automatic transition following the completion of command execution. Transition due to command input. 22 Integrated Silicon Solution, Inc. — www.issi.com Rev. A1 10/11/2016 IS42S16100H, IS45S16100H Device Initialization At Power-On Burst Length (Power-On Sequence) When writing or reading, data can be input or output data continuously. In these operations, an address is input only once and that address is taken as the starting address internally by the device. The device then automatically generates the following address. The burst length field in the mode register stipulates the number of data items input or output in sequence. In the DRAM product, a burst length of 1, 2, 4, 8, or full page can be specified. See the table on the next page for details on setting the mode register. As is the case with conventional DRAMs, the DRAM product must be initialized by executing a stipulated power-on sequence after power is applied. After power is applied and VDD and VDDQ reach their stipulated voltages, set and hold the CKE and DQM pins HIGH for 100 µs. Then, execute the precharge command to precharge both bank. Next, execute the auto-refresh command twice or more and define the device operation mode by executing a mode register set command. The mode register set command can be also set before auto-refresh command. Mode Register Settings The mode register set command sets the mode register. When this command is executed, pins A0 to A9, A10, and A11 function as data input pins for setting the register, and this data becomes the device internal OP code. This OP code has four fields as listed in the table below. Input Pin A11, A10, A9, A8, A7 A6, A5, A4 A3 A2, A1, A0 Field Mode Options CAS Latency Burst Type Burst Length Note that the mode register set command can be executed only when both banks are in the idle (inactive) state. If the Mode Register Set command is executed, the next command (except NOP or Deselect) cannot be executed until at least two clock cycles later, in order to avoid violating tMCD. Burst Type The burst data order during a read or write operation is stipulated by the burst type, which can be set by the mode register set command. The DRAM product supports sequential mode and interleaved mode burst type settings. See the table on the next page for details on setting the mode register. See the “Burst Length and Column Address Sequence” item for details on DQ data orders in these modes. Write Mode Burst write or single write mode is selected by the OP code (A11, A10, A9) of the mode register. A burst write operation is enabled by setting the OP code (A11, A10, A9) to (0,0,0). A burst write starts on the same cycle as a write command set. The write start address is specified by the column address and bank select address at the write command set cycle. A single write operation is enabled by setting OP code (A11, A10, A9) to (0, 0,1). In a single write operation, data is only written to the column address and bank select address specified by the write command set cycle without regard to the bust length setting. CAS Latency During a read operation, the between the execution of the read command and data output is stipulated as the CAS latency. This period can be set using the mode register set command. The optimal CAS latency is determined by the clock frequency and device speed grade. See the “Operating Frequency / Latency Relationships” item for details on the relationship between the clock frequency and the CAS latency. See the table on the next page for details on setting the mode register. Integrated Silicon Solution, Inc. — www.issi.com Rev. A1 10/11/2016 23 IS42S16100H, IS45S16100H MODE REGISTER A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 WRITE MODE LT MODE BT BL Address Bus (Ax) Mode Register (Mx) Burst Length M2 M1 M0 Sequential Interleaved 0 0 0 1 1 0 0 1 2 2 0 1 0 4 4 0 1 1 8 8 1 0 0 Reserved Reserved 1 0 1 Reserved Reserved 1 1 0 Reserved Reserved 1 1 1 Full Page Reserved Burst Type M3 Type 0 Sequential 1 Interleaved M6 M5 M4 CAS Latency Latency Mode 0 0 0 Reserved 0 0 1 Reserved 0 1 0 2 0 1 1 3 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Reserved 1 1 1 Reserved M11 M10 M9 M8 M7 Write Mode 0 0 1 0 0 Burst Read & Single Write 0 0 0 0 0 Burst Read & Burst Write Note: Other values for these bits are reserved. 24 Integrated Silicon Solution, Inc. — www.issi.com Rev. A1 10/11/2016 IS42S16100H, IS45S16100H Burst Length and Column Address Sequence Column Address Address Sequence Burst Length A2 A1 A0 Sequential Interleaved 2 X X X X 0 1 0-1 1-0 0-1 1-0 4 X X X X 0 0 1 1 0 1 0 1 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 8 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 Full Page (256) n n n Cn, Cn+1, Cn+2 Cn+3, Cn+4..... ...Cn-1(Cn+255), Cn(Cn+256)..... None Notes: 1. The burst length in full page mode is 256. Integrated Silicon Solution, Inc. — www.issi.com Rev. A1 10/11/2016 25 IS42S16100H, IS45S16100H Bank Select and Precharge Address Allocation Row X0 X1 X2 X3 X4 X5 X6 X7 — — — — — — — — Row Address Row Address Row Address Row Address Row Address Row Address Row Address Row Address X8 — Row Address X9 X10 X11 — Row Address — Row Address (Active Command) 0 Precharge of the Selected Bank (Precharge Command) 1 Precharge of Both Banks (Precharge Command) 0 Bank 0 Selected (Precharge and Active Commands) 1 Bank 1 Selected (Precharge and Active Commands) Column Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 — Column Address — Column Address — Column Address — Column Address — Column Address — Column Address — Column Address — Column Address — Don’t Care — Don’t Care 0 Auto-Precharge - Disabled 1 Auto-Precharge - Enables 0 Bank 0 Selected (Read and Write Commands) 1 Bank 1 Selected (Read and Write Commands) 26 Integrated Silicon Solution, Inc. — www.issi.com Rev. A1 10/11/2016 IS42S16100H, IS45S16100H Burst Read The read cycle is started by executing the read command. The address provided during read command execution is used as the starting address. First, the data corresponding to this address is output in synchronization with the clock signal after the CAS latency period. Next, data corresponding to an address generated automatically by the device is output in synchronization with the clock signal. The output buffers go to the LOW impedance state CAS latency minus one cycle after the read command, and go to the HIGH impedance state automatically after the last data is output. However, the case where the burst length is a full page is an exception. In this case the output buffers must be set to the high impedance state by executing a burst stop command. Note that upper byte and lower byte output data can be masked independently under control of the signals applied to the U/LDQM pins. The delay period (tqmd) is fixed at two, regardless of the CAS latency setting, when this function is used. The selected bank must be set to the active state before executing this command. CLK COMMAND READ A0 tQMD=2 UDQM LDQM DQ8-DQ15 DOUT A0 DQ0-DQ 7 DOUT A0 READ (CA=A, BANK 0) CAS latency = 3, burst length = 4 HI-Z DOUT A1 DOUT A2 DOUT A3 HI-Z HI-Z DATA MASK (LOWER BYTE) DATA MASK (UPPER BYTE) Burst Write The write cycle is started by executing the command. The address provided during write command execution is used as the starting address, and at the same time, data for this address is input in synchronization with the clock signal. Next, data is input in other in synchronization with the clock signal. During this operation, data is written to address generated automatically by the device. This cycle terminates automatically after a number of clock cycles determined by the stipulated burst length. However, the case where the burst length is a full page is an exception. In this case the write cycle must be terminated by executing a burst stop command. The latency for DQ pin data input is zero, regardless of the CAS latency setting. However, a wait period (write recovery: tdpl) after the last data input is required for the device to complete the write operation. Note that the upper byte and lower byte input data can be masked independently under control of the signals applied to the U/LDQM pins. The delay period (tdmd) is fixed at zero, regardless of the CAS latency setting, when this function is used. The selected bank must be set to the active state before executing this command. CLK COMMAND DQ WRITE DIN 0 DIN 1 DIN 2 DIN 3 BURST LENGTH CAS latency = 2,3, burst length = 4 Integrated Silicon Solution, Inc. — www.issi.com 27 Rev. A1 10/11/2016 IS42S16100H, IS45S16100H Read With Auto-Precharge The read with auto-precharge command first executes a burst read operation and then puts the selected bank in the precharged state automatically. After the precharge completes, the bank goes to the idle state. Thus this command performs a read command and a precharge command in a single operation. During this operation, the delay period (tpql) between the last burst data output and the start of the precharge operation differs depending on the CAS latency setting. When the CAS latency setting is two, the precharge operation starts on one clock cycle before the last burst data is output (tpql = –1). When the CAS latency setting is three, the precharge operation starts on two clock cycles before the last burst data is output (tpql = –2). Therefore, the selected bank can be made active after a delay of trp from the start position of this precharge operation. The selected bank must be set to the active state before executing this command. The auto-precharge function is invalid if the burst length is set to full page. CAS Latency tpql 3 2 –2 –1 CLK COMMAND READA 0 ACT 0 tPQL DQ DOUT 0 READ WITH AUTO-PRECHARGE (BANK 0) DOUT 1 DOUT 2 DOUT 3 tRP PRECHARGE START CAS latency = 2, burstlength = 4 CLK COMMAND ACT 0 READA 0 tPQL DQ READ WITH AUTO-PRECHARGE (BANK 0) DOUT 0 PRECHARGE START DOUT 1 DOUT 2 DOUT 3 tRP CAS latency = 3, burstlength = 4 28 Integrated Silicon Solution, Inc. — www.issi.com Rev. A1 10/11/2016 IS42S16100H, IS45S16100H Write With Auto-Precharge The write with auto-precharge command first executes a burst write operation and then puts the selected bank in the precharged state automatically. After the precharge completes the bank goes to the idle state. Thus this command performs a write command and a precharge command in a single operation. During this operation, the delay period (tdal) between the last burst data input and the completion of the precharge operation differs depending on the CAS latency setting. The delay (tdal) is trp plus two CLK periods. That is, the precharge operation starts two clock periods after the last burst data input. Therefore, the selected bank can be made active after a delay of tdal. The selected bank must be set to the active state before executing this command. The auto-precharge function is invalid if the burst length is set to full page. CAS Latency 3 2 tdal 2CLK 2CLK +trp +trp CLK COMMAND ACT 0 WRITE A0 PRECHARGE START DQ DIN 0 DIN 1 DIN 2 DIN 3 tRP tDAL WRITE WITH AUTO-PRECHARGE (BANK 0) CAS latency = 2, burstlength = 4 CLK COMMAND ACT 0 WRITE A0 PRECHARGE START DQ DIN 0 DIN 1 WRITE WITH AUTO-PRECHARGE (BANK 0) DIN 2 DIN 3 tRP tDAL CAS latency = 3, burstlength = 4 Integrated Silicon Solution, Inc. — www.issi.com 29 Rev. A1 10/11/2016 IS42S16100H, IS45S16100H Interval Between Read Command A new command can be executed while a read cycle is in progress, i.e., before that cycle completes. When the second read command is executed, after the CAS latency has elapsed, data corresponding to the new read command is output in place of the data due to the previous read command. The interval between two read command (tccd) must be at least one clock cycle. The selected bank must be set to the active state before executing this command. CLK COMMAND READ A0 READ B0 DQ DOUT A0 DOUT B0 DOUT B1 DOUT B2 DOUT B3 tCCD READ (CA=A, BANK 0) READ (CA=B, BANK 0) CAS latency = 2, burstlength = 4 Interval Between Write Command A new command can be executed while a write cycle is in progress, i.e., before that cycle completes. At the point the second write command is executed, data corresponding to the new write command can be input in place of the data for the previous write command. The interval between two write commands (tccd) must be at least one clock cycle. The selected bank must be set to the active state before executing this command. CLK tCCD COMMAND DQ WRITE A0 WRITE B0 DIN A0 DIN B0 DIN B1 DIN B2 DIN B3 WRITE (CA=A, BANK 0) WRITE (CA=B, BANK 0) CAS latency = 3, burstlength = 4 30 Integrated Silicon Solution, Inc. — www.issi.com Rev. A1 10/11/2016 IS42S16100H, IS45S16100H Interval Between Write and Read Commands A new read command can be executed while a write cycle is in progress, i.e., before that cycle completes. Data corresponding to the new read command is output after the CAS latency has elapsed from the point the new read command was executed. The I/On pins must be placed in the HIGH impedance state at least one cycle before data is output during this operation. The interval (tccd) between command must be at least one clock cycle. The selected bank must be set to the active state before executing this command. CLK tCCD COMMAND DQ WRITE A0 READ B0 DIN A0 HI-Z WRITE (CA=A, BANK 0) DOUT B0 DOUT B1 DOUT B2 DOUT B3 DOUT B0 DOUT B1 DOUT B2 READ (CA=B, BANK 0) CAS latency = 2, burstlength = 4 CLK tCCD COMMAND DQ WRITE A0 READ B0 DIN A0 WRITE (CA=A, BANK 0) HI-Z DOUT B3 READ (CA=B, BANK 0) CAS latency = 3, burstlength = 4 Integrated Silicon Solution, Inc. — www.issi.com Rev. A1 10/11/2016 31 IS42S16100H, IS45S16100H Interval Between Read and Write Commands A read command can be interrupted and a new write command executed while the read cycle is in progress, i.e., before that cycle completes. Data corresponding to the new write command can be input at the point new write command is executed. To prevent collision between input and output data at the DQn pins during this operation, the output data must be masked using the U/LDQM pins. The interval (tccd) between these commands must be at least one clock cycle. The selected bank must be set to the active state before executing this command. CLK tCCD COMMAND READ A0 WRITE B0 U/LDQM DQ HI-Z DIN B0 READ (CA=A, BANK 0) DIN B1 DIN B2 DIN B3 WRITE (CA=B, BANK 0) CAS latency = 2, 3, burstlength = 4 32 Integrated Silicon Solution, Inc. — www.issi.com Rev. A1 10/11/2016 IS42S16100H, IS45S16100H Precharge Read Cycle Interruption The precharge command sets the bank selected by pin A11 to the precharged state. This command can be executed at a time tras following the execution of an active command to the same bank. The selected bank goes to the idle state at a time trp following the execution of the precharge command, and an active command can be executed again for that bank. Using the Precharge Command If pin A10 is low when this command is executed, the bank selected by pin A11 will be precharged, and if pin A10 is HIGH, both banks will be precharged at the same time. This input to pin A11 is ignored in the latter case. A read cycle can be interrupted by the execution of the precharge command before that cycle completes. The delay time (trql) from the execution of the precharge command to the completion of the burst output is the clock cycle of CAS latency. CAS Latency trql 3 3 2 2 CLK tRQL COMMAND PRE 0 READ A0 DQ DOUT A0 DOUT A1 DOUT A2 READ (CA=A, BANK 0) HI-Z PRECHARGE (BANK 0) CAS latency = 2, burstlength = 4 CLK tRQL COMMAND READ A0 DQ PRE 0 DOUT A0 DOUT A1 DOUT A2 READ (CA=A, BANK 0) HI-Z PRECHARGE (BANK 0) CAS latency = 3, burstlength = 4 Integrated Silicon Solution, Inc. — www.issi.com Rev. A1 10/11/2016 33 IS42S16100H, IS45S16100H Write Cycle Interruption Using the Precharge Command A write cycle can be interrupted by the execution of the precharge command before that cycle completes. The delay time (twdl) from the precharge command to the point where burst input is invalid, i.e., the point where input data is no longer written to device internal memory is zero clock cycles regardless of the CAS. Inversely, to write all the burst data to the device, the precharge command must be executed after the write data recovery period (tdpl) has elapsed. Therefore, the precharge command must be executed two clock cycles after the input of the last burst data item. To inhibit invalid write, the DQM signal must be asserted HIGH with the precharge command. This precharge command and burst write command must be of the same bank, otherwise it is not precharge interrupt but only another bank precharge of dual bank operation. CAS Latency twdl 3 2 0 0 tdpl 2 2 CLK tWDL=0 COMMAND PRE 0 WRITE A0 DQM DQ DIN A0 DIN A1 DIN A2 DIN A3 MASKED BY DQM WRITE (CA=A, BANK 0) PRECHARGE (BANK 0) CAS latency = 2, burstlength = 4 CLK tDPL COMMAND DQ WRITE A0 DIN A0 DIN WRITE (CA=A, BANK 0) PRE 0 A1 DIN A2 DIN A3 PRECHARGE (BANK 0) CAS latency = 3, burstlength = 4 34 Integrated Silicon Solution, Inc. — www.issi.com Rev. A1 10/11/2016 IS42S16100H, IS45S16100H Read Cycle (Full Page) Interruption Using the Burst Stop Command The IS42/4516100H can output data continuously from the burst start address (a) to location a+255 during a read cycle in which the burst length is set to full page. The IS42/4516100H repeats the operation starting at the 256th cycle with the data output returning to location (a) and continuing with a+1, a+2, a+3, etc. A burst stop command must be executed to terminate this cycle. A precharge command must be executed within the ACT to PRE command period (tras max.) following the burst stop command. After the period (trbd) required for burst data output to stop following the execution of the burst stop command has elapsed, the outputs go to the HIGH impedance state. This period (trbd) is two clock cycle when the CAS latency is two and three clock cycle when the CAS latency is three. CAS Latency trbd 3 2 3 2 CLK tRBD COMMAND READ A0 DQ BST DOUT A0 DOUT A0 DOUT A1 DOUT A2 DOUT A3 HI-Z BURST STOP READ (CA=A, BANK 0) CAS latency = 2, burstlength = 4 CLK tRBD COMMAND BST READ A0 DQ DOUT A0 DOUT A0 READ (CA=A, BANK 0) DOUT A1 DOUT A2 DOUT A3 HI-Z BURST STOP CAS latency = 3, burstlength = 4 Integrated Silicon Solution, Inc. — www.issi.com Rev. A1 10/11/2016 35 IS42S16100H, IS45S16100H Write Cycle (Full Page) Interruption Using the Burst Stop Command must be executed within the ACT to PRE command period (tras max.) following the burst stop command. After the period (twbd) required for burst data input to stop following the execution of the burst stop command has elapsed, the write cycle terminates. This period (twbd) is zero clock cycles, regardless of the CAS latency. The DRAM can input data continuously from the burst start address (a) to location a+255 during a write cycle in which the burst length is set to full page. The DRAM repeats the operation starting at the 256th cycle with data input returning to location (a) and continuing with a+1, a+2, a+3, etc. A burst stop command must be executed to terminate this cycle. A precharge command CLK tWBD=0 COMMAND WRITE A0 BST tRP PRE 0 INVALID DATA DQ DIN A0 DIN A1 DIN A DIN A1 DIN A2 READ (CA=A, BANK 0) BURST STOP PRECHARGE (BANK 0) Don't Care Burst Data Interruption Using the U/LDQM Pins (Read Cycle) Burst data output can be temporarily interrupted (masked) during a read cycle using the U/LDQM pins. Regardless of the CAS latency, two clock cycles (tqmd) after one of the U/LDQM pins goes HIGH, the corresponding outputs go to the HIGH impedance state. Subsequently, the outputs are maintained in the high impedance state as long as that U/LDQM pin remains HIGH. When the U/LDQM pin goes LOW, output is resumed at a time tqmd later. This output control operates independently on a byte basis with the UDQM pin controlling upper byte output (pins DQ8-DQ15) and the LDQM pin controlling lower byte output (pins DQ0 to DQ7). Since the U/LDQM pins control the device output buffers only, the read cycle continues internally and, in particular, incrementing of the internal burst counter continues. CLK COMMAND READ A0 tQMD=2 UDQM LDQM DQ8-DQ15 DOUT A0 DQ0-DQ 7 DOUT A0 READ (CA=A, BANK 0) HI-Z DOUT A1 DOUT A2 DOUT A3 HI-Z HI-Z DATA MASK (LOWER BYTE) DATA MASK (UPPER BYTE) CAS latency = 2, burstlength = 4 36 Integrated Silicon Solution, Inc. — www.issi.com Rev. A1 10/11/2016 IS42S16100H, IS45S16100H Burst Data Interruption U/LDQM Pins (Write Cycle) Burst data input can be temporarily interrupted (muted ) during a write cycle using the U/LDQM pins. Regardless of the CAS latency, as soon as one of the U/LDQM pins goes HIGH, the corresponding externally applied input data will no longer be written to the device internal circuits. Subsequently, the corresponding input continues to be muted as long as that U/LDQM pin remains HIGH. that pin is dropped to LOW and data will be written to the device. This input control operates independently on a byte basis with the UDQM pin controlling upper byte input (pin DQ8 to DQ15) and the LDQM pin controlling the lower byte input (pins DQ0 to DQ7). Since the U/LDQM pins control the device input buffers only, the cycle continues internally and, in particular, incrementing of the internal burst counter continues. The DRAM will revert to accepting input as soon as CLK COMMAND WRITE A0 UDQM tDMD=0 LDQM DQ8-DQ15 DIN A1 DQ0-DQ7 DIN A0 WRITE (CA=A, BANK 0) DATA MASK (LOWER BYTE) DATA MASK (UPPER BYTE) DIN A2 DIN A3 DIN A3 Don't Care CAS latency = 2, burstlength = 4 Burst Read and Single Write The burst read and single write mode is set up using the mode register set command. During this operation, the burst read cycle operates normally, but the write cycle only writes a single data item for each write cycle. The CAS latency and DQM latency are the same as in normal mode. CLK COMMAND DQ WRITE A0 DIN A0 WRITE (CA=A, BANK 0) CAS latency = 2, 3 Integrated Silicon Solution, Inc. — www.issi.com Rev. A1 10/11/2016 37 IS42S16100H, IS45S16100H Bank Active Command Interval When the selected bank is precharged, the period trp has elapsed and the bank has entered the idle state, the bank can be activated by executing the active command. If the other bank is in the idle state at that time, the active command can be executed for that bank after the period trrd has elapsed. At that point both banks will be in the active state. When a bank active command has been executed, a precharge command must be executed for that bank within the ACT to PRE command period (tras max). Also note that a precharge command cannot be executed for an active bank before tras (min) has elapsed. After a bank active command has been executed and the trcd period has elapsed, read write (including autoprecharge) commands can be executed for that bank. CLK tRRD COMMAND ACT 0 ACT 1 BANK ACTIVE (BANK 0) BANK ACTIVE (BANK 1) CLK tRCD COMMAND ACT 0 READ 0 BANK ACTIVE (BANK 0) BANK ACTIVE (BANK 0) CAS latency = 3 Clock Suspend When the CKE pin is dropped from HIGH to LOW during a read or write cycle, the DRAM enters clock suspend mode on the next CLK rising edge. This command reduces the device power dissipation by stopping the device internal clock. Clock suspend mode continues as long as the CKE pin remains low. In this state, all inputs other than CKE pin are invalid and no other commands can be executed. Also, the device internal states are maintained. When the CKE pin goes from LOW to HIGH clock suspend mode is terminated on the next CLK rising edge and device operation resumes. The next command cannot be executed until the recovery period (tcka) has elapsed. Since this command differs from the self-refresh command described previously in that the refresh operation is not performed automatically internally, the refresh operation must be performed within the refresh period (tref). Thus the maximum time that clock suspend mode can be held is just under the refresh cycle time. CLK CKE COMMAND READ 0 DQ DOUT 0 READ (BANK 0) DOUT 1 DOUT 2 DOUT 3 CLOCK SUSPEND CAS latency = 2, burstlength = 4 38 Integrated Silicon Solution, Inc. — www.issi.com Rev. A1 10/11/2016 IS42S16100H, IS45S16100H OPERATION TIMING EXAMPLE Power-On Sequence, Mode Register Set Cycle T0 T1 T2 T3 T10 T17 T18 T19 T20 CLK tCHI tCK CKE HIGH tCS tCL tCH CS tCS tCH tCS tCH tCS tCH RAS CAS WE tAS A0-A9 tAH ROW CODE tAS A10 tAS tAH tAH CODE BANK 0 & 1 tAS A11 ROW tAH BANK 1 CODE BANK 0 DQM HIGH DQ WAIT TIME T=100 µs tRC tRP tRAS tRC tMCD tRC Undefined CAS latency = 2, 3 Integrated Silicon Solution, Inc. — www.issi.com Rev. A1 10/11/2016 Don't Care 39 IS42S16100H, IS45S16100H Power-Down Mode Cycle T0 T1 CLK tCKS tCK tCS tCKA tCH CKE T2 tCHI T3 tCL Tn Tn+1 Tn+2 Tn+3 tCKH tCKS tCKA CS tCS tCH tCS tCH tCS tCH RAS CAS WE tAS tAH ROW A0-A9 tAS A10 A11 tAH BANK 0 & 1 ROW BANK 0 OR 1 BANK 1 BANK 1 BANK 0 BANK 0 DQM DQ POWER DOWN MODE tRP EXIT POWER DOWN MODE tRAS tRC Undefined CAS latency = 2, 3 40 Don't Care Integrated Silicon Solution, Inc. — www.issi.com Rev. A1 10/11/2016 IS42S16100H, IS45S16100H Auto-Refresh Cycle T0 T1 T2 T3 Tl Tm Tn Tn+1 CLK tCKS tCK tCS tCH tCHI tCL CKE CS tCS tCH tCS tCH tCS tCH RAS CAS WE ROW A0-A9 tAS A10 tAH ROW BANK 0 & 1 BANK 1 A11 BANK 0 DQM DQ tRC tRP tRAS tRC tRC tRC Undefined CAS latency = 2, 3 Integrated Silicon Solution, Inc. — www.issi.com Rev. A1 10/11/2016 Don't Care 41 IS42S16100H, IS45S16100H Self-Refresh Cycle T0 T1 T2 T3 Tm Tm+1 Tm+2 Tn CLK tCKS CKE tCK tCHI tCL tCKS tCKA tCS tCH CS tCS tCH tCS tCH tCS tCH tAS tAH RAS CAS WE A0-A9 A10 BANK 0 & 1 A11 DQM DQ tRP SELF REFRESH MODE tXSR tRC Undefined CAS latency = 2, 3 Don't Care Note: 1: A8, A9 = Don’t Care. 2. Self-Refresh Mode is not supported for A2 grade with Ta > 85oC. 42 Integrated Silicon Solution, Inc. — www.issi.com Rev. A1 10/11/2016 IS42S16100H, IS45S16100H Read Cycle T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 CLK tCKS tCK tCS tCKA tCH CKE tCHI tCL CS tCS tCH tCS tCH tCS tCH tAS tAH RAS CAS WE A0-A9 COLUMN m ROW tAS ROW BANK 0 AND 1 tAH NO PRE ROW A10 tAH tAS A11 (1) ROW BANK 0 OR 1 BANK 1 BANK 1 BANK 1 BANK 1 BANK 0 tCS BANK 0 tCH BANK 0 tQMD BANK 0 DQM tAC tAC tOH DQ DOUT m tAC tAC tOH tOH tOH DOUT m+1 DOUT m+2 DOUT m+3 tLZ tCAC tRCD tRQL tRAS tHZ tRCD tRAS tRP tRC tRC Undefined CAS latency = 2, burstlength = 4 Don't Care Note 1: A8,A9 = Don’t Care. Integrated Silicon Solution, Inc. — www.issi.com Rev. A1 10/11/2016 43 IS42S16100H, IS45S16100H Read Cycle / Auto-Precharge T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 CLK tCKS tCK tCS tCKA tCH CKE tCHI tCL CS tCS tCH tCS tCH tCS tCH tAS tAH RAS CAS WE A0-A9 ROW tAS COLUMN m ROW AUTO PRE ROW BANK 1 BANK 1 tAH ROW A10 tAH tAS A11 (1) BANK 1 BANK 0 tCS BANK 0 BANK 0 tCH tQMD DQM tAC DQ tAC tAC tAC tOH tOH tOH tOH DOUT m DOUT m+1 DOUT m+2 DOUT m+3 tLZ tRCD tCAC tRAS tPQL tHZ tRCD tRAS tRP tRC tRC Undefined CAS latency = 2, burstlength = 4 Don't Care Note 1: A8,A9 = Don’t Care. 44 Integrated Silicon Solution, Inc. — www.issi.com Rev. A1 10/11/2016 IS42S16100H, IS45S16100H Read Cycle / Full Page T0 T1 T2 T3 T4 T5 T6 T260 T261 T262 T263 CLK tCKS tCK tCS tCKA tCH CKE tCHI tCL CS tCS tCH tCS tCH tCS tCH RAS CAS WE tAS A0-A9 tAH tAS tAH ROW A10 tAH tAS A11 (1) COLUMN ROW BANK 0 tCS NO PRE BANK 0 OR 1 BANK 0 BANK 0 tCH tQMD DQM tAC tAC tOH DQ DOUT 0m tAC tOH DOUT 0m+1 tAC tOH DOUT 0m-1 tAC tOH tOH DOUT 0m DOUT 0m+1 tLZ tRCD tCAC (BANK 0) tRAS tHZ tRBD tRP (BANK 0) tRC (BANK 0) Undefined CAS latency = 2, burstlength = full page Don't Care Note 1: A8,A9 = Don’t Care. Integrated Silicon Solution, Inc. — www.issi.com Rev. A1 10/11/2016 45 IS42S16100H, IS45S16100H Read Cycle / Ping-Pong Operation (Bank Switching) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 CLK tCKS tCK tCS tCKA tCH CKE tCHI tCL CS tCS tCH tCS tCH tCS tCH RAS CAS WE tAS A0-A9 tAH (1) ROW COLUMN tAS tAH AUTO PRE tAH NO PRE ROW COLUMN AUTO PRE ROW ROW A10 tAS A11 (1) ROW BANK 0 BANK 0 ROW BANK 1 tCS NO PRE BANK 0 OR 1 BANK 1 BANK 0 BANK 0 OR 1 BANK 0 BANK 1 tCH tQMD DQM tAC tAC tAC tOH DQ DOUT 0m tRRD (BANK 0 TO 1) tRCD (BANK 0) tCAC (BANK 1) DOUT 1m tCAC (BANK 1) tRP (BANK 0) tHZ tRCD (BANK 0) tRAS (BANK 0) tRC (BANK 0) tRAS (BANK 1) tRC (BANK 1) tOH DOUT 1m+1 tLZ tHZ tRCD (BANK 1) tRAS (BANK 0) tRC (BANK 0) DOUT 0m+1 tLZ tAC tOH tOH tRP (BANK1) Undefined CAS latency = 2, burstlength = 2 Don't Care Note 1: A8,A9 = Don’t Care. 46 Integrated Silicon Solution, Inc. — www.issi.com Rev. A1 10/11/2016 IS42S16100H, IS45S16100H Write Cycle T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 CLK tCKS tCK tCS tCKA tCH CKE tCHI tCL CS tCS tCH tCS tCH tCS tCH tAS tAH RAS CAS WE A0-A9 ROW tAS COLUMN m ROW BANK 0 AND 1 tAH NO PRE ROW A10 tAH tAS A11 (1) ROW BANK 1 BANK 0 OR 1 BANK 1 BANK 0 BANK 1 BANK 0 BANK 0 BANK 1 BANK 0 tCS tCH DQM tDS tDH tDS DIN m DQ tDH tDS DIN m+1 tDH tDS DIN m+2 tDH DIN m+3 tDPL tRCD tRAS tRCD tRP tRAS tRC tRC Undefined CAS latency = 2, burstlength = 4 Don't Care Note 1: A8,A9 = Don’t Care. Integrated Silicon Solution, Inc. — www.issi.com Rev. A1 10/11/2016 47 IS42S16100H, IS45S16100H Write Cycle / Auto-Precharge T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 CLK tCKS tCK tCS tCKA tCH CKE tCHI tCL CS tCS tCH tCS tCH tCS tCH tAS tAH RAS CAS WE A0-A9 ROW tAS COLUMN m ROW AUTO PRE ROW BANK 1 BANK 1 tAH ROW A10 tAH tAS A11 (1) BANK 1 BANK 0 BANK 0 tCS BANK 0 tCH DQM tDS tDH tDS DIN m DQ tDH tDS DIN m+1 tDH tDS DIN m+2 tDH DIN m+3 tDAL tRCD tRAS tRCD tRP tRAS tRC tRC Undefined CAS latency = 2, burstlength = 4 Don't Care Note 1: A8,A9 = Don’t Care. 48 Integrated Silicon Solution, Inc. — www.issi.com Rev. A1 10/11/2016 IS42S16100H, IS45S16100H Write Cycle / Full Page T0 T1 T2 T3 T4 T5 T258 T259 T260 T261 T262 CLK tCKS tCK tCS tCKA tCH CKE tCHI tCL CS tCS tCH tCS tCH tCS tCH tAS tAH RAS CAS WE A0-A9 COLUMN m ROW tAS tAH ROW A10 tAH tAS A11 (1) BANK 0 NO PRE BANK 0 OR 1 BANK 0 BANK 0 tCH tCS DQM tDS DQ tDH tDS DIN 0m tDH tDS DIN 0m+1 tDH tDS DIN 0m+2 tDH DIN 0m-1 DIN 0m tDPL tRCD tRAS tRP tRC Undefined CAS latency = 2, burst length = full page Don't Care Note 1: A8,A9 = Don’t Care. Integrated Silicon Solution, Inc. — www.issi.com Rev. A1 10/11/2016 49 IS42S16100H, IS45S16100H Write Cycle / Ping-Pong Operation T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 CLK tCKS tCK tCS tCKA tCH CKE tCHI tCL CS tCS tCH tCS tCH tCS tCH RAS CAS WE tAS A0-A9 tAH (1) ROW COLUMN tAS tAH AUTO PRE tAH NO PRE ROW COLUMN AUTO PRE ROW A10 ROW tAS A11 (1) ROW BANK 0 BANK 0 ROW BANK 1 NO PRE BANK 0 OR 1 BANK 1 BANK 0 BANK 0 tCH tCS DQM tDS tDH tDS DIN 0m DQ tRRD (BANK 0 TO 1) tRCD (BANK 0) DIN 0m+1 tDH tDS DIN 0m+2 tDH tDS DIN 0m+3 tDH tDS DIN 1m tDH tDS DIN 1m+1 tDH tDS DIN 1m+2 tDH DIN 1m+3 tDPL tRCD (BANK 1) tRAS (BANK 0) tRC (BANK 0) tDH tDS tDPL tRP (BANK 0) tRAS (BANK 1) tRC (BANK 1) tRCD (BANK 0) tRAS (BANK 0) tRC (BANK 0) Undefined CAS latency = 2, burst length = 2 Don't Care Note 1: A8,A9 = Don’t Care. 50 Integrated Silicon Solution, Inc. — www.issi.com Rev. A1 10/11/2016 IS42S16100H, IS45S16100H Read Cycle / Page Mode T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 CLK tCKS tCK tCS tCKA tCH CKE tCHI tCL CS tCS tCH tCS tCH tCS tCH RAS CAS WE tAS A0-A9 tAH tAS tAH tAS A11 (1) COLUMN n COLUMN o tAH ROW A10 (1) (1) COLUMN m ROW BANK 1 BANK 0 tCS NO PRE NO PRE BANK 1 BANK 1 BANK 0 BANK 0 tQMD AUTO PRE BANK 0 AND 1 NO PRE BANK 0 OR 1 BANK 1 BANK 1 BANK 0 BANK 0 tCH DQM tAC tAC tOH DQ tAC tOH DOUT m DOUT m+1 tAC tOH DOUT n tAC tOH DOUT n+1 tAC tOH DOUT o tLZ tRCD tRAS tRC tHZ tCAC tOH DOUT o+1 tCAC tCAC tRQL tRP Undefined CAS latency = 2, burst length = 2 Don't Care Note 1: A8,A9 = Don’t Care. Integrated Silicon Solution, Inc. — www.issi.com Rev. A1 10/11/2016 51 IS42S16100H, IS45S16100H Read Cycle / Page Mode; Data Masking T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 CLK tCKS tCK tCS tCKA tCH CKE tCHI tCL CS tCS tCH tCS tCH tCS tCH tAS tAH RAS CAS WE A0-A9 COLUMN n COLUMN o tAH ROW A10 (1) (1) COLUMN m ROW tAS tAH tAS A11 (1) BANK 1 BANK 0 tCS NO PRE NO PRE BANK 1 BANK 1 BANK 0 BANK 0 tQMD NO PRE AUTO PRE BANK 0 AND 1 NO PRE BANK 0 OR 1 BANK 1 BANK 1 BANK 0 BANK 0 tCH tQMD DQM tAC tAC tAC tOH DQ tOH DOUT m DOUT m+1 tLZ tRCD tRAS tRC tCAC tAC tOH DOUT n tOH tOH DOUT o DOUT o+1 tLZ tHZ tCAC tAC tHZ tCAC tRQL tRP Undefined CAS latency = 2, burst length = 2 Don't Care Note 1: A8,A9 = Don’t Care. 52 Integrated Silicon Solution, Inc. — www.issi.com Rev. A1 10/11/2016 IS42S16100H, IS45S16100H Write Cycle / Page Mode T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 CLK tCKS tCK tCS tCKA tCH CKE tCHI tCL CS tCS tCH tCS tCH tCS tCH RAS CAS WE tAS A0-A9 tAH tAS (1) (1) COLUMN n COLUMN o tAH ROW A10 tAH tAS A11 (1) COLUMN m ROW BANK 1 BANK 0 tCS NO PRE NO PRE BANK 1 BANK 1 AUTO PRE BANK 0 AND 1 NO PRE BANK 0 OR 1 BANK 1 BANK 1 BANK 0 BANK 0 BANK 0 BANK 0 tCH DQM tDS tDH tDS DIN m DQ tDH tDS DIN m+1 tDH tDS DIN n tDH tDS DIN n+1 tDH tDS tDH DIN o DIN o+1 tRCD tRAS tRC tDPL tRP Undefined CAS latency = 2, burst length = 2 Don't Care Note 1: A8,A9 = Don’t Care. Integrated Silicon Solution, Inc. — www.issi.com Rev. A1 10/11/2016 53 IS42S16100H, IS45S16100H Write Cycle / Page Mode; Data Masking T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 CLK tCKS tCK tCS tCKA tCH CKE tCHI tCL CS tCS tCH tCS tCH tCS tCH RAS CAS WE tAS A0-A9 tAH tAS tAH tAS A11 COLUMN n COLUMN o tAH ROW A10 (1) (1) (1) COLUMN m ROW BANK 1 BANK 0 tCS AUTO PRE BANK 0 AND 1 NO PRE NO PRE BANK 1 BANK 1 NO PRE BANK 1OR 0 BANK 0 BANK 0 BANK 1 BANK 0 BANK 1 BANK 0 tCH DQM tDS tDH tDS DIN m DQ tDH tDS DIN m+1 tDH tDS DIN n tDH tDS DIN o tRCD tRAS tRC tDH DIN o+1 tDPL tRP Undefined CAS latency = 2, burst length = 2 Don't Care Note 1: A8,A9 = Don’t Care. 54 Integrated Silicon Solution, Inc. — www.issi.com Rev. A1 10/11/2016 IS42S16100H, IS45S16100H Read Cycle / Clock Suspend T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 CLK tCKS tCK tCS tCKA tCH CKE tCHI tCKS tCL tCKH CS tCS tCH tCS tCH tCS tCH tAS tAH RAS CAS WE A0-A9 tAS ROW tAH AUTO PRE BANK 0 AND 1 tAH NO PRE BANK 0 OR 1 BANK 1 BANK 1 BANK 0 BANK 0 ROW ROW A10 tAS A11 (1) COLUMN m ROW BANK 1 BANK 0 tCS BANK 1 BANK 0 tCH tQMD DQM tAC tAC tOH DQ tOH DOUT m DOUT m+1 tLZ tRCD tHZ tCAC tRAS tRAS tRP tRC tRC Undefined CAS latency = 2, burst length = 2 Don't Care Note 1: A8,A9 = Don’t Care. Integrated Silicon Solution, Inc. — www.issi.com Rev. A1 10/11/2016 55 IS42S16100H, IS45S16100H Write Cycle / Clock Suspend T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 CLK tCKS tCK tCS tCKA tCH CKE tCHI tCL tCKS tCKH CS tCS tCH tCS tCH tCS tCH tAS tAH RAS CAS WE A0-A9 COLUMN m ROW tAS ROW tAH AUTO PRE BANK 0 AND 1 tAH NO PRE BANK 0 OR 1 BANK 1 BANK 1 BANK 0 BANK 1 BANK 0 BANK 0 ROW ROW A10 tAS A11 (1) BANK 1 BANK 0 tCS tCH DQM tDS tDH DIN m DQ tRCD tDS tDH DIN m+1 tDPL tRAS tRAS tRP tRC tRC Undefined T0 CAS latency = 2, burst length = 2 Note 1: A8,A9 = Don’t Care. CLK tCKS tCK tCS tCKA tCH CKE CS tCS RAS 56 Integrated Silicon Solution, Inc. — www.issi.com CAS Rev. A1 10/11/2016 tCS IS42S16100H, IS45S16100H Read Cycle / Precharge Termination T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 CLK tCKS tCK tCS tCKA tCH CKE tCHI tCL CS tCS tCH tCS tCH tCS tCH RAS CAS WE tAS A0-A9 tAH tAS COLUMN n ROW AUTO PRE tAH ROW ROW A10 tAH tAS A11 (1) (1) COLUMN m ROW BANK 0 NO PRE BANK 0 OR 1 BANK 0 BANK 0 tCS BANK 1 BANK 0 tCH tQMD NO PRE BANK 1 BANK 0 DQM tAC tAC tOH DQ DOUT m tAC tOH tHZ tOH DOUT m+1 DOUT m+2 tLZ tRCD tCAC tRAS tRQL tRCD tRP tRAS tRC tCAC tRC Undefined CAS latency = 2, burst length = 4 Don't Care Note 1: A8,A9 = Don’t Care. Integrated Silicon Solution, Inc. — www.issi.com Rev. A1 10/11/2016 57 IS42S16100H, IS45S16100H Write Cycle / Precharge Termination T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 CLK tCKS tCK tCS tCKA tCH CKE tCHI tCL CS tCS tCH tCS tCH tCS tCH RAS CAS WE tAS A0-A9 tAH tAS COLUMN n ROW AUTO PRE tAH ROW ROW A10 BANK 0 OR 1 NO PRE tAH tAS A11 (1) (1) COLUMN m ROW BANK 0 BANK 0 NO PRE BANK 1 BANK 0 tCS tCH tCS tDH tDS tDH BANK 1 BANK 0 tCH BANK 0 tCS DQM tDH tDS tDS DQ DIN 0m DIN 0m+1 DIN 0m+2 DIN 0n tRCD tRCD tRAS tRAS tRP tRC tDH tDS tRC Undefined CAS latency = 2, burst length = 4 Don't Care Note 1: A8,A9 = Don’t Care. 58 Integrated Silicon Solution, Inc. — www.issi.com Rev. A1 10/11/2016 IS42S16100H, IS45S16100H Read Cycle / Byte Operation T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 CLK tCKS tCK tCS tCKA tCH CKE tCHI tCL CS tCS tCH tCS tCH tCS tCH RAS CAS WE tAS A0-A9 tAH tAS tAH ROW AUTO PRE BANK 0 AND 1 NO PRE BANK 0 OR 1 BANK 1 BANK 0 BANK 1 ROW ROW A10 tAH tAS A11 (1) COLUMN m ROW BANK 1 BANK 0 tCS BANK 0 tCH tQMD BANK 1 BANK 0 UDQM tQMD tCS tCH LDQM tAC tLZ DQ8-15 tAC tHZ tOH tLZ DOUT m+2 DOUT m tAC tLZ DQ0-7 tCAC tOH DOUT m+3 tAC tOH DOUT m tRCD tAC tOH tOH DOUT m+1 tQMD tRQL tRAS tRCD tRP tRAS tRC tRC Undefined CAS latency = 2, burst length = 4 Don't Care Note 1: A8,A9 = Don’t Care. Integrated Silicon Solution, Inc. — www.issi.com Rev. A1 10/11/2016 59 IS42S16100H, IS45S16100H Write Cycle / Byte Operation T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 CLK tCKS tCK tCS tCKA tCH CKE tCHI tCL CS tCS tCH tCS tCH tCS tCH RAS CAS WE tAS A0-A9 tAH tAS tAH ROW AUTO PRE BANK 0 AND 1 NO PRE BANK 0 OR 1 BANK 1 BANK 0 BANK 1 ROW ROW A10 tAH tAS A11 (1) COLUMN m ROW BANK 1 BANK 0 tCS BANK 0 tCH BANK 1 BANK 0 UDQM tCS tCH tDS tDS tDH LDQM DQ8-15 DIN m tDH tDS DIN m+1 DIN m+3 tDH tDS DQ0-7 tDH tDH tDS DIN m DIN m+3 tRCD tDPL tRCD tRAS tRP tRAS tRC tRC Undefined CAS latency = 2, burst length = 4 Don't Care Note 1: A8,A9 = Don’t Care. 60 Integrated Silicon Solution, Inc. — www.issi.com Rev. A1 10/11/2016 IS42S16100H, IS45S16100H Read Cycle, Write Cycle / Burst Read, Single Write T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 CLK tCKS tCK tCS tCKA tCH CKE tCHI tCL CS tCS tCH tCS tCH tCS tCH RAS CAS WE tAS A0-A9 tAH tAS (1) COLUMN n tAH tAH tAS AUTO PRE BANK 0 AND 1 NO PRE BANK 0 OR 1 BANK 1 BANK 1 BANK 0 BANK 0 NO PRE ROW A10 A11 (1) COLUMN m ROW BANK 1 BANK 1 BANK 0 tCS BANK 0 tCH tQMD DQM tAC tAC tOH DQ DOUT m tLZ tRCD tAC tAC tDS tOH tOH tOH DOUT m+1 DOUT m+2 DOUT m+3 tDH DIN n tHZ tCAC tDPL tRAS tRP tRC Undefined CAS latency = 2, burst length = 4 Don't Care Note 1: A8,A9 = Don’t Care. Integrated Silicon Solution, Inc. — www.issi.com 61 Rev. A1 10/11/2016 IS42S16100H, IS45S16100H Read Cycle T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 CLK tCKS tCK tCS tCKA tCH CKE tCHI tCL CS tCS tCH tCS tCH tCS tCH RAS CAS WE tAS A0-A9 tAH tAS BANK 0 AND 1 NO PRE tAH tAS A11 ROW tAH ROW A10 (1) COLUMN m ROW ROW BANK 0 OR 1 BANK 1 BANK 1 BANK 1 BANK 1 BANK 0 BANK 0 tCS tCH BANK 0 tQMD BANK 0 DQM tAC tAC tOH DQ DOUT m tAC tAC tOH tOH tOH DOUT m+1 DOUT m+2 DOUT m+3 tLZ tRCD tCAC tRQL tRAS tHZ tRCD tRAS tRP tRC tRC Undefined CAS latency = 3, burst length = 4 Don't Care Note 1: A8,A9 = Don’t Care. 62 Integrated Silicon Solution, Inc. — www.issi.com Rev. A1 10/11/2016 IS42S16100H, IS45S16100H Read Cycle / Auto-Precharge T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 CLK tCKS tCK tCS tCKA tCH CKE tCHI tCL CS tCS tCH tCS tCH tCS tCH tAS tAH RAS CAS WE A0-A9 tAH ROW AUTO PRE ROW ROW A10 tAH tAS A11 COLUMN ROW tAS (1) BANK 1 BANK 1 BANK 1 BANK 0 BANK 0 tCS BANK 0 tCH tQMD DQM tAC tAC tOH DQ DOUT m tAC tAC tOH tOH tOH DOUT m+1 DOUT m+2 DOUT m+3 tLZ tRCD tCAC tRAS tPQL tHZ tRCD tRAS tRP tRC tRC Undefined CAS latency = 3, burst length = 4 Note 1: A8,A9 = Don’t Care. T0 CLK tCKS CKE t tCS CS t Integrated Silicon Solution, Inc. — www.issi.com RAS Rev. A1 10/11/2016 63 t CAS IS42S16100H, IS45S16100H Read Cycle / Full Page T0 T1 T2 T3 T4 T5 T6 T7 T8 T262 T263 T264 T265 CLK tCKS tCK tCS tCKA tCH CKE tCHI tCL CS tCS tCH tCS tCH tCS tCH RAS CAS WE tAS A0-A9 tAH tAS tAH NO PRE ROW A10 BANK 0 OR 1 tAH tAS A11 (1) COLUMN ROW BANK 0 BANK 0 BANK 0 tCH tCS DQM tAC tAC tOH DQ DOUT 0m tAC tOH DOUT 0m+1 tAC tOH DOUT 0m-1 tAC tOH tOH DOUT 0m DOUT 0m+1 tLZ tRCD (BANK 0) tRAS (BANK 0) tRC (BANK 0) (BANK 0) tHZ tRBD tCAC tRP (BANK 0) Undefined CAS latency = 3, burst length = full page Don't Care Note 1: A8,A9 = Don’t Care. 64 Integrated Silicon Solution, Inc. — www.issi.com Rev. A1 10/11/2016 IS42S16100H, IS45S16100H Read Cycle / Ping Pong Operation (Bank Switching) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 ROW COLUMN COLUMN AUTO PRE AUTO PRE NO PRE NO PRE BANK 0 OR 1 BANK 0 OR 1 BANK 0 BANK 1 BANK 0 BANK1 T12 CLK tCKS tCK tCS tCKA tCH CKE tCHI tCL CS tCS tCH tCS tCH tCS tCH RAS CAS WE tAS A0-A9 tAH ROW tAS tAH ROW tAH tAS A11 ROW ROW ROW A10 (1) (1) BANK 0 BANK 1 tCS BANK 0 tCH tQMD DQM tAC tLZ tAC tOH DQ DOUT 0m tRRD (BANK 0 TO 1) tRCD (BANK 0) tCAC tOH DOUT 1m DOUT 1m+1 tHZ tRQL (BANK 0) tRP (BANK 1) tRC (BANK 1) tRCD (BANK 0) tRAS (BANK 0) (BANK 0) tRP (BANK 0) tRAS DOUT 0m+1 tAC tOH tCAC (BANK 1) tRCD (BANK 1) tRAS (BANK 0) tRC (BANK 0) tAC tOH tRC (BANK 0) (BANK1) Undefined CAS latency = 3, burst length = 2 Don't Care Note 1: A8,A9 = Don’t Care. Integrated Silicon Solution, Inc. — www.issi.com Rev. A1 10/11/2016 65 IS42S16100H, IS45S16100H Write Cycle T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 CLK tCKS tCK tCS tCKA tCH CKE tCHI tCL CS tCS tCH tCS tCH tCS tCH RAS CAS WE tAS A0-A9 tAH tAS COLUMN ROW BANK 0 AND 1 tAH NO PRE ROW A10 tAH tAS A11 (1) ROW ROW BANK 1 BANK 0 OR 1 BANK 1 BANK 0 BANK 1 BANK 0 BANK 0 BANK 1 BANK 0 tCS tCH DQM tDS tDH tDS DIN m DQ tDH tDS DIN m+1 tDH tDS DIN m+2 tDH DIN m+3 tDPL tRCD tRAS tRCD tRP tRAS tRC tRC Undefined CAS latency = 3, burst length = 4 Don't Care Note 1: A8,A9 = Don’t Care. 66 Integrated Silicon Solution, Inc. — www.issi.com Rev. A1 10/11/2016 IS42S16100H, IS45S16100H Write Cycle / Auto-Precharge T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 CLK tCKS tCK tCS tCKA tCH CKE tCHI tCL CS tCS tCH tCS tCH tCS tCH RAS CAS WE tAS A0-A9 tAH tAS COLUMN ROW AUTO PRE tAH ROW A10 ROW tAH tAS A11 (1) ROW BANK 1 BANK 1 BANK 1 BANK 0 BANK 0 tCS BANK 0 tCH DQM tDS tDH tDS DIN m DQ tDH tDS DIN m+1 tDH tDS DIN m+2 tDH DIN m+3 tDAL tRCD tRAS tRCD tRP tRAS tRC tRC Undefined CAS latency = 3, burst length = 4 Don't Care Note 1: A8,A9 = Don’t Care. Integrated Silicon Solution, Inc. — www.issi.com 67 Rev. A1 10/11/2016 IS42S16100H, IS45S16100H Write Cycle / Full Page T0 T1 T2 T3 T4 T5 T6 T259 T260 T261 T262 T263 T264 CLK tCKS tCK tCS tCKA tCH CKE tCHI tCL CS tCS tCH tCS tCH tCS tCH RAS CAS WE tAS A0-A9 tAH tAS tAH NO PRE ROW A10 BANK 0 OR 1 tAH tAS A11 (1) COLUMN ROW BANK 0 BANK 0 BANK 0 tCH tCS DQM tDS DQ tDH tDS DIN 0m tDH tDS DIN 0m+1 tDH tDS DIN 0m+2 tDH DIN 0m-1 DIN 0m tDPL tRCD tRAS tRP tRC Undefined CAS latency = 3, burst length = full page Don't Care Note 1: A8,A9 = Don’t Care. 68 Integrated Silicon Solution, Inc. — www.issi.com Rev. A1 10/11/2016 IS42S16100H, IS45S16100H Write Cycle / Ping-Pong Operation (Bank Switching) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T11 T10 T12 CLK tCKS tCK tCS tCKA tCH CKE tCHI tCL CS tCS tCH tCS tCH tCS tCH RAS CAS WE tAS A0-A9 tAH ROW COLUMN tAS ROW COLUMN AUTO PRE AUTO PRE tAH ROW A10 ROW ROW NO PRE tAH tAS A11 (1) (1) ROW BANK 0 BANK 0 BANK 1 NO PRE BANK 0 OR 1 BANK 1 BANK 0 BANK 1 BANK 0 tCH tCS DQM tDS tDH tDS DIN 0m DQ tDH tDS DIN 0m+1 tRRD (BANK 0 TO 1) tRCD (BANK 0) tDH tDS DIN 0m+2 tRCD tDH tDS DIN 0m+3 tDH tDS DIN 1m tDH tDS DIN 1m+1 tDH tDS DIN 1m+2 tDH DIN 1m+3 tDPL (BANK 0) tDPL tRCD (BANK 1) tRP tRAS tRAS (BANK 0) (BANK 0) tRC (BANK 0) tRC tRAS (BANK 1) tRC (BANK 1) Undefined CAS latency = 3, burst length = 4 Don't Care Note 1: A8,A9 = Don’t Care. Integrated Silicon Solution, Inc. — www.issi.com 69 Rev. A1 10/11/2016 IS42S16100H, IS45S16100H Read Cycle / Page Mode T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 CLK tCKS tCK tCS tCKA tCH CKE tCHI tCL CS tCS tCH tCS tCH tCS tCH RAS CAS WE tAS A0-A9 tAH tAS (1) COLUMN o NO PRE tAH tAS A11 (1) COLUMN n tAH ROW A10 (1) COLUMN m ROW BANK 1 BANK 0 BANK 0 AND 1 NO PRE BANK 0 OR 1 BANK 1 BANK 0 BANK 1 BANK 0 NO PRE BANK 1 BANK 1 BANK 0 AUTO PRE tCS tQMD BANK 0 tCH DQM tAC tLZ tAC tOH DQ DOUT m tRCD tRAS tRC DOUT m+1 tAC tAC tAC tOH tOH tOH DOUT n DOUT n+1 DOUT o tCAC tCAC tCAC tAC tOH tOH DOUT o+1 tHZ tRQL tRP Undefined CAS latency = 3, burst length = 2 Don't Care Note 1: A8,A9 = Don’t Care. 70 Integrated Silicon Solution, Inc. — www.issi.com Rev. A1 10/11/2016 IS42S16100H, IS45S16100H Read Cycle / Page Mode; Data Masking T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T11 T10 T12 CLK tCKS tCK tCS tCKA tCH CKE tCHI tCL CS tCS tCH tCS tCH tCS tCH RAS CAS WE tAS A0-A9 tAH ROW tAS (1) COLUMN o NO PRE AUTO PRE BANK 0 AND 1 NO PRE BANK 0 OR 1 BANK 1 BANK 0 NO PRE tAH tAS A11 (1) COLUMN n tAH ROW A10 (1) COLUMN m BANK 1 BANK 0 BANK 1 BANK 1 BANK 1 BANK 0 BANK 0 BANK 0 tCS tQMD tCH tQMD DQM tAC tAC tOH tLZ DQ DOUT m tRCD tRAS tRC tCAC tCAC tAC tOH tAC tAC tOH DOUT m+1 DOUT n tOH tOH DOUT o DOUT o+1 tHZ tCAC tRQL tRP Undefined CAS latency = 3, burst length = 2 Don't Care Note 1: A8,A9 = Don’t Care. Integrated Silicon Solution, Inc. — www.issi.com 71 Rev. A1 10/11/2016 IS42S16100H, IS45S16100H Write Cycle / Page Mode T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 CLK tCKS tCK tCS tCKA tCH CKE tCHI tCL CS tCS tCH tCS tCH tCS tCH RAS CAS WE tAS A0-A9 tAH ROW tAS (1) (1) COLUMN n COLUMN o tAH ROW A10 tAH tAS A11 (1) COLUMN m AUTO PRE BANK 0 AND 1 NO PRE NO PRE BANK 1 BANK 1 NO PRE BANK 0 OR 1 BANK 1 BANK 0 BANK 0 BANK 0 BANK 1 BANK 0 BANK 0 tCS tCH DQM tDS tDH tDS DIN m DQ tDH tDS DIN m+1 tDH tDS DIN n tDH tDS DIN o tRCD tRAS tRC tDH DIN o+1 tDPL tRP Undefined CAS latency = 3, burst length = 2 Don't Care Note 1: A8,A9 = Don’t Care. 72 Integrated Silicon Solution, Inc. — www.issi.com Rev. A1 10/11/2016 IS42S16100H, IS45S16100H Write Cycle / Page Mode; Data Masking T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 CLK tCKS tCK tCS tCKA tCH CKE tCHI tCL CS tCS tCH tCS tCH tCS tCH RAS CAS WE tAS A0-A9 tAH ROW tAS (1) (1) COLUMN n COLUMN o tAH NO PRE ROW A10 tAH tAS A11 (1) COLUMN m BANK 1 BANK 0 tCS AUTO PRE BANK 0 AND 1 NO PRE BANK 1OR 0 NO PRE BANK 1 BANK 1 BANK 0 BANK 0 BANK 1 BANK 0 tCH BANK 1 BANK 0 DQM tDS tDH tDS DIN m DQ tDH tDS DIN m+1 tDH tDS DIN n tDH tDS DIN o tRCD tRAS tRC tDH DIN o+1 tDPL tRP Undefined CAS latency = 3, burst length = 2 Don't Care Note 1: A8,A9 = Don’t Care. Integrated Silicon Solution, Inc. — www.issi.com Rev. A1 10/11/2016 73 IS42S16100H, IS45S16100H Read Cycle / Clock Suspend T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 CLK tCKS tCK tCS tCKA tCH CKE tCHI tCKS tCL tCKH CS tCS tCH tCS tCH tCS tCH tAS tAH RAS CAS WE A0-A9 COLUMN m ROW tAS tAH AUTO PRE BANK 0 AND 1 tAH NO PRE BANK 0 OR 1 BANK 1 BANK 0 BANK 1 ROW A10 tAS A11 (1) BANK 1 BANK 0 tCS BANK 0 tCH tQMD DQM tAC tAC tOH DQ tOH DOUT m DOUT m+1 tLZ tRCD tHZ tCAC tRAS tRP tRC Undefined CAS latency = 3, burst length = 2 Don't Care Note 1: A8,A9 = Don’t Care. 74 Integrated Silicon Solution, Inc. — www.issi.com Rev. A1 10/11/2016 IS42S16100H, IS45S16100H Write Cycle / Clock Suspend T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 CLK tCKS tCK tCS tCKA tCH CKE tCHI tCL tCKS tCKH CS tCS tCH tCS tCH tCS tCH tAS tAH RAS CAS WE A0-A9 tAS ROW BANK 0 AND 1 tAH AUTO PRE tAH NO PRE BANK 0 OR 1 BANK 1 BANK 1 BANK 0 BANK 1 BANK 0 BANK 0 ROW ROW A10 tAS A11 (1) COLUMN m ROW BANK 1 BANK 0 tCS tCH DQM tDS tDH DIN m DQ tRCD tDS tDH DIN m+1 tDPL tRAS tRAS tRP tRC tRC Undefined CAS latency = 3, burst length = 2 Don't Care Note 1: A8,A9 = Don’t Care. Integrated Silicon Solution, Inc. — www.issi.com Rev. A1 10/11/2016 75 IS42S16100H, IS45S16100H Read Cycle / Precharge Termination T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 CLK tCKS tCK tCS tCKA tCH CKE tCHI tCL CS tCS tCH tCS tCH tCS tCH RAS CAS WE tAS A0-A9 tAH tAS ROW tAH ROW ROW A10 tAH tAS A11 (1) COLUMN m ROW BANK 0 NO PRE BANK 0 OR 1 BANK 0 BANK 0 tCS BANK 1 BANK 0 tCH tQMD DQM tAC tAC tOH DQ DOUT m tAC tOH tHZ tOH DOUT m+1 DOUT m+2 tLZ tRCD tCAC tRAS tRQL tRCD tRP tRAS tRC tRP Undefined CAS latency = 3, burst length = 2 Don't Care Note 1: A8,A9 = Don’t Care. 76 Integrated Silicon Solution, Inc. — www.issi.com Rev. A1 10/11/2016 IS42S16100H, IS45S16100H Write Cycle / Precharge Termination T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 CLK tCKS tCK tCS tCKA tCH CKE tCHI tCL CS tCS tCH tCS tCH tCS tCH tAS tAH RAS CAS WE A0-A9 COLUMN m ROW tAS ROW tAH ROW ROW A10 tAH tAS A11 (1) BANK 0 NO PRE BANK 0 OR 1 BANK 0 BANK 0 tCS tCS tCH BANK 1 BANK 0 tCH DQM tDH tDS tDS DQ DIN 0m tDH tDS DIN 0m+1 tDH DIN 0m+2 tRCD tRCD tRAS tRAS tRP tRC tRP Undefined CAS latency = 3, burst length = 4 Don't Care Note 1: A8,A9 = Don’t Care. Integrated Silicon Solution, Inc. — www.issi.com 77 Rev. A1 10/11/2016 IS42S16100H, IS45S16100H Read Cycle / Byte Operation T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 CLK tCKS tCK tCS tCKA tCH CKE tCHI tCL CS tCS tCH tCS tCH tCS tCH RAS CAS WE tAS A0-A9 tAH tAS ROW tAH AUTO PRE BANK 0 AND 1 tAH NO PRE BANK 0 OR 1 BANK 1 BANK 1 BANK 1 BANK 0 BANK 0 ROW ROW A10 tAS A11 (1) COLUMN m ROW tCS tQMD tCS tQMD BANK 1 BANK 0 tCH BANK 0 UDQM tCH LDQM tAC tLZ DQ8-15 tAC tHZ tOH tAC tLZ DOUT m+2 DOUT m tAC tLZ DQ0-7 tRCD tCAC tAC tHZ tOH DOUT m+3 tHZ tOH tOH DOUT m DOUT m+1 tQMD tRAS tRQL tRCD tRP tRAS tRP tRC Undefined CAS latency = 3, burst length = 4 Don't Care Note 1: A8,A9 = Don’t Care. 78 Integrated Silicon Solution, Inc. — www.issi.com Rev. A1 10/11/2016 IS42S16100H, IS45S16100H Write Cycle / Byte Operation T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 CLK tCKS tCK tCS tCKA tCH CKE tCHI tCL CS tCS tCH tCS tCH tCS tCH RAS CAS WE tAS A0-A9 tAH tAS tAH ROW AUTO PRE BANK 0 AND 1 NO PRE BANK 0 OR 1 BANK 1 BANK 0 BANK 1 ROW ROW A10 tAH tAS A11 (1) COLUMN m ROW BANK 1 BANK 0 tCS BANK 0 tCH BANK 1 BANK 0 UDQM tCS tCH tDS tDS tDH LDQM DQ8-15 DIN m tDH tDS DIN m+1 DIN m+3 tDH tDS DQ0-7 tDH tDH tDS DIN m DIN m+3 tRCD tDPL tRCD tRAS tRP tRAS tRP tRC Undefined CAS latency = 3, burst length = 4 Don't Care Note 1: A8,A9 = Don’t Care. Integrated Silicon Solution, Inc. — www.issi.com 79 Rev. A1 10/11/2016 IS42S16100H, IS45S16100H Read Cycle, Write Cycle / Burst Read, Single Write T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T11 T10 T12 CLK tCKS tCK tCS tCKA tCH CKE tCHI tCL CS tCS tCH tCS tCH tCS tCH RAS CAS WE tAS A0-A9 tAH tAS AUTO PRE BANK 0 AND 1 NO PRE BANK 0 OR 1 BANK 1 BANK 1 NO PRE tAH tAS A11 COLUMN n tAH ROW A10 (1) (1) COLUMN m ROW BANK 1 BANK 1 BANK 0 BANK 0 tCS BANK 0 tQMD tCH BANK 0 DQM tAC DQ tLZ tRC tAC tDS tOH tOH DOUT m DOUT m+1 tDH DIN n tHZ tCAC tDPL tRAS tRP tRC Undefined CAS latency = 3, burst length = 2 Don't Care Note 1: A8,A9 = Don’t Care. 80 Integrated Silicon Solution, Inc. — www.issi.com Rev. A1 10/11/2016 IS42S16100H, IS45S16100H ORDERING INFORMATION Commercial Range: 0°C to 70°C Frequency Speed (ns) Order Part No. Package 200 MHz 5 IS42S16100H-5T 400-mil TSOP II IS42S16100H-5TL 400-mil TSOP II, Lead-free IS42S16100H-5BL 60-ball BGA, Lead-free IS42S16100H-6T 400-mil TSOP II IS42S16100H-6TL 400-mil TSOP II, Lead-free IS42S16100H-6BL 60-ball BGA, Lead-free IS42S16100H-7T 400-mil TSOP II IS42S16100H-7TL 400-mil TSOP II, Lead-free IS42S16100H-7BL 60-ball BGA, Lead-free 166 MHz 143MHz 6 7 Industrial Range: -40°C to +85°C Frequency 166 MHz Speed (ns) 6 143MHz Order Part No. Package IS42S16100H-6TLI 400-mil TSOP II, Lead-free IS42S16100H-6BLI 60-ball BGA, Lead-free IS42S16100H-7TLI 400-mil TSOP II, Lead-free IS42S16100H-7BLI 60-ball BGA, Lead-free Please contact ISSI for leaded parts support. Automotive Range: -40°C to +85°C Frequency Speed (ns) Order Part No. Package 166 MHz 6 IS45S16100H-6TLA1 IS45S16100H-6BLAI 400-mil TSOP II, Lead-free 143MHz 7 IS45S16100H-7TLA1 400-mil TSOP II, Lead-free IS45S16100H-7BLA1 60-ball BGA, Lead-free Automotive Range: -40°C to +105°C Frequency 143MHz Speed (ns) 7 Order Part No. IS45S16100H-7TLA2 400-mil TSOP II, Lead-free IS45S16100H-7BLA2 60-ball BGA, Lead-free Integrated Silicon Solution, Inc. — www.issi.com Rev. A1 10/11/2016 Package 81 IS42S16100H, IS45S16100H Θ NoTe : 1. controlling dimension : mm Θ 2. dimension d and e1 do not include mold protrusion . 3. dimension b does not include dambar protrusion/intrusion. 4. formed leads shall be planar with respect to one another within 0.1mm at the seating plane after final test. Package Outline 09/01/2006 Rev. A1 10/11/2016 Integrated Silicon Solution, Inc. — www.issi.com 82 IS42S16100H, IS45S16100H Integrated Silicon Solution, Inc. — www.issi.com Rev. A1 10/11/2016 83