IS42S16800B-6TL

IS42S81600B IS42S16800B 16Meg x 8, 8Meg x16 128-MBIT SYNCHRONOUS DRAM ISSI MAY 2006 ® FEATURES • Clock frequency: 167, 143, 133 MHz • Fully synchronous; all signals referenced to a positive clock edge • Internal bank for hiding row access/precharge • Power supply IS42S81600B IS42S16800B • LVTTL interface • Programmable burst length – (1, 2, 4, 8, full page) • Programmable burst sequence: Sequential/Interleave • Auto Refresh (CBR) • Self Refresh with programmable refresh periods • 4096 refresh cycles every 64 ms • Random column address every clock cycle • Programmable CAS latency (2, 3 clocks) • Burst read/write and burst read/single write operations capability • Burst termination by burst stop and precharge command • Industrial Temperature Availability • Lead-free Availability VDDQ VDD 3.3V 3.3V 3.3V 3.3V OVERVIEW ISSI's 128Mb Synchronous DRAM achieves high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input.The 128Mb SDRAM is organized as follows. IS42S81600B 4M x8x4 Banks 54-pin TSOPII IS42S16800B 2M x16x4 Banks 54-pin TSOPII KEY TIMING PARAMETERS Parameter Clk Cycle Time CAS Latency = 3 CAS Latency = 2 Clk Frequency CAS Latency = 3 CAS Latency = 2 Access Time from Clock CAS Latency = 3 CAS Latency = 2 -6 6 – 167 – 5.4 – -7 7 10 143 100 5.4 6 -75E – 7.5 – 133 – 6 Unit ns ns Mhz Mhz ns ns Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. E 05/01/06 1 IS42S81600B, IS42S16800B ISSI ® DEVICE OVERVIEW The 128Mb SDRAM is a high speed CMOS, dynamic random-access memory designed to operate in 3.3V VDD and 3.3V VDDQ memory systems containing 134,217,728 bits. Internally configured as a quad-bank DRAM with a synchronous interface. Each 33,554,432-bit bank is organized as 4,096 rows by 512 columns by 16 bits or 4,096 rows by 1,024 columns by 8 bits. The 128Mb SDRAM includes an AUTO REFRESH MODE, and a power-saving, power-down mode. All signals are registered on the positive edge of the clock signal, CLK. All inputs and outputs are LVTTL compatible. The 128Mb SDRAM has the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks to hide precharge time and the capability to randomly change column addresses on each clock cycle during burst access. A self-timed row precharge initiated at the end of the burst sequence is available with the AUTO PRECHARGE function enabled. Precharge one bank while accessing one of the other three banks will hide the precharge cycles and provide seamless, high-speed, random-access operation. SDRAM read and write accesses are burst oriented starting at a selected location and continuing for a programmed number of locations in a programmed sequence. The registration of an ACTIVE command begins accesses, followed by a READ or WRITE command. The ACTIVE command in conjunction with address bits registered are used to select the bank and row to be accessed (BA0, BA1 select the bank; A0-A11 select the row). The READ or WRITE commands in conjunction with address bits registered are used to select the starting column location for the burst access. Programmable READ or WRITE burst lengths consist of 1, 2, 4 and 8 locations or full page, with a burst terminate option. FUNCTIONAL BLOCK DIAGRAM (FOR 2MX16X4 BANKS ONLY) CLK CKE CS RAS CAS WE DQML DQMH COMMAND DECODER & CLOCK GENERATOR DATA IN BUFFER 16 16 2 MODE REGISTER 12 REFRESH CONTROLLER DQ 0-15 SELF REFRESH CONTROLLER A10 A11 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 BA0 BA1 12 DATA OUT BUFFER 16 16 VDD/VDDQ Vss/VssQ REFRESH COUNTER 4096 4096 4096 4096 ROW DECODER MULTIPLEXER MEMORY CELL ARRAY 12 ROW ADDRESS LATCH 12 ROW ADDRESS BUFFER BANK 0 SENSE AMP I/O GATE COLUMN ADDRESS LATCH 9 512 (x 16) BANK CONTROL LOGIC BURST COUNTER COLUMN DECODER COLUMN ADDRESS BUFFER 9 2 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. E 05/01/06 IS42S81600B, IS42S16800B ISSI ® PIN CONFIGURATIONS 54 pin TSOP - Type II for x8 VDD DQ0 VDDQ NC DQ1 VSSQ NC DQ2 VDDQ NC DQ3 VSSQ NC VDD NC WE CAS RAS CS BA0 BA1 A10 A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 VSS DQ7 VSSQ NC DQ6 VDDQ NC DQ5 VSSQ NC DQ4 VDDQ NC VSS NC DQM CLK CKE NC A11 A9 A8 A7 A6 A5 A4 VSS PIN DESCRIPTIONS A0-A11 A0-A9 BA0, BA1 DQ0 to DQ7 CLK CKE CS RAS CAS Row Address Input Column Address Input Bank Select Address Data I/O System Clock Input Clock Enable Chip Select Row Address Strobe Command Column Address Strobe Command WE DQM VDD Vss VDDQ VssQ NC Write Enable Data Input/Output Mask Power Ground Power Supply for I/O Pin Ground for I/O Pin No Connection Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. E 05/01/06 3 IS42S81600B, IS42S16800B ISSI ® PIN CONFIGURATIONS 54 pin TSOP - Type II for x16 VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 VDD LDQM WE CAS RAS CS BA0 BA1 A10 A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 VSS NC UDQM CLK CKE NC A11 A9 A8 A7 A6 A5 A4 VSS PIN DESCRIPTIONS A0-A11 A0-A8 BA0, BA1 DQ0 to DQ15 CLK CKE CS RAS CAS Row Address Input Column Address Input Bank Select Address Data I/O System Clock Input Clock Enable Chip Select Row Address Strobe Command Column Address Strobe Command WE DQML DQMH VDD Vss VDDQ VssQ NC Write Enable x16 Lower Byte, Input/Output Mask x16 Upper Byte, Input/Output Mask Power Ground Power Supply for I/O Pin Ground for I/O Pin No Connection 4 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. E 05/01/06 IS42S81600B, PIN FUNCTIONS Symbol A0-A11 IS42S16800B ISSI Function (In Detail) ® Type Input Pin Address Inputs: A0-A11 are sampled during the ACTIVE command (row-address A0-A11) and READ/WRITE command (column address A0-A9 (x8), or A0-A8 (x16); with A10 defining auto precharge) to select one location out of the memory array in the respective bank. A10 is sampled during a PRECHARGE command to determine if all banks are to be precharged (A10 HIGH) or bank selected by BA0, BA1 (LOW). The address inputs also provide the op-code during a LOAD MODE REGISTER command. Bank Select Address: BA0 and BA1 defines which bank the ACTIVE, READ, WRITE or PRECHARGE command is being applied. CAS, in conjunction with the RAS and WE, forms the device command. See the "Command Truth Table" for details on device commands. The CKE input determines whether the CLK input is enabled. The next rising edge of the CLK signal will be valid when is CKE HIGH and invalid when LOW. When CKE is LOW, the device will be in either power-down mode, clock suspend mode, or self refresh mode. CKE is an asynchronous input. CLK is the master clock input for this device. Except for CKE, all inputs to this device are acquired in synchronization with the rising edge of this pin. The CS input determines whether command input is enabled within the device. Command input is enabled when CS is LOW, and disabled with CS is HIGH. The device remains in the previous state when CS is HIGH. DQML and DQMH control the lower and upper bytes of the I/O buffers. In read mode,DQML and DQMH control the output buffer. WhenDQML orDQMH is LOW, the corresponding buffer byte is enabled, and when HIGH, disabled. The outputs go to the HIGH impedance state whenDQML/DQMH is HIGH. This function corresponds to OE in conventional DRAMs. In write mode,DQML and DQMH control the input buffer. When DQML or DQMH is LOW, the corresponding buffer byte is enabled, and data can be written to the device. WhenDQML or DQMH is HIGH, input data is masked and cannot be written to the device. For IS42S16800B only. For IS42S81600B only. Data on the Data Bus is latched on DQ pins during Write commands, and buffered for output after Read commands. RAS, in conjunction with CAS and WE, forms the device command. See the "Command Truth Table" item for details on device commands. WE, in conjunction with RAS and CAS, forms the device command. See the "Command Truth Table" item for details on device commands. VDDQ is the output buffer power supply. VDD is the device internal power supply. VSSQ is the output buffer ground. VSS is the device internal ground. BA0, BA1 CAS CKE Input Pin Input Pin Input Pin CLK CS Input Pin Input Pin DQML, DQMH Input Pin DQM DQ0-DQ7 or DQ0-DQ15 RAS WE VDDQ VDD VSSQ VSS Input Pin Input/Output Input Pin Input Pin Power Supply Pin Power Supply Pin Power Supply Pin Power Supply Pin Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. E 05/01/06 5 IS42S81600B, IS42S16800B ISSI ® GENERAL DESCRIPTION READ The READ command selects the bank from BA0, BA1 inputs and starts a burst read access to an active row. Inputs A0-A9 (x8); A0-A8 (x16) provides the starting column location. When A10 is HIGH, this command functions as an AUTO PRECHARGE command. When the auto precharge is selected, the row being accessed will be precharged at the end of the READ burst. The row will remain open for subsequent accesses when AUTO PRECHARGE is not selected. DQ’s read data is subject to the logic level on the DQM inputs two clocks earlier. When a given DQM signal was registered HIGH, the corresponding DQ’s will be HighZ two clocks later. DQ’s will provide valid data when the DQM signal was registered LOW. PRECHARGE function in conjunction with a specific READ or WRITE command. For each individual READ or WRITE command, auto precharge is either enabled or disabled. AUTO PRECHARGE does not apply except in full-page burst mode. Upon completion of the READ or WRITE burst, a precharge of the bank/row that is addressed is automatically performed. AUTO REFRESH COMMAND This command executes the AUTO REFRESH operation. The row address and bank to be refreshed are automatically generated during this operation. The stipulated period (tRC) is required for a single refresh operation, and no other commands can be executed during this period. This command is executed at least 4096 times for every 64ms. During an AUTO REFRESH command, address bits are “Don’t Care”. This command corresponds to CBR Auto-refresh. WRITE A burst write access to an active row is initiated with the WRITE command. BA0, BA1 inputs selects the bank, and the starting column location is provided by inputs A0-A9 (x8); A0-A8 (x16). Whether or not AUTO-PRECHARGE is used is determined by A10. The row being accessed will be precharged at the end of the WRITE burst, if AUTO PRECHARGE is selected. If AUTO PRECHARGE is not selected, the row will remain open for subsequent accesses. A memory array is written with corresponding input data on DQ’s and DQM input logic level appearing at the same time. Data will be written to memory when DQM signal is LOW. When DQM is HIGH, the corresponding data inputs will be ignored, and a WRITE will not be executed to that byte/ column location. BURST TERMINATE The BURST TERMINATE command forcibly terminates the burst read and write operations by truncating either fixedlength or full-page bursts and the most recently registered READ or WRITE command prior to the BURST TERMINATE. COMMAND INHIBIT COMMAND INHIBIT prevents new commands from being executed. Operations in progress are not affected, apart from whether the CLK signal is enabled NO OPERATION When CS is low, the NOP command prevents unwanted commands from being registered during idle or wait states. PRECHARGE The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. BA0, BA1 can be used to select which bank is precharged or they are treated as “Don’t Care”. A10 determined whether one or all banks are precharged. After executing this command, the next command for the selected bank(s) is executed after passage of the period tRP, which is the period required for bank precharging. Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank. LOAD MODE REGISTER During the LOAD MODE REGISTER command the mode register is loaded from A0-A11. This command can only be issued when all banks are idle. ACTIVE COMMAND When the ACTIVE COMMAND is activated, BA0, BA1 inputs selects a bank to be accessed, and the address inputs on A0-A11 selects the row. Until a PRECHARGE command is issued to the bank, the row remains open for accesses. AUTO PRECHARGE The AUTO PRECHARGE function ensures that the precharge is initiated at the earliest valid stage within a burst. This function allows for individual-bank precharge without requiring an explicit command. A10 to enable the AUTO 6 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. E 05/01/06 IS42S81600B, IS42S16800B ISSI CS H L L L L L L L L L L L L RAS × H H H H H H L L L L L L CAS CAS × H H L L L L H H H L L L WE WE × H L H H L L H L L H H L BA1 × × × V V V V V V × × × L BA0 × × × V V V V V V × × × L A10 × × × L H L H V L H × × L A11 A9 - A0 × × × V V V V V × × × × V ® COMMAND TRUTH TABLE CKE Function n–1 Device deselect (DESL) H No operation (NOP) H Burst stop (BST) H Read H Read with auto precharge H Write H Write with auto precharge H Bank activate (ACT) H Precharge select bank (PRE) H Precharge all banks (PALL) H CBR Auto-Refresh (REF) H Self-Refresh (SELF) H Mode register set (MRS) H n × × × × × × × × × × H L × Note: H=VIH, L=VIL x= VIH or VIL, V = Valid Data. DQM TRUTH TABLE Function Data write / output enable Data mask / output disable Upper byte write enable / output enable Lower byte write enable / output enable Upper byte write inhibit / output disable Lower byte write inhibit / output disable Note: H=VIH, L=VIL x= VIH or VIL, V = Valid Data. CKE n-1 H H H H H H n × × × × × × DQM U L H L × H × L L H × L × H Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. E 05/01/06 7 IS42S81600B, IS42S16800B ISSI CKE n–1 H L L H H H L L L n L L H H L L H H H CS × × × L L × L H × RAS × × × L L × H × × CAS × × × L L × H × × WE × × × H H × H × × Address × × × × × × × × × ® CKE TRUTH TABLE Current State /Function Activating Clock suspend mode entry Any Clock suspend mode Clock suspend mode exit Auto refresh command Idle (REF) Self refresh entry Idle (SELF) Power down entry Idle Self refresh exit Power down exit Note: H=VIH, L=VIL x= VIH or VIL, V = Valid Data. 8 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. E 05/01/06 IS42S81600B, IS42S16800B ISSI Address X X X BA, CA, A10 A, CA, A10 BA, RA BA, A10 X OC, BA1=L X X X BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X OC, BA X X X BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X OC, BA X X X BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X OC, BA Command DESL NOP BST READ/READA WRIT/ WRITA ACT PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/ WRITA ACT PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA RA ACT PRE/PALL REF/SELF MRS Action Nop or Power Down(2) Nop or Power Down(2) Nop or Power Down ILLEGAL (3) ILLEGAL(3) Row activating Nop ® FUNCTIONAL TRUTH TABLE Current State Idle CS H L L L L L L L L Row Active H L L L L L L L L Read H L L L L L L L L Write H L L L L L L L L RAS CAS X H H H H L L L L X H H H H L L L L X H H H H L L L L X H H H H L L L L X H H L L H H L L X H H L L H H L L X H H L L H H L L X H H L L H H L L WE X H L H L H L H L X H L H L H L H L X H L H L H L H L X H L H L H L H L Auto refresh or Self-refresh(4) Mode register set Nop Nop Nop Begin read Begin write ILLEGAL (3) Precharge Precharge all banks(6) ILLEGAL ILLEGAL Continue burst to end to Row active Continue burst to end Row Row active Burst stop, Row active Terminate burst, begin new read (7) Terminate burst, begin write (7,8) ILLEGAL (3) Terminate burst Precharging ILLEGAL ILLEGAL Continue burst to end Write recovering Continue burst to end Write recovering Burst stop, Row active Terminate burst, start read : Determine AP (7,8) Terminate burst, new write : Determine AP (7) ILLEGAL (3) Terminate burst Precharging ILLEGAL ILLEGAL (9) (5) (5) Note: H=VIH, L=VIL x= VIH or VIL, V = Valid Data, BA= Bank Address, CA+Column Address, RA=Row Address, OC= Op-Code Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. E 05/01/06 9 IS42S81600B, IS42S16800B ISSI Address × x × BA, CA, A10 BA, CA, A10 BA, RA BA, A10 × OC, BA × × × BA, CA, A10 BA, CA, A10 BA, RA BA, A10 × OC, BA × × × BA, CA, A10 BA, CA, A10 BA, RA BA, A10 × OC, BA × × × BA, CA, A10 BA, CA, A10 BA, RA BA, A10 × OC, BA Command DESL NOP BST READ/READA WRIT/ WRITA ACT PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/ WRITA ACT PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS Action ® FUNCTIONAL TRUTH TABLE Continued: Current State Read with auto Precharging CS H L L L L L L L L Write with Auto Precharge H L L L L L L L L Precharging H L L L L L L L L Row Activating H L L L L L L L L RAS CAS × H H H H L L L L × H H H H L L L L × H H H H L L L L × H H H H L L L L × H H L L H H L L × H H L L H H L L × H H L L H H L L × H H L L H H L L WE × H L H L H L H L × H L H L H L H L × H L H L H L H L × H L H L H L H L Continue burst to end, Precharge Continue burst to end, Precharge ILLEGAL ILLEGAL (11) ILLEGAL (11) ILLEGAL (3) ILLEGAL (11) ILLEGAL ILLEGAL Continue burst to end, Write recovering with auto precharge Continue burst to end, Write recovering with auto precharge ILLEGAL ILLEGAL(11) ILLEGAL (11) ILLEGAL (3,11) ILLEGAL (3,11) ILLEGAL ILLEGAL Nop, Enter idle after tRP Nop, Enter idle after tRP Nop, Enter idle after tRP ILLEGAL (3) ILLEGAL (3) ILLEGAL(3) Nop Enter idle after tRP ILLEGAL ILLEGAL Nop, Enter bank active after tRCD Nop, Enter bank active after tRCD Nop, Enter bank active after tRCD ILLEGAL (3) ILLEGAL (3) ILLEGAL (3,9) ILLEGAL (3) ILLEGAL ILLEGAL Note: H=VIH, L=VIL x= VIH or VIL, V = Valid Data, BA= Bank Address, CA+Column Address, RA=Row Address, OC= Op-Code 10 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. E 05/01/06 IS42S81600B, CS H L L L L L L L L Write Recovering with Auto Precharge H L L L L L L L L Refresh H L L L L L L L Mode Register Accessing H L L L L IS42S16800B RAS CAS × H H H H L L L L × H H H H L L L L × H H H L L L L × H H H L × H H L L H H L L × H H L L H H L L × H L L H H L L × H H L × WE × H L H L H L H L × H L H L H L H L × × H L H L H L × H L × × ISSI Address × × × BA, CA, A10 BA, CA, A10 BA, RA BA, A10 × OC, BA × × × BA, CA, A10 BA, CA, A10 BA, RA BA, A10 × OC, BA × × BA, CA, A10 BA, CA, A10 BA, RA BA, A10 × OC, BA × × × BA, CA, A10 BA, RA Command DESL NOP BST READ/READA WRIT/ WRITA ACT PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP/BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP BST READ/WRITE ACT/PRE/PALL REF/MRS Action Nop, Enter row active after tDPL Nop, Enter row active after tDPL Nop, Enter row active after tDPL Begin read (8) Begin new write ILLEGAL (3) ILLEGAL (3) ILLEGAL ILLEGAL Nop, Enter precharge after tDPL Nop, Enter precharge after tDPL Nop, Enter row active after tDPL ILLEGAL(3,8,11) ILLEGAL (3,11) ILLEGAL (3,11) ILLEGAL (3,11) ILLEGAL ILLEGAL Nop, Enter idle after tRC Nop, Enter idle after tRC ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Nop, Enter idle after 2 clocks Nop, Enter idle after 2 clocks ILLEGAL ILLEGAL ILLEGAL ® FUNCTIONAL TRUTH TABLE Continued: Current State Write Recovering Note: H=VIH, L=VIL x= VIH or VIL, V = Valid Data, BA= Bank Address, CA+Column Address, RA=Row Address, OC= Op-Code Notes: 1. All entries assume that CKE is active (CKEn-1=CKEn=H). 2. If both banks are idle, and CKE is inactive (Low), the device will enter Power Down mode. All input buffers except CKE will be disabled. 3. Illegal to bank in specified states; Function may be legal in the bank indicated by Bank Address (BA), depending on the state of that bank. 4. If both banks are idle, and CKE is inactive (Low), the device will enter Self-Refresh mode. All input buffers except CKE will be disabled. 5. Illegal if tRCD is not satisfied. 6. Illegal if tRAS is not satisfied. 7. Must satisfy burst interrupt condition. 8. Must satisfy bus contention, bus turn around, and/or write recovery requirements. 9. Must mask preceding data which don’t satisfy tDPL. 10. Illegal if tRRD is not satisfied. 11. Illegal for single bank, but legal for other banks. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. E 05/01/06 11 IS42S81600B, IS42S16800B ISSI CKE n-1 H L L L L L H H H H H H H H L L H L L H H H H H H H H H H L H H L L n X H H H H L H H H H L L L L H L X H L H H H H H L L L L L X H L H L CS X H L L L X H L L L H L L L X X X X X H L L L L H L L L L X X X X X RAS X X H H L X X H H L X H H L X X X X X X H L L L X H L L L X X X X X CAS X X H L X X X H L X X H L X X X X X X X X H L L X X H L L X X X X X WE X X X X X X X X X X X X X X X X X X X X X X H L X X X H L X X X X X Address X X X X X X X X X X X X X X X X — X X — — — X Op - Code — — — X Op - Code X X X X X ® CKE RELATED COMMAND TRUTH TABLE(1) Current State Self-Refresh (S.R.) Self-Refresh Recovery Power-Down(P.D.) Both Banks Idle Any state other than listed above Operation INVALID, CLK (n - 1) would exit S.R. Self-Refresh Recovery(2) Self-Refresh Recovery(2) Illegal Illegal Maintain S.R. Idle After tRC Idle After tRC Illegal Illegal Begin clock suspend next cycle(5) Begin clock suspend next cycle(5) Illegal Illegal Exit clock suspend next cycle(2) Maintain clock suspend INVALID, CLK (n - 1) would exit P.D. EXIT P.D. --> Idle(2) Maintain power down mode Refer to operations in Operative Command Table Refer to operations in Operative Command Table Refer to operations in Operative Command Table Auto-Refresh Refer to operations in Operative Command Table Refer to operations in Operative Command Table Refer to operations in Operative Command Table Refer to operations in Operative Command Table Self-Refresh(3) Refer to operations in Operative Command Table Power-Down(3) Refer to operations in Operative Command Table Begin clock suspend next cycle(4) Exit clock suspend next cycle Maintain clock suspend Notes: 1. H : High level, L : low level, X : High or low level (Don’t care). 2. CKE Low to High transition will re-enable CLK and other inputs asynchronously. A minimum setup time must be satisfied before any command other than EXIT. 3. Power down and Self refresh can be entered only from the both banks idle state. 4. Must be legal command as defined in Operative Command Table. 5. Illegal if tSRX is not satisfied. 12 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. E 05/01/06 IS42S81600B, IS42S16800B ISSI ® STATE DIAGRAM Self Refresh SELF SELF exit Mode Register Set MRS IDLE REF CBR (Auto) Refresh CKE CKE ACT Power Down CKE Row Active BST CKE BST Active Power Down th rge Write Write Read Au to Re wi ha rite W WRITE SUSPEND Au CKE WRITE CKE to Pr ec Read CKE READ CKE h wit ad arge h ec Pr Write Read READ SUSPEND POWER ON Precharge Precharge PR E( Pr ec ha rge WRITEA SUSPEND ter WRITEA CKE mi CKE na tio Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. E 05/01/06 RR E( Pre a ch rge m ter ina n) tio n) CKE READA CKE READA SUSPEND Automatic sequence Manual Input 13 IS42S81600B, IS42S16800B ISSI Rating –0.5 to +4.6 –0.5 to +4.6 –0.5 to VDD + 0.5 –1.0 to VDDQ + 0.5 1 50 0 to +70 –40 to +85 –65 to +150 Unit V V V V W mA °C °C ® ABSOLUTE MAXIMUM RATINGS(1) Symbol VDD MAX VDDQ MAX VIN VOUT PD MAX ICS TOPR TSTG Parameters Maximum Supply Voltage Maximum Supply Voltage for Output Buffer Input Voltage Output Voltage Allowable Power Dissipation Output Shorted Current Operating Temperature Com. Ind. Storage Temperature Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. All voltages are referenced to Vss. DC RECOMMENDED OPERATING CONDITIONS Symbol VDD VDDQ VIH(1) VIL(2) Note: 1. VIH (max) = VDDQ +1.2V (PULSE WIDTH < 3NS). 2. VIL (min) = -1.2V (PULSE WIDTH < 3NS). 3. All voltages are referenced to Vss. Parameter Supply Voltage I/O Supply Voltage Input High Voltage Input Low Voltage Min. 3.0 3.0 2.0 -1.2 Typ. 3.3 3.3 — — Max. 3.6 3.6 VDDQ + 1.2 +0.8 Unit V V V V CAPACITANCE CHARACTERISTICS (At TA = 0 to +25°C, VDD = VDDQ = 3.3 ± 0.3V) Symbol CIN1 CIN2 CI/O Parameter Input Capacitance: CLK Input Capacitance:All other input pins Data Input/Output Capacitance:I/Os Min. -6 2.5 2.5 4.0 3.5 3.8 6.5 Max. -7/-75E 4.0 5.0 6.5 Unit pF pF pF 14 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. E 05/01/06 IS42S81600B, IS42S16800B ISSI x8 x16 x8 / x16 x8 / x16 x8 / x16 x8 / x16 x8 / x16 x8 / x16 x8 x16 x8/ x16 x8 / x16 -6 120 140 2 1 25 15 30 20 170 180 180 2 -7 100 120 2 1 25 15 30 20 120 130 160 2 -75E 100 120 2 1 25 15 30 20 120 130 160 2 Unit mA mA mA mA mA mA mA mA mA mA mA mA ® DC ELECTRICAL CHARACTERISTICS 1 (Recommended Operation Conditions unless otherwise noted.) Symbol IDD1 (1) IDD2P IDD2PS IDD2N (2) IDD2NS IDD3N (2) IDD3NS IDD4 IDD5 IDD6 Notes: 1. IDD (MAX) is specified at the output open condition. 2. Input signals are changed one time during 30ns. Parameter Operating Current Precharge Standby Current (In Power-Down Mode) Precharge Standby Current (In Power-Down Mode) Precharge Standby Current (In Non Power-Down Mode) Precharge Standby Current (In Non Power-Down Mode) Active Standby Current (In Non Power-Down Mode) Active Standby Current (In Non Power-Down Mode) Operating Current Auto-Refresh Current Self-Refresh Current Test Condition One bank active, CL = 3, BL = 1, tCLK = tCLK (min), tRC = tRC (min) CKE ≤ VIL (MAX), tCK = 15ns CKE ≤ VIL (MAX), CLK ≤ VIL (MAX) CS ≥ Vcc - 0.2V, CKE ≥ VIH (MIN) tCK = 15ns CS ≥ Vcc - 0.2V, CKE ≥ VIH (MIN) or CKE ≤ VIL (MAX), All inputs stable CS ≥ Vcc - 0.2V, CKE ≥ VIH (MIN) tCK = 15ns CS ≥ Vcc - 0.2V, CKE ≥ VIH (MIN) or CKE ≤ VIL (MAX), All inputs stable All banks active, BL = 4, CL = 3, tCK = tCK (min) tRC = tRC (min), tCLK = tCLK (min) CKE ≤ 0.2V DC ELECTRICAL CHARACTERISTICS 2 (Recommended Operation Conditions unless otherwise noted.) Symbol IIL IOL VOH VOL Parameter Input Leakage Current Output Leakage Current Output High Voltage Level Output Low Voltage Level Test Condition 0V ≤ Vin ≤ Vcc, with pins other than the tested pin at 0V Output is disabled, 0V ≤ Vout ≤ Vcc, IOH = -2mA IOL = 2mA Min -10 -5 2.4 — Max 10 5 — 0.4 Unit μA μA V V Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. E 05/01/06 15 IS42S81600B, IS42S16800B (1,2,3) ISSI Min. -6 Max. — — 5.4 — — — — — — 5.4 — — — — — — — — — 100K — — — — — — — — 10 64 Min. 7 10 — — 2.5 2.5 2.7 2.7 0 2.7 1.5 0.8 1.5 0.8 1.5 0.8 1.5 0.8 67.5 45 20 20 14 14 35 15 7.5 7.5 1 — -7 Max. — — 5.4 6 — — — — — 5.4 — — — — — — — — — 100K — — — — — — — — 10 64 -75E Min. Max. — 7.5 — — 2.5 2.5 — 2.7 0 2.7 1.5 0.8 1.5 0.8 1.5 0.8 1.5 0.8 67.5 45 20 20 14 14 35 15 7.5 7.5 1 — — — — 6 — — — — — 5.4 — — — — — — — — — 100K — — — — — — — — 10 64 6 — — — 2.5 2.5 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ® AC ELECTRICAL CHARACTERISTICS Symbol Parameter tCK3 tCK2 tAC3 tAC2 tCHI tCL tOH3 tOH2 tLZ tHZ tDS tDH tAS tAH tCKS tCKH tCS tCH tRC tRAS tRP tRCD tRRD tDPL tDAL tMRD tDDE tSRX tT tREF Clock Cycle Time Access Time From CLK CLK HIGH Level Width CLK LOW Level Width Output Data Hold Time Output LOW Impedance Time Output HIGH Impedance Time Input Data Setup Time(2) Input Data Hold Time(2) Address Setup Time Address Hold Time CKE Setup Time CKE Hold Time (2) (2) (2) (2) Units CAS Latency = 3 CAS Latency = 2 CAS Latency = 3 CAS Latency = 2 CAS Latency = 3 CAS Latency = 2 2.7 — 0 2.7 1.5 0.8 1.5 0.8 1.5 0.8 (2) Command Setup Time (CS, RAS, CAS, WE, DQM) Command Period (REF to REF / ACT to ACT) Command Period (ACT to PRE) Command Period (PRE to ACT) Command Period (ACT [0] to ACT[1]) Input Data To Precharge Command Delay time Input Data To Active / Refresh Command Delay time (During Auto-Precharge) Mode Register Program Time Power Down Exit Setup Time Self-Refresh Exit Time Transition Time Refresh Cycle Time (4096) 1.5 0.8 60 42 18 12 12 27 12 6 6 1 — Command Hold Time (CS, RAS, CAS, WE, DQM)(2) Active Command To Read / Write Command Delay Time 15 Notes: 1. The power-on sequence must be executed before starting memory operation. 2. Measured with tT = 1 ns. If clock rising time is longer than 1ns, (tR /2 - 0.5) ns should be added to the parameter. 3. The reference level is 1.4V when measuring input signal timing. Rise and fall times are measured between VIH(min.) and VIL (max). 16 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. E 05/01/06 IS42S81600B, IS42S16800B ISSI UNITS 6 167 3 3 6 — 10 7 3 2 1 2 5 3 — 0 3 — 0 -2 — 2 0 2 CAS Latency = 3 CAS Latency = 2 7 143 3 3 6 — 10 7 3 2 1 2 5 3 — 0 3 — 0 –2 — 2 0 2 7.5 133 2 3 — 5 9 6 3 2 1 2 5 — 2 0 — 2 0 — -1 2 0 2 10 100 2 2 — 4 7 5 2 2 1 2 4 — 2 0 — 2 0 — -1 2 0 2 ns MHz cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle ® OPERATING FREQUENCY / LATENCY RELATIONSHIPS SYMBOL PARAMETER — — tCAC tRCD tRAC tRC tRAS tRP tRRD tCCD tDPL tDAL tRBD tWBD tRQL tWDL tPQL tQMD tDMD tMRD Clock Cycle Time Operating Frequency (CAS Latency = 3) CAS Latency Active Command To Read/Write Command Delay Time RAS Latency (tRCD + tCAC) Command Period (REF to REF / ACT to ACT) Command Period (ACT to PRE) Command Period (PRE to ACT) Command Period (ACT[0] to ACT [1]) Column Command Delay Time (READ, READA, WRIT, WRITA) Input Data To Precharge Command Delay Time Input Data To Active/Refresh Command Delay Time (During Auto-Precharge) Burst Stop Command To Output in HIGH-Z Delay Time (Read) CAS Latency = 3 CAS Latency = 2 Burst Stop Command To Input in Invalid Delay Time (Write) Precharge Command To Output in HIGH-Z Delay Time (Read) CAS Latency = 3 CAS Latency = 2 Precharge Command To Input in Invalid Delay Time (Write) Last Output To Auto-Precharge Start Time (Read) CAS Latency = 3 CAS Latency = 2 DQM To Output Delay Time (Read) DQM To Input Delay Time (Write) Mode Register Set To Command Delay Time Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. E 05/01/06 17 IS42S81600B, IS42S16800B ISSI Output Load ® AC TEST CONDITIONS Input Load tCK tCHI 3.0V tCL 1.4V CLK 1.4V 0V tCS 3.0V tCH Z = 50Ω Output 50 pF 50Ω INPUT 1.4V 0V tOH OUTPUT 1.4V tAC 1.4V AC TEST CONDITIONS Parameter AC Input Levels Input Rise and Fall Times Input Timing Reference Level Output Timing Measurement Reference Level Rating 0V to 3.0V 1 ns 1.4V 1.4V 18 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. E 05/01/06 IS42S81600B, IS42S16800B Initialization ISSI ® FUNCTIONAL DESCRIPTION The 128Mb SDRAMs are quad-bank DRAMs which operate at 3.3V and include a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the 33,554,432-bit banks is organized as 4,096 rows by 512 columns by 16 bits or 4,096 rows by 1,024 columns by 8 bits. Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0 and BA1 select the bank, A0-A11 select the row). The address bits A0-A9 (x8); A0-A8 (x16) registered coincident with the READ or WRITE command are used to select the starting column location for the burst access. Prior to normal operation, the SDRAM must be initialized. The following sections provide detailed information covering device initialization, register definition, command descriptions and device operation. SDRAMs must be powered up and initialized in a predefined manner. The 128M SDRAM is initialized after the power is applied to VDD and VDDQ (simultaneously) and the clock is stable with DQM High and CKE High. A 100µs delay is required prior to issuing any command other than a COMMAND INHIBIT or a NOP. The COMMAND INHIBIT or NOP may be applied during the 100us period and should continue at least through the end of the period. With at least one COMMAND INHIBIT or NOP command having been applied, a PRECHARGE command should be applied once the 100µs delay has been satisfied. All banks must be precharged. This will leave all banks in an idle state after which at least two AUTO REFRESH cycles must be performed. After the AUTO REFRESH cycles are complete, the SDRAM is then ready for mode register programming. The mode register should be loaded prior to applying any operational command because it will power up in an unknown state. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. E 05/01/06 19 IS42S81600B, IS42S16800B ISSI To+1 tCL Tp+1 Tp+2 Tp+3 ® INITIALIZE AND LOAD MODE REGISTER(1) T0 CLK tCK tCKS tCKH CKE tCMH tCMS COMMAND DQM/ DQML, DQMH NOP T1 Tn+1 tCH tCMH tCMS PRECHARGE tCMH tCMS AUTO REFRESH NOP AUTO REFRESH NOP Load MODE REGISTER NOP ACTIVE tAS tAH A0-A9, A11 ALL BANKS A10 SINGLE BANK BA0, BA1 DQ tRP T Power-up: VCC and CLK stable T = 100µs Min. Precharge all banks AUTO REFRESH AUTO REFRESH Program MODE REGISTER (2, 3, 4) DON'T CARE tRC tRC tMRD ALL BANKS CODE tAS tAH CODE tAS tAH CODE BANK ROW ROW Notes: 1. If CS is High at clock High time, all commands applied are NOP. 2. The Mode register may be loaded prior to the Auto-Refresh cycles if desired. 3. JEDEC and PC100 specify three clocks. 4. Outputs are guaranteed High-Z after the command is issued. 20 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. E 05/01/06 IS42S81600B, IS42S16800B ISSI T2 tCL tCH Tn+1 To+1 ® AUTO-REFRESH CYCLE T0 CLK tCKS tCKH CKE tCMS tCMH COMMAND DQM/ DQML, DQMH A0-A9, A11 ALL BANKS A10 SINGLE BANK BA0, BA1 DQ BANK(s) tAS tAH High-Z tRP tRC tRC DON'T CARE Notes: 1. CAS latency = 2, 3 T1 tCK PRECHARGE NOP Auto Refresh NOP Auto Refresh NOP ACTIVE ROW ROW BANK Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. E 05/01/06 21 IS42S81600B, IS42S16800B ISSI T2 Tn+1 To+1 To+2 tCL tCKS ≥ tRAS tCKS ® SELF-REFRESH CYCLE T0 CLK tCK tCKS tCKH CKE tCMS tCMH COMMAND DQM/ DQML, DQMH A0-A9, A11 ALL BANKS A10 SINGLE BANK tAS tAH BA0, BA1 BANK PRECHARGE T1 tCH NOP Auto Refresh NOP NOP Auto Refresh DQ High-Z tRP Precharge all active banks Enter self refresh mode tSRX CLK stable prior to exiting Exit self refresh mode self refresh mode (Restart refresh time base) DON'T CARE 22 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. E 05/01/06 IS42S81600B, IS42S16800B ISSI ® REGISTER DEFINITION Mode Register The mode register is used to define the specific mode of operation of the SDRAM. This definition includes the selection of a burst length, a burst type, a CAS latency, an operating mode and a write burst mode, as shown in MODE REGISTER DEFINITION. The mode register is programmed via the LOAD MODE REGISTER command and will retain the stored information until it is programmed again or the device loses power. Mode register bits M0-M2 specify the burst length, M3 specifies the type of burst (sequential or interleaved), M4- M6 specify the CAS latency, M7 and M8 specify the operating mode, M9 specifies the WRITE burst mode, and M10 and M11 are reserved for future use. The mode register must be loaded when all banks are idle, and the controller must wait the specified time before initiating the subsequent operation. Violating either of these requirements will result in unspecified operation. MODE REGISTER DEFINITION BA1 BA0 A11 A10 (1) A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus Mode Register (Mx) Reserved B urst Length M2 0 0 0 0 1 1 1 1 Burst Type M3 0 1 Latency Mode M6 M5 M4 0 0 0 0 1 1 1 1 Operating Mode M8 M7 00 —— M6-M0 Defined — Mode Standard Operation All Other States Reserved 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 CAS Latency Reserved Reserved 2 3 Reserved Reserved Reserved Reserved Type Sequential Interleaved M1 M0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 M3=0 1 2 4 8 Reserved Reserved Reserved Full Page M3=1 1 2 4 8 Reserved Reserved Reserved Reserved Write Burst Mode M9 0 1 Mode Programmed Burst Length Single Location Access 1. To ensure compatibility with future devices, should program BA1, BA0, A11, A10 = "0" Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. E 05/01/06 23 IS42S81600B, BURST LENGTH IS42S16800B ISSI ® Read and write accesses to the SDRAM are burst oriented, with the burst length being programmable, as shown in MODE REGISTER DEFINITION. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst lengths of 1, 2, 4 or 8 locations are available for both the sequential and the interleaved burst types, and a full-page burst is available for the sequential type. The full-page burst is used in conjunction with the BURST TERMINATE command to generate arbitrary burst lengths. Reserved states should not be used, as unknown operation or incompatibility with future versions may result. When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, mean- ing that the burst will wrap within the block if a boundary is reached. The block is uniquely selected by A1-A8 (x16) when the burst length is set to two; by A2-A8 (x16) when the burst length is set to four; and by A3-A8 (x16) when the burst length is set to eight. The remaining (least significant) address bit(s) is (are) used to select the starting location within the block. Full-page bursts wrap within the page if the boundary is reached. Burst Type Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit M3. The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in BURST DEFINITION table. BURST DEFINITION Burst Length 2 A1 0 4 0 1 1 A2 0 0 0 8 0 1 1 1 1 Full Page (y) n = A0-A7 (location 0-y) A1 0 0 1 1 0 0 1 1 Starting Column Address A0 0 1 A0 0 1 0 1 A0 0 1 0 1 0 1 0 1 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 Cn, Cn + 1, Cn + 2 Cn + 3, Cn + 4... …Cn - 1, Cn… 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 Not Supported 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 0-1 1-0 0-1 1-0 Order of Accesses Within a Burst Type = Sequential Type = Interleaved 24 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. E 05/01/06 IS42S81600B, CAS Latency IS42S16800B Operating Mode ISSI ® The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data. The latency can be set to two or three clocks. If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available by clock edge n + m. The DQs will start driving as a result of the clock edge one cycle earlier (n + m - 1), and provided that the relevant access times are met, the data will be valid by clock edge n + m. For example, assuming that the clock cycle time is such that all relevant access times are met, if a READ command is registered at T0 and the latency is programmed to two clocks, the DQs will start driving after T1 and the data will be valid by T2, as shown in CAS Latency diagrams. The Allowable Operating Frequency table indicates the operating frequencies at which each CAS latency setting can be used. Reserved states should not be used as unknown operation or incompatibility with future versions may result. The normal operating mode is selected by setting M7 and M8 to zero; the other combinations of values for M7 and M8 are reserved for future use and/or test modes. The programmed burst length applies to both READ and WRITE bursts. Test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result. Write Burst Mode When M9 = 0, the burst length programmed via M0-M2 applies to both READ and WRITE bursts; when M9 = 1, the programmed burst length applies to READ bursts, but write accesses are single-location (nonburst) accesses. CAS Latency Allowable Operating Frequency (MHz) Speed -6 -7 -75E CAS Latency = 2 — — 133 CAS Latency = 3 167 143 — CAS LATENCY T0 CLK T1 T2 T3 COMMAND DQ READ NOP tAC NOP DOUT tLZ CAS Latency - 2 tOH T0 CLK T1 T2 T3 T4 COMMAND DQ READ NOP NOP tAC NOP DOUT tLZ CAS Latency - 3 tOH DON'T CARE UNDEFINED Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. E 05/01/06 25 IS42S81600B, CHIP OPERATION IS42S16800B ISSI CLK HIGH CKE CS RAS CAS WE A0-A11 BA0, BA1 ROW ADDRESS BANK ADDRESS ® BANK/ROW ACTIVATION Before any READ or WRITE commands can be issued to a bank within the SDRAM, a row in that bank must be “opened.” This is accomplished via the ACTIVE command, which selects both the bank and the row to be activated (see Activating Specific Row Within Specific Bank). After opening a row (issuing an ACTIVE command), a READ or WRITE command may be issued to that row, subject to the tRCD specification. Minimum tRCD should be divided by the clock period and rounded up to the next whole number to determine the earliest clock edge after the ACTIVE command on which a READ or WRITE command can be entered. For example, a tRCD specification of 18ns with a 125 MHz clock (8ns period) results in 2.25 clocks, rounded to 3. This is reflected in the following example, which covers any case where 2 < [tRCD (MIN)/tCK] ≤ 3. (The same procedure is used to convert other specification limits from time units to clock cycles). A subsequent ACTIVE command to a different row in the same bank can only be issued after the previous active row has been “closed” (precharged). The minimum time interval between successive ACTIVE commands to the same bank is defined by tRC. A subsequent ACTIVE command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row-access overhead. The minimum time interval between successive ACTIVE commands to different banks is defined by tRRD. ACTIVATING SPECIFIC ROW WITHIN SPECIFIC BANK EXAMPLE: MEETING TRCD (MIN) WHEN 2 < [TRCD (MIN)/TCK] ≤ 3 T0 CLK T1 T2 T3 T4 COMMAND ACTIVE NOP tRCD NOP READ or WRITE DON'T CARE 26 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. E 05/01/06 IS42S81600B, READS IS42S16800B READ COMMAND ISSI CLK HIGH ® READ bursts are initiated with a READ command, as shown in the READ COMMAND diagram. The starting column and bank addresses are provided with the READ command, and auto precharge is either enabled or disabled for that burst access. If auto precharge is enabled, the row being accessed is precharged at the completion of the burst. For the generic READ commands used in the following illustrations, auto precharge is disabled. During READ bursts, the valid data-out element from the starting column address will be available following the CAS latency after the READ command. Each subsequent dataout element will be valid by the next positive clock edge. The CAS Latency diagram shows general timing for each possible CAS latency setting. Upon completion of a burst, assuming no other commands have been initiated, the DQs will go High-Z. A full-page burst will continue until terminated. (At the end of the page, it will wrap to column 0 and continue.) Data from any READ burst may be truncated with a subsequent READ command, and data from a fixed-length READ burst may be immediately followed by data from a READ command. In either case, a continuous flow of data can be maintained. The first data element from the new burst follows either the last element of a completed burst or the last desired data element of a longer burst which is being truncated. The new READ command should be issued x cycles before the clock edge at which the last desired data element is valid, where x equals the CAS latency minus one. This is shown in Consecutive READ Bursts for CAS latencies of two and three; data element n + 3 is either the last of a burst of four or the last desired of a longer burst. The 128Mb SDRAM uses a pipelined architecture and therefore does not require the 2n rule associated with a prefetch architecture. A READ command can be initiated on any clock cycle following a previous READ command. Full-speed random read accesses can be performed to the same bank, as shown in Random READ Accesses, or each subsequent READ may be performed to a different bank. Data from any READ burst may be truncated with a subsequent WRITE command, and data from a fixed-length READ burst may be immediately followed by data from a WRITE command (subject to bus turnaround limitations). The WRITE burst may be initiated on the clock edge immediately following the last (or last desired) data element from the READ burst, provided that I/O contention can be avoided. In a given system design, there may be a possibility that the device driving the input data will go Low-Z before the SDRAM DQs go High-Z. In this case, at least a single-cycle delay should occur between the last read data and the WRITE command. CKE CS RAS CAS WE A0-A9 A11 AUTO PRECHARGE COLUMN ADDRESS A10 NO PRECHARGE BA0, BA1 BANK ADDRESS Note: A9 is "Don't Care" for x16. The DQM input is used to avoid I/O contention, as shown in Figures RW1 and RW2. The DQM signal must be asserted (HIGH) at least three clocks prior to the WRITE command (DQM latency is two clocks for output buffers) to suppress data-out from the READ. Once the WRITE command is registered, the DQs will go High-Z (or remain HighZ), regardless of the state of the DQM signal, provided the DQM was active on the clock just prior to the WRITE command that truncated the READ command. If not, the second WRITE will be an invalid WRITE. For example, if DQM was LOW during T4 in Figure RW2, then the WRITEs at T5 and T7 would be valid, while the WRITE at T6 would be invalid. The DQM signal must be de-asserted prior to the WRITE command (DQM latency is zero clocks for input buffers) to ensure that the written data is not masked. A fixed-length READ burst may be followed by, or truncated with, a PRECHARGE command to the same bank (provided that auto precharge was not activated), and a full-page burst may be truncated with a PRECHARGE command to the same bank. The PRECHARGE command should be issued x cycles before the clock edge at which the last desired data element is valid, where x equals the CAS latency minus one. This is shown in the READ to PRECHARGE diagram for each Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. E 05/01/06 27 IS42S81600B, IS42S16800B ISSI ® possible CAS latency; data element n + 3 is either the last of a burst of four or the last desired of a longer burst. Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until tRP is met. Note that part of the row precharge time is hidden during the access of the last data element(s). In the case of a fixed-length burst being executed to completion, a PRECHARGE command issued at the optimum time (as described above) provides the same operation that would result from the same fixed-length burst with auto precharge. The disadvantage of the PRECHARGE command is that it requires that the command and address buses be available at the appropriate time to issue the command; the advantage of the PRECHARGE command is that it can be used to truncate fixed-length or full-page bursts. Full-page READ bursts can be truncated with the BURST TERMINATE command, and fixed-length READ bursts may be truncated with a BURST TERMINATE command, provided that auto precharge was not activated. The BURST TERMINATE command should be issued x cycles before the clock edge at which the last desired data element is valid, where x equals the CAS latency minus one. This is shown in the READ Burst Termination diagram for each possible CAS latency; data element n + 3 is the last desired data element of a longer burst. 28 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. E 05/01/06 IS42S81600B, IS42S16800B ISSI T2 T3 T4 T5 T6 ® RW1 - READ to WRITE T0 CLK T1 DQM COMMAND READ NOP NOP NOP NOP NOP WRITE ADDRESS BANK, COL n BANK, COL b tHZ DQ CAS Latency - 2 DON'T CARE DOUT n DOUT n+1 DOUT n+2 DIN b tDS RW2 - READ to WRITE T0 CLK T1 T2 T3 T4 T5 DQM COMMAND READ NOP NOP NOP NOP WRITE ADDRESS BANK, COL n BANK, COL b tHZ DQ CAS Latency - 3 DOUT n DIN b tDS DON'T CARE Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. E 05/01/06 29 IS42S81600B, IS42S16800B ISSI ® CONSECUTIVE READ BURSTS T0 CLK T1 T2 T3 T4 T5 T6 COMMAND READ NOP NOP NOP READ NOP NOP ADDRESS BANK, COL n BANK, COL b DQ CAS Latency - 2 DOUT n DOUT n+1 DOUT n+2 DOUT n+3 DOUT b DON'T CARE T0 CLK T1 T2 T3 T4 T5 T6 T7 COMMAND READ NOP NOP NOP READ NOP NOP NOP ADDRESS BANK, COL n BANK, COL b DQ CAS Latency - 3 DOUT n DOUT n+1 DOUT n+2 DOUT n+3 DOUT b DON'T CARE 30 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. E 05/01/06 IS42S81600B, IS42S16800B ISSI ® RANDOM READ ACCESSES T0 CLK T1 T2 T3 T4 T5 COMMAND READ READ READ READ NOP NOP ADDRESS BANK, COL n BANK, COL b BANK, COL m BANK, COL x DQ CAS Latency - 2 DOUT n DOUT b DOUT m DOUT x DON'T CARE T0 CLK T1 T2 T3 T4 T5 T6 COMMAND READ READ READ READ NOP NOP NOP ADDRESS BANK, COL n BANK, COL b BANK, COL m BANK, COL x DQ CAS Latency - 3 DOUT n DOUT b DOUT m DOUT x DON'T CARE Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. E 05/01/06 31 IS42S81600B, IS42S16800B ISSI ® READ BURST TERMINATION T0 CLK T1 T2 T3 T4 T5 T6 COMMAND READ NOP NOP NOP BURST TERMINATE NOP NOP x = 1 cycle ADDRESS BANK a, COL n DQ CAS Latency - 2 DOUT n DOUT n+1 DOUT n+2 DOUT n+3 DON'T CARE T0 CLK T1 T2 T3 T4 T5 T6 T7 COMMAND READ NOP NOP NOP BURST TERMINATE NOP x = 2 cycles NOP NOP ADDRESS BANK, COL n DQ CAS Latency - 3 DOUT n DOUT n+1 DOUT n+2 DOUT n+3 DON'T CARE 32 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. E 05/01/06 IS42S81600B, IS42S16800B ISSI T3 T4 T5 T6 T7 T8 ® ALTERNATING BANK READ ACCESSES T0 CLK tCKS tCKH CKE tCMS tCMH COMMAND DQM/ DQML, DQMH tAS tAH A0-A9, A11 A10 BA0, BA1 ROW tAS tAH ROW tAS tAH BANK 0 ACTIVE tCK T1 tCL T2 tCH NOP READ tCMS tCMH NOP ACTIVE NOP READ NOP ACTIVE COLUMN m(2) ENABLE AUTO PRECHARGE ROW ROW COLUMN b(2) ENABLE AUTO PRECHARGE ROW ROW BANK 0 tLZ BANK 3 tOH DOUT m tAC tAC tOH DOUT m+1 tAC BANK 3 tOH DOUT m+2 tAC tRP - BANK 0 tRCD - BANK 3 CAS Latency - BANK 3 tOH DOUT m+3 tAC BANK 0 tOH DOUT b tAC tRCD - BANK 0 DQ tRCD - BANK 0 tRRD tRAS - BANK 0 tRC - BANK 0 CAS Latency - BANK 0 DON'T CARE Notes: 1) CAS latency = 2, Burst Length = 4 2) X16: A9 and A11 = "Don't Care" X8: A11 = "Don't Care" Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. E 05/01/06 33 IS42S81600B, IS42S16800B ISSI T3 T4 T5 T6 Tn+1 Tn+2 Tn+3 Tn+4 ® READ - FULL-PAGE BURST T0 CLK tCKS tCKH CKE tCMS tCMH COMMAND DQM/ DQML, DQMH tAS tAH A0-A9, A11 A10 BA0, BA1 ROW tAS tAH ROW tAS tAH BANK ACTIVE T1 tCK tCL T2 tCH NOP READ NOP NOP NOP NOP NOP BURST TERM NOP NOP tCMS tCMH COLUMN m(2) BANK tAC tAC DOUT m tAC DOUT m+1 tAC DOUT m+2 tOH tAC DOUT m-1 tOH tAC DOUT m tOH tHZ DOUT m+1 tOH DON'T CARE Full page Full-page burst not self-terminating. completion Use BURST TERMINATE command. UNDEFINED DQ tRCD tLZ CAS Latency tOH tOH each row (x4) has 1,024 locations Notes: 1) CAS latency = 2, Burst Length = Full Page 2) X16: A9 and A11 = "Don't Care" X8: A11 = "Don't Care" 34 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. E 05/01/06 IS42S81600B, IS42S16800B ISSI T3 T4 T5 T6 T7 T8 ® READ - DQM OPERATION T0 CLK tCKS tCKH CKE tCMS tCMH COMMAND DQM/ DQML, DQMH tAS tAH A0-A9, A11 A10 BA0, BA1 ROW tAS tAH ROW tAS tAH BANK ACTIVE tCK T1 tCL T2 tCH NOP READ tCMS tCMH NOP NOP NOP NOP NOP NOP COLUMN m(2) ENABLE AUTO PRECHARGE DISABLE AUTO PRECHARGE BANK tAC tOH DOUT m tHZ tLZ tAC tOH DOUT m+2 tAC tOH DOUT m+3 tHZ DON'T CARE UNDEFINED DQ tLZ tRCD CAS Latency Notes: 1) CAS latency = 2, Burst Length = 4 2) X16: A9 and A11 = "Don't Care" X8: A11 = "Don't Care" Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. E 05/01/06 35 IS42S81600B, IS42S16800B ISSI ® READ to PRECHARGE T0 CLK T1 T2 T3 T4 T5 tRP T6 T7 COMMAND READ NOP NOP NOP PRECHARGE NOP ACTIVE NOP ADDRESS BANK a, COL n BANK (a or all) BANK a, ROW tRQL DQ CAS Latency - 2 DOUT n DOUT n+1 DOUT n+2 DOUT n+3 High-Z DON'T CARE T0 CLK T1 T2 T3 T4 T5 tRP T6 T7 COMMAND READ NOP NOP NOP PRECHARGE NOP NOP ACTIVE ADDRESS BANK, COL n BANK, COL b BANK a, ROW tRQL DQ CAS Latency - 3 DOUT n DOUT n+1 DOUT n+2 DOUT n+3 High-Z DON'T CARE 36 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. E 05/01/06 IS42S81600B, WRITES IS42S16800B ISSI ® WRITE bursts are initiated with a WRITE command, as shown in WRITE Command diagram. WRITE COMMAND CLK HIGH CKE CS RAS CAS WE A0-A9 A11 AUTO PRECHARGE COLUMN ADDRESS A10 NO PRECHARGE BA0, BA1 BANK ADDRESS Note: A9 is "Don't Care" for x16. The starting column and bank addresses are provided with the WRITE command, and auto precharge is either enabled or disabled for that access. If auto precharge is enabled, the row being accessed is precharged at the completion of the burst. For the generic WRITE commands used in the following illustrations, auto precharge is disabled. During WRITE bursts, the first valid data-in element will be registered coincident with the WRITE command. Subsequent data elements will be registered on each successive positive clock edge. Upon completion of a fixed-length burst, assuming no other commands have been initiated, the DQs will remain High-Z and any additional input data will be ignored (see WRITE Burst). A full-page burst will continue until terminated. (At the end of the page, it will wrap to column 0 and continue.) Data for any WRITE burst may be truncated with a subsequent WRITE command, and data for a fixed-length WRITE burst may be immediately followed by data for a WRITE command. The new WRITE command can be issued on any clock following the previous WRITE command, and the data provided coincident with the new command applies to the new command. An example is shown in WRITE to WRITE diagram. Data n + 1 is either the last of a burst of two or the last desired of a longer burst. The 128Mb SDRAM uses a pipelined architecture and therefore does not require the 2n rule associated with a prefetch architecture. A WRITE command can be initiated on any clock cycle following a previous WRITE command. Full-speed random write accesses within a page can be performed to the same bank, as shown in Random WRITE Cycles, or each subsequent WRITE may be performed to a different bank. Data for any WRITE burst may be truncated with a subsequent READ command, and data for a fixed-length WRITE burst may be immediately followed by a subsequent READ command. Once the READ com mand is registered, the data inputs will be ignored, and WRITEs will not be executed. An example is shown in WRITE to READ. Data n + 1 is either the last of a burst of two or the last desired of a longer burst. Data for a fixed-length WRITE burst may be followed by, or truncated with, a PRECHARGE command to the same bank (provided that auto precharge was not activated), and a fullpage WRITE burst may be truncated with a PRECHARGE command to the same bank. The PRECHARGE command should be issued tDPL after the clock edge at which the last desired input data element is registered. The auto precharge mode requires a tDPL of at least one clock plus time, regardless of frequency. In addition, when truncating a WRITE burst, the DQM signal must be used to mask input data for the clock edge prior to, and the clock edge coincident with, the PRECHARGE command. An example is shown in the WRITE to PRECHARGE diagram. Data n+1 is either the last of a burst of two or the last desired of a longer burst. Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until tRP is met. In the case of a fixed-length burst being executed to completion, a PRECHARGE command issued at the optimum time (as described above) provides the same operation that would result from the same fixed-length burst with auto precharge. The disadvantage of the PRECHARGE command is that it requires that the command and address buses be available at the appropriate time to issue the command; the advantage of the PRECHARGE command is that it can be used to truncate fixed-length or full-page bursts. Fixed-length or full-page WRITE bursts can be truncated with the BURST TERMINATE command. When truncating a WRITE burst, the input data applied coincident with the BURST TERMINATE command will be ignored. The last data written (provided that DQM is LOW at that time) will be the input data applied one clock previous to the BURST TERMINATE command. This is shown in WRITE Burst Termination, where data n is the last desired data element of a longer burst. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. E 05/01/06 37 IS42S81600B, WRITE BURST IS42S16800B ISSI T0 T1 T2 T3 ® CLK COMMAND WRITE NOP NOP NOP ADDRESS BANK, COL n DQ DIN n DIN n+1 DON'T CARE WRITE TO WRITE T0 CLK T1 T2 COMMAND WRITE NOP WRITE ADDRESS BANK, COL n BANK, COL b DQ DIN n DIN n+1 DIN b DON'T CARE RANDOM WRITE CYCLES T0 CLK T1 T2 T3 COMMAND WRITE WRITE WRITE WRITE ADDRESS BANK, COL n BANK, COL b BANK, COL m BANK, COL x DQ DIN n DIN b DIN m DIN x 38 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. E 05/01/06 IS42S81600B, IS42S16800B ISSI T1 T2 T3 T4 T5 ® WRITE to READ T0 CLK COMMAND WRITE NOP READ NOP NOP NOP ADDRESS BANK, COL n BANK, COL b DQ DIN n DIN n+1 CAS Latency - 2 DOUT b DOUT b+1 DON'T CARE WP1 - WRITE to PRECHARGE T0 CLK T1 T2 T3 T4 T5 T6 DQM tRP COMMAND WRITE NOP NOP PRECHARGE NOP ACTIVE NOP ADDRESS BANK a, COL n BANK (a or all) BANK a, ROW tDPL DQ DIN n DIN n+1 DIN n+2 DON'T CARE Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. E 05/01/06 39 IS42S81600B, IS42S16800B ISSI T2 T3 T4 T5 T6 ® WP2 - WRITE to PRECHARGE T0 CLK T1 DQM tRP COMMAND WRITE NOP NOP PRECHARGE NOP NOP ACTIVE ADDRESS BANK a, COL n BANK (a or all) BANK a, ROW tDPL DQ DIN n DIN n+1 DON'T CARE WRITE Burst Termination T0 CLK T1 T2 COMMAND WRITE BURST TERMINATE NEXT COMMAND ADDRESS BANK, COL n (ADDRESS) DQ DIN n (DATA) DON'T CARE 40 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. E 05/01/06 IS42S81600B, IS42S16800B ISSI T3 tCH T4 T5 Tn+1 Tn+2 ® WRITE - FULL PAGE BURST T0 CLK tCKS tCKH CKE tCMS tCMH COMMAND DQM/DQML DQMH tAS tAH A0-A9, A11 A10 BA0, BA1 ROW tAS tAH ROW tAS tAH BANK BANK tDS DQ tRCD tDH tDS tDH DIN m+1 tDS tDH DIN m+2 tDS tDH tDS tDH tDS tDH DIN m DIN m+3 DIN m-1 DON'T CARE COLUMN m(2) ACTIVE NOP WRITE NOP NOP NOP NOP BURST TERM NOP T1 tCK tCL T2 tCMS tCMH Full page completed Notes: 1) Burst Length = Full Page 2) X16: A9 and A11 = "Don't Care" X8: A11 = "Don't Care" Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. E 05/01/06 41 IS42S81600B, IS42S16800B ISSI T2 T3 tCH T4 T5 T6 T7 ® WRITE - DQM OPERATION T0 CLK tCKS tCKH CKE tCMS tCMH COMMAND DQM/DQML DQMH tAS tAH A0-A9, A11 A10 BA0, BA1 ROW tAS tAH ROW tAS tAH BANK ACTIVE tCK T1 tCL NOP WRITE tCMS tCMH NOP NOP NOP NOP NOP COLUMN m(2) ENABLE AUTO PRECHARGE DISABLE AUTO PRECHARGE BANK tDS tDH tDS tDH DIN m+2 tDS tDH DIN m tRCD DIN m+3 DON'T CARE DQ Notes: 1) Burst Length = 4 2) X16: A9 and A11 = "Don't Care" X8: A11 = "Don't Care" 42 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. E 05/01/06 IS42S81600B, IS42S16800B ISSI T3 T4 T5 T6 T7 T8 T9 ® ALTERNATING BANK WRITE ACCESSES T0 CLK tCKS tCKH CKE tCMS tCMH COMMAND DQM/DQML DQMH tAS tAH A0-A9, A11 A10 BA0, BA1 ROW tAS tAH ROW tAS tAH BANK 0 ACTIVE tCK T1 tCL T2 tCH NOP WRITE tCMS tCMH NOP ACTIVE NOP WRITE NOP NOP ACTIVE COLUMN m(2) ENABLE AUTO PRECHARGE ROW ROW COLUMN b(2) ENABLE AUTO PRECHARGE ROW ROW BANK 0 tDS tDH tDS tDH DIN m+1 BANK 1 tDS tDH DIN m+2 tDS tDH BANK 1 tDS tDH DIN b tDS tDH tDS tDH BANK 0 tDS tDH DQ tRCD - BANK 0 tRRD tRAS - BANK 0 tRC - BANK 0 DIN m DIN m+3 DIN b+1 DIN b+2 DIN b+3 tRCD - BANK 0 tDPL - BANK 1 tDPL - BANK 0 tRCD - BANK 1 tRP - BANK 0 DON'T CARE Notes: 1) Burst Length = 4 2) X16: A9 and A11 = "Don't Care" X8: A11 = "Don't Care" Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. E 05/01/06 43 IS42S81600B, IS42S16800B ISSI ® CLOCK SUSPEND Clock suspend mode occurs when a column access/burst is in progress and CKE is registered LOW. In the clock suspend mode, the internal clock is deactivated, “freezing” the synchronous logic. For each positive clock edge on which CKE is sampled LOW, the next internal positive clock edge is suspended. Any command or data present on the input pins at the time of a suspended internal clock edge is ignored; any data present on the DQ pins remains driven; and burst counters are not incremented, as long as the clock is suspended. (See following examples.) Clock suspend mode is exited by registering CKE HIGH; the internal clock and related operation will resume on the subsequent positive clock edge. Clock Suspend During WRITE Burst T0 CLK T1 T2 T3 T4 T5 CKE INTERNAL CLOCK COMMAND NOP WRITE NOP NOP ADDRESS BANK a, COL n DQ DIN n DIN n+1 DIN n+2 DON'T CARE Clock Suspend During READ Burst T0 CLK T1 T2 T3 T4 T5 T6 CKE INTERNAL CLOCK COMMAND READ NOP NOP NOP NOP NOP ADDRESS BANK a, COL n DQ DOUT n DOUT n+1 DOUT n+2 DOUT n+3 DON'T CARE 44 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. E 05/01/06 IS42S81600B, IS42S16800B ISSI T3 T4 T5 T6 T7 T8 T9 ® CLOCK SUSPEND MODE T0 CLK tCKS tCKH CKE tCMS tCMH COMMAND DQM/DQML DQMH tAS tAH A0-A9, A11 A10 tAS tAH BA0, BA1 BANK COLUMN m(2) tAS tAH READ tCK T1 tCL T2 tCH tCKS tCKH NOP tCMS tCMH NOP NOP NOP NOP WRITE NOP COLUMN n(2) BANK tAC tAC DOUT m tLZ tOH DON'T CARE UNDEFINED tHZ DOUT m+1 tDS tDH DIN e DIN e+1 DQ Notes: 1) CAS latency = 3, Burst Length = 2, Auto Precharge is disabled. 2) X16: A9 and A11 = "Don't Care" X8: A11 = "Don't Care" Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. E 05/01/06 45 IS42S81600B, PRECHARGE IS42S16800B ISSI PRECHARGE Command CLK HIGH ® The PRECHARGE command (see figure) is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access some specified time (tRP) after the PRECHARGE command is issued. Input A10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs BA0, BA1 select the bank. When all banks are to be precharged, inputs BA0, BA1 are treated as “Don’t Care.” Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank. CKE CS RAS CAS WE A0-A9, A11 ALL BANKS POWER-DOWN Power-down occurs if CKE is registered LOW coincident with a NOP or COMMAND INHIBIT when no accesses are in progress. If power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if powerdown occurs when there is a row active in either bank, this mode is referred to as active power-down. Entering powerdown deactivates the input and output buffers, excluding CKE, for maximum power savings while in standby. The device may not remain in the power-down state longer than the refresh period (64ms) since no refresh operations are performed in this mode. The power-down state is exited by registering a NOP or COMMAND INHIBIT and CKE HIGH at the desired clock edge (meeting tCKS). See figure below. A10 BANK SELECT BA0, BA1 BANK ADDRESS POWER-DOWN CLK tCKS CKE ≥ tCKS COMMAND NOP Input buffers gated off NOP ACTIVE tRCD tRAS tRC DON'T CARE All banks idle Enter power-down mode Exit power-down mode less than 64ms 46 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. E 05/01/06 IS42S81600B, IS42S16800B ISSI T2 tCL tCKS tCH tCKS Tn+1 Tn+2 ® POWER-DOWN MODE CYCLE T0 CLK tCKS tCKH CKE tCMS tCMH COMMAND DQM/DQML DQMH A0-A9, A11 ALL BANKS A10 SINGLE BANK tAS tAH BA0, BA1 BANK PRECHARGE tCK T1 NOP NOP NOP ACTIVE ROW ROW BANK DQ High-Z Two clock cycles Precharge all active banks All banks idle, enter power-down mode Input buffers gated off while in power-down mode All banks idle Exit power-down mode DON'T CARE Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. E 05/01/06 47 IS42S81600B, IS42S16800B ISSI READ with Auto Precharge ® BURST READ/SINGLE WRITE The burst read/single write mode is entered by programming the write burst mode bit (M9) in the mode register to a logic 1. In this mode, all WRITE commands result in the access of a single column location (burst of one), regardless of the programmed burst length. READ commands access columns according to the programmed burst length and sequence, just as in the normal mode of operation (M9 = 0). Four cases where CONCURRENT AUTO PRECHARGE occurs are defined below. 1. Interrupted by a READ (with or without auto precharge): A READ to bank m will interrupt a READ on bank n, CAS latency later. The PRECHARGE to bank n will begin when the READ to bank m is registered. 2. Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m will interrupt a READ on bank n when registered. DQM should be used three clocks prior to the WRITE command to prevent bus contention. The PRECHARGE to bank n will begin when the WRITE to bank m is registered. CONCURRENT AUTO PRECHARGE An access command (READ or WRITE) to another bank while an access command with auto precharge enabled is executing is not allowed by SDRAMs, unless the SDRAM supports CONCURRENT AUTO PRECHARGE. ISSI SDRAMs support CONCURRENT AUTO PRECHARGE. READ With Auto Precharge interrupted by a READ T0 CLK COMMAND NOP READ - AP BANK n T1 T2 T3 T4 T5 T6 T7 NOP READ - AP BANK m NOP NOP NOP NOP BANK n Page Active READ with Burst of 4 Interrupt Burst, Precharge tRP - BANK n Idle tRP - BANK m Precharge Internal States BANK m Page Active BANK n, COL a BANK n, COL b READ with Burst of 4 ADDRESS DQ DOUT a CAS Latency - 3 (BANK n) DOUT a+1 DOUT b DOUT b+1 DON'T CARE CAS Latency - 3 (BANK m) READ With Auto Precharge interrupted by a WRITE T0 CLK COMMAND READ - AP BANK n T1 T2 T3 T4 T5 T6 T7 NOP NOP NOP WRITE - AP BANK m NOP NOP NOP BANK n READ with Burst of 4 Page Active Page Active BANK n, COL a BANK m, COL b Interrupt Burst, Precharge tRP - BANK n WRITE with Burst of 4 Idle tDPL - BANK m Write-Back Internal States BANK m ADDRESS DQM DQ DOUT a CAS Latency - 3 (BANK n) DIN b DIN b+1 DIN b+2 DIN b+3 DON'T CARE 48 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. E 05/01/06 IS42S81600B, IS42S16800B ISSI ® WRITE with Auto Precharge 3. Interrupted by a READ (with or without auto precharge): A READ to bank m will interrupt a WRITE on bank n when registered, with the data-out appearing (CAS latency) later. The PRECHARGE to bank n will begin after tDPL is met, where tDPL begins when the READ to bank m is registered. The last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m. 4. Interrupted by a WRITE (with or without auto precharge): AWRITE to bank m will interrupt a WRITE on bank n when registered. The PRECHARGE to bank n will begin after tDPL is met, where tDPL begins when the WRITE to bank m is registered. The last valid data WRITE to bank n will be data registered one clock prior to a WRITE to bank m. WRITE With Auto Precharge interrupted by a READ T0 CLK T1 T2 T3 T4 T5 T6 T7 COMMAND NOP WRITE - AP BANK n NOP READ - AP BANK m NOP NOP NOP NOP BANK n Page Active WRITE with Burst of 4 Interrupt Burst, Write-Back tDPL - BANK n Precharge tRP - BANK n tRP - BANK m Precharge Internal States BANK m Page Active READ with Burst of 4 ADDRESS BANK n, COL a BANK m, COL b DQ DIN a DIN a+1 CAS Latency - 3 (BANK m) DOUT b DOUT b+1 DON'T CARE WRITE With Auto Precharge interrupted by a WRITE T0 CLK T1 T2 T3 T4 T5 T6 T7 COMMAND NOP WRITE - AP BANK n NOP NOP WRITE - AP BANK m NOP NOP NOP BANK n Page Active WRITE with Burst of 4 Interrupt Burst, Write-Back tDPL - BANK n Precharge tRP - BANK n tDPL - BANK m Write-Back Internal States BANK m Page Active WRITE with Burst of 4 ADDRESS BANK n, COL a BANK m, COL b DQ DIN a DIN a+1 DIN a+2 DIN b DIN b+1 DIN b+2 DIN b+3 DON'T CARE Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. E 05/01/06 49 IS42S81600B, IS42S16800B ISSI T3 T4 T5 T6 T7 T8 ® SINGLE READ WITH AUTO PRECHARGE T0 CLK tCKS tCKH CKE tCMS tCMH COMMAND DQM/DQML DQMH tAS A0-A9, A11 A10 BA0, BA1 tAH ROW tAS tAH ROW tAS tAH BANK ACTIVE T1 tCK tCL T2 tCH NOP NOP NOP READ NOP NOP ACTIVE NOP tCMS tCMH COLUMN m(2) ENABLE AUTO PRECHARGE ROW ROW BANK tAC tOH DOUT m tHZ tRCD tRAS tRC CAS Latency tRP BANK DQ DON'T CARE UNDEFINED Notes: 1) CAS latency = 2, Burst Length = 1 2) X16: A9 and A11 = "Don't Care" X8: A11 = "Don't Care" 50 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. E 05/01/06 IS42S81600B, IS42S16800B ISSI T3 T4 T5 T6 T7 T8 ® READ WITH AUTO PRECHARGE T0 CLK tCKS tCKH CKE tCMS tCMH COMMAND DQM/DQML DQMH tAS tAH A0-A9, A11 A10 BA0, BA1 DQ ROW tAS tAH ROW tAS tAH BANK ACTIVE tCK T1 tCL T2 tCH NOP READ tCMS tCMH NOP NOP NOP NOP NOP ACTIVE COLUMN m(2) ENABLE AUTO PRECHARGE ROW ROW BANK tAC tLZ CAS Latency tAC DOUT m tOH tAC DOUT m+1 tOH tAC DOUT m+2 tOH tRP tHZ DOUT m+3 tOH BANK tRCD tRAS tRC DON'T CARE UNDEFINED Notes: 1) CAS latency = 2, Burst Length = 4 2) X16: A9 and A11 = "Don't Care" X8: A11 = "Don't Care" Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. E 05/01/06 51 IS42S81600B, IS42S16800B ISSI T3 T4 T5 T6 T7 T8 ® SINGLE READ WITHOUT AUTO PRECHARGE T0 CLK tCKS tCKH CKE tCMS tCMH COMMAND DQM/DQML DQMH tAS tAH A0-A9, A11 A10 BA0, BA1 DQ ROW tAS tAH ROW tAS tAH BANK ACTIVE tCK T1 tCL T2 tCH NOP READ tCMS tCMH NOP NOP PRECHARGE NOP ACTIVE NOP COLUMN m(2) ALL BANKS ROW ROW DISABLE AUTO PRECHARGE BANK tAC tLZ CAS Latency tOH DOUT m tHZ tRCD tRAS tRC SINGLE BANK BANK BANK DON'T CARE tRP UNDEFINED Notes: 1) CAS latency = 2, Burst Length = 1 2) X16: A9 and A11 = "Don't Care" X8: A11 = "Don't Care" 52 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. E 05/01/06 IS42S81600B, IS42S16800B ISSI T3 T4 T5 T6 T7 T8 ® READ WITHOUT AUTO PRECHARGE T0 CLK tCKS tCKH CKE tCMS tCMH COMMAND DQM/DQML DQMH tAS tAH A0-A9, A11 A10 BA0, BA1 DQ ROW tAS tAH ROW tAS tAH BANK ACTIVE tCK T1 tCL T2 tCH NOP READ tCMS tCMH NOP NOP NOP PRECHARGE NOP ACTIVE COLUMN m(2) ALL BANKS ROW ROW DISABLE AUTO PRECHARGE BANK tAC tLZ CAS Latency tAC DOUT m tOH tAC DOUT m+1 tOH SINGLE BANK BANK tAC DOUT m+2 tOH tRP tHZ DOUT m+3 tOH DON'T CARE UNDEFINED BANK tRCD tRAS tRC Notes: 1) CAS latency = 2, Burst Length = 4 2) X16: A9 and A11 = "Don't Care" X8: A11 = "Don't Care" Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. E 05/01/06 53 IS42S81600B, IS42S16800B ISSI ® SINGLE WRITE WITH AUTO PRECHARGE T0 CLK tCKS tCKH CKE tCMS tCMH COMMAND DQM/DQML, DQMH tAS A0-A9, A11 A10 BA0, BA1 tAH ACTIVE tCK T1 tCL T2 tCH T3 T4 T5 T6 T7 T8 T9 NOP NOP NOP WRITE tCMS tCMH NOP NOP NOP ACTIVE NOP ROW tAS tAH ROW tAS tAH BANK COLUMN m(2) ENABLE AUTO PRECHARGE ROW ROW BANK tDS tDH BANK DQ tRCD tRAS tRC DIN m tDPL tRP DON'T CARE Notes: 1) Burst Length = 1 2) X16: A9 and A11 = "Don't Care" X8: A11 = "Don't Care" 54 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. E 05/01/06 IS42S81600B, IS42S16800B ISSI T3 T4 T5 T6 T7 T8 ® SINGLE WRITE - WITHOUT AUTO PRECHARGE T0 CLK tCKS tCKH CKE tCMS tCMH COMMAND DQM/DQML DQMH tAS tAH A0-A9, A11 A10 BA0, BA1 ROW tAS tAH ROW tAS tAH BANK ACTIVE tCK T1 tCL T2 tCH NOP WRITE tCMS tCMH NOP NOP PRECHARGE NOP ACTIVE NOP COLUMN m(2) DISABLE AUTO PRECHARGE ROW ALL BANKS ROW SINGLE BANK BANK tDS tDH BANK BANK DQ tRCD tRAS tRC DIN m tDPL(3) tRP DON'T CARE Notes: 1) Burst Length = 1 2) X16: A9 and A11 = "Don't Care" X8: A11 = "Don't Care" 3) tRAS must not be violated. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. E 05/01/06 55 IS42S81600B, IS42S16800B ISSI T3 T4 T5 T6 T7 T8 ® WRITE - WITHOUT AUTO PRECHARGE T0 CLK tCKS tCKH CKE tCMS tCMH COMMAND DQM/DQML DQMH tAS tAH A0-A9, A11 A10 BA0, BA1 ROW tAS tAH ROW tAS tAH BANK ACTIVE tCK T1 tCL T2 tCH NOP WRITE tCMS tCMH NOP NOP NOP PRECHARGE NOP ACTIVE COLUMN m(2) ALL BANKS ROW ROW DISABLE AUTO PRECHARGE BANK tDS tDH tDS tDH DIN m+1 tDS tDH DIN m+2 tDS tDH SINGLE BANK BANK BANK DQ tRCD tRAS tRC DIN m DIN m+3 tDPL(3) tRP DON'T CARE Notes: 1) Burst Length = 4 2) X16: A9 and A11 = "Don't Care" X8: A11 = "Don't Care" 3) tRAS must not be violated. 56 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. E 05/01/06 IS42S81600B, IS42S16800B ISSI T3 T4 T5 T6 T7 T8 T9 ® WRITE - WITH AUTO PRECHARGE T0 CLK tCKS tCKH CKE tCMS tCMH COMMAND DQM/DQML DQMH tAS tAH A0-A9, A11 A10 BA0, BA1 ROW tAS tAH ROW tAS tAH BANK ACTIVE tCK T1 tCL T2 tCH NOP WRITE tCMS tCMH NOP NOP NOP NOP NOP NOP ACTIVE COLUMN m(2) ENABLE AUTO PRECHARGE ROW ROW BANK tDS tDH tDS tDH DIN m+1 tDS tDH DIN m+2 tDS tDH BANK DQ tRCD tRAS tRC DIN m DIN m+3 tDPL tRP DON'T CARE Notes: 1) Burst Length = 4 2) X16: A9 and A11 = "Don't Care" X8: A11 = "Don't Care" Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. E 05/01/06 57 IS42S81600B, IS42S16800B ISSI Package 54-Pin TSOPII 54-Pin TSOPII ® ORDERING INFORMATION - VDD = 3.3V Commercial Range: 0°C to 70°C Frequency 167 MHz 143 MHz Speed (ns) 6 7 Order Part No. IS42S81600B-6T IS42S81600B-7T Frequency 167 MHz 143 MHz Speed (ns) 6 7 Order Part No. IS42S16800B-6T IS42S16800B-7T Package 54-Pin TSOPII 54-Pin TSOPII ORDERING INFORMATION - VDD Industrial Range: -40°C to 85°C Frequency 143 MHz Speed (ns) 7 Order Part No. = 3.3V Package 54-Pin TSOPII IS42S81600B-7TI Frequency 143 MHz Speed (ns) 7 Order Part No. IS42S16800B-7TI Package 54-Pin TSOPII 58 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. E 05/01/06 IS42S81600B, IS42S16800B ISSI Package 54-Pin TSOPII, Lead-free 54-Pin TSOPII, Lead-free ® ORDERING INFORMATION - VDD = 3.3V Commercial Range: 0°C to 70°C Frequency 167 MHz 143 MHz Speed (ns) 6 7 Order Part No. IS42S81600B-6TL IS42S81600B-7TL Frequency 167 MHz 143 MHz 133 MHz Speed (ns) 6 7 7.5 Order Part No. IS42S16800B-6TL IS42S16800B-7TL IS42S16800B-75ETL Package 54-Pin TSOPII, Lead-free 54-Pin TSOPII, Lead-free 54-Pin TSOPII, Lead-free ORDERING INFORMATION - VDD Industrial Range: -40°C to 85°C Frequency 143 MHz Speed (ns) 7 Order Part No. = 3.3V Package 54-Pin TSOPII, Lead-free IS42S81600B-7TLI Frequency 167 MHz 143 MHz Speed (ns) 6 7 Order Part No. IS42S16800B-6TLI IS42S16800B-7TLI Package 54-Pin TSOPII, Lead-free 54-Pin TSOPII, Lead-free Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. E 05/01/06 59 PACKAGING INFORMATION Plastic TSOP 54–Pin, 86-Pin Package Code: T (Type II) ISSI N/2+1 E1 E Notes: 1. Controlling dimension: millimieters, unless otherwise specified. 2. BSC = Basic lead spacing between centers. 3. Dimensions D and E1 do not include mold flash protrusions and should be ® N measured from the bottom of the package. 4. Formed leads shall be planar with respect to one another within 0.004 inches at the seating plane. 1 D N/2 SEATING PLANE ZD A e b L A1 α C Symbol Ref. Std. No. Leads (N) A A1 A2 b C D E1 E e L L1 ZD α Plastic TSOP (T - Type II) Millimeters Inches Min Max Min Max 54 — 0.047 0.002 0.006 — — 0.012 0.018 0.005 0.0083 0.867 0.8827 0.395 0.405 0.455 0.471 0.031 BSC 0.016 0.024 — — 0° 8° Plastic TSOP (T - Type II) Millimeters Inches Symbol Min Max Min Max Ref. Std. No. Leads (N) 86 A A1 A2 b C D E1 E e L L1 ZD α — 1.20 0.05 0.15 0.95 1.05 0.17 0.27 0.12 0.21 22.02 22.42 10.16 BSC 11.56 11.96 0.50 BSC 0.40 0.60 0.80 REF 0.61 REF 0° 8° — 0.047 0.002 0.006 0.037 0.041 0.007 0.011 0.005 0.008 0.867 0.8827 0.400 BSC 0.455 0.471 0.020 BSC 0.016 0.024 0.031 REF 0.024 BSC 0° 8° — 1.20 0.05 0.15 — — 0.30 0.45 0.12 0.21 22.02 22.42 10.03 10.29 11.56 11.96 0.80 BSC 0.40 0.60 — — 0.71 REF 0° 8° Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. C 01/28/02 1