IS43QR16256A-093PBL

® IS43/46QR16256A Long-term Support World Class Quality 256Mbx16 4Gb DDR4 SDRAM FEBRUARY 2018 FEATURES ‡ Standard Voltage : VDD = VDDQ = 1.2V, VPP=2.5V ‡ High speed data transfer rates with system frequency up to 2400 Mbps ‡ Data Integrity ‡ Signal Integrity - Internal VREFDQ Training - Read Preamble Training - Gear Down Mode - Auto Self Refresh (ASR) by DRAM built-in TS - Per DRAM Adressability - Auto Refresh and Self Refresh Modes - Configurable DS for system compatibility ‡ DRAM access bandwidth - Separated IO gating structures by Bank Groups - Self Refresh Abort - Fine Granularity Refresh ‡ Signal Synchronization - Write Leveling via MR settings - Read Leveling via MPR ‡ Reliability & Error Handling - Command/Address Parity (Not Supported) - Configurable On-Die Termination - Data bus Inversion (DBI) - ZQ Calibration for DS/ODT impedance accuracy via external ZQ pad (240 ohm +/- 1%) ‡ Power Saving and efficiency - POD with VDDQ termination - Command/Address Latency (CAL) - Maximum Power Saving - Low power Auto Self Refresh (LPASR) - Data bus Write CRC - MPR readout - Boundary Scan ‡ Speed Grade (CL-TRCD-TRP) ‡ Operating Temperature - Commercial ( Tc = 0 oC to + 95 oC) - Industrial ( Tc = - 40 oC to + 95oC) - 2133Mbps / 15-15-15 (-093P) - Automotive A1 ( Tc = - 40 oC to + 95 oC) - 2400Mbps / 16-16-16 (- 083R) - Automotive A2 ( Tc = - 40 oC to + 105 oC) PPROGRAMMABLE FUNCTIONS ‡ Output Driver Impedance (34/48) ADDRESS TABLE Parameter 256M x16 Row Addressing A0-A14 Column Addressing A0-A9 Bank Addressing BA0-BA1 Bank Groups BG0 Page size 2KB ‡ CAS Write Latency (9/0/11/12/14/16/18) ‡ Additive Latency (0/CL-1/CL-2) ‡ CS# to Command Address (3/4/5/6/8) ‡ Burst Type (Sequential/Interleaved) ‡ Write Recovery Time (10/12/14/16/18/20/24) ‡ Read Preamble (1T/2T) ‡ Write Preamble (1T/2T) ‡ Burst Length (BL8/BC4/BC4 or 8 on the fly) Options tRFC 260ns ‡ Configuration : 256Mx16 ‡ Package: - 96-ball FBGA (9mm x 13mm, 0.8mm ball pitch) Copyright © 2017 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 1 ® Long-term Support World Class Quality IS43/46QR16256A 1.2 DDR4 SDRAM package ball out 96-ball FBGA –x16 (Top View) 1 2 3 A B C D VDDQ VPP VDDQ VDD VSSQ VSS DQ12 VSSQ DQ8 VDD DQ10 DQ14 E VSS 4 5 6 7 8 9 DQSU DQSU DQ11 DQ15 VSSQ DQ9 DQ13 VSSQ VDDQ VDD VSSQ VDDQ A B C D VSSQ VSS E LDM/ LDBI DQ1 F VSSQ UDM/ UDBI VDDQ G H J K VDDQ VSSQ VDD VSS DQ0 DQ4 VDDQ CKE DQSL DQSL DQ2 DQ6 ODT L VDD WE/ A14 ACT CS CK RAS/ A16 M VREFCA BG0 N P VSS BA0 A6 A10/ AP A4 A0 A12/ BC A3 A1 CAS/ A15 BA1 A5 A8 A11 A2 PAR A9 NC A7 A13 R T RESET VDD VSS VSSQ Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 VDD DQ3 DQ7 CK VDDQ ZQ F VSS DQ5 VDDQ VDDQ VSSQ VDD VSS G H J K VDD L VSS M TEN N P ALERT VPP VDD R T 2 ® Long-term Support World Class Quality IS43/46QR16256A PINOUT DESCRIPTION Symbol Type Function Input Clock: CK and CK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK CKE Input Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and device input buffers and output drivers. Taking CKE Low provides Precharge PowerDown and Self-Refresh operation (all banks idle), or Active Power-Down (row Active in any bank). CKE is synchronous for Self-Refresh exit. After VREFCA and Internal DQ Vref have become stable during the power on and initialization sequence, they must be maintained during all operations (including Self-Refresh). CKE must be maintained high throughout read and write accesses. Input buffers, excluding CK, CK, ODT and CKE are disabled during power-down. Input buffers, excluding CKE, are disabled during SelfRefresh. CS Input Chip Select: All commands are masked when CS is registered HIGH. CS provides for external Rank selection on systems with multiple Ranks. CS is considered part of the command code. ODT Input On Die Termination: ODT (registered HIGH) enables RTT_NOM termination resistance internal to the DDR4 SDRAM. When enabled, ODT is applied to each DQ, DQSU, DQSU, DQSL, DQSL, UDM and LDM signal. The ODT pin will be ignored if MR1 is programmed to disable RTT_NOM. ACT Input Activation Command Input : ACT_n defines the Activation command being entered along with CS. The input into RAS/A16, CAS/A15 and WE/A14 will be considered as Row Address A16, A15 and A14 CK, CK RAS/A16. CAS/A15 WE/A14 LDM, UDM UDBI, LDBI BG0 BA0 - BA1 A0 - A16 A10 / AP Input Input/Output Command Inputs: RAS/A16, CAS/A15 and WE/A14 (along with CS) define the command being entered. Those pins have multi function. For example, for activation with ACT Low, those are Addressing like A16,A15 and A14 but for non-activation command with ACT High, those are Command pins for Read, Write and other command defined in command truth table Input Data Mask and Data Bus Inversion: DM is an input mask signal for write data. Input data is masked when DM is sampled LOW coincident with that input data during a Write access. DM is sampled on both edges of DQS. DM is muxed with DBI function by Mode Register A10,A11,A12 setting in MR5. DBI is an input/output identifying whether to store/output the true or inverted data. If DBI is LOW, the data will be stored/output after inversion inside the DDR4 SDRAM and not inverted if DBI is HIGH. The DM and DBI functions must be configured in Mode Register Settings Input Bank Group Inputs: BG0 define to which bank group an Active, Read, Write or Precharge command is being applied. BG0 also determines which mode register is to be accessed during a MRS cycle. BG1 is not used for this component. Input Bank Address Inputs: BA0 - BA1 define to which bank an Active, Read, Write or Precharge command is being applied. Bank address also determines which mode register is to be accessed during a MRS cycle. Input Address Inputs: Provide the row address for ACTIVATE Commands and the column address for Read/Write commands to select one location out of the memory array in the respective bank. (A10/AP, A12/BC, RAS/A16, CAS/A15 and WE/A14 have additional functions, see other rows.The address inputs also provide the op-code during Mode Register Set commands. A15 and A16 are used on some higher densities. Input A12 / BC Input RESET Input Auto-precharge: A10 is sampled during Read/Write commands to determine whether Autoprecharge should be performed to the accessed bank after the Read/Write operation. (HIGH: Autoprecharge; LOW: no Autoprecharge).A10 is sampled during a Precharge command to determine whether the Precharge applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by bank addresses. Burst Chop: A12 / BC is sampled during Read and Write commands to determine if burst chop (on-the-fly) will be performed. (HIGH, no burst chop; LOW: burst chopped). See command truth table for details. Active Low Asynchronous Reset: Reset is active when RESET is LOW, and inactive when RESET is HIGH. RESET must be HIGH during normal operation. RESET is a CMOS rail to rail signal with DC high and low at 80% and 20% of VDD, Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 3 ® Long-term Support World Class Quality IS43/46QR16256A Symbol Type DQ0-DQ15 Input / Output DQS, DQS, DQSU, DQSU, DQSL, DQSL Input / Output TDQS, TDQS PAR ALERT TEN Output Input Input/Output Input Function Data Input/ Output: Bi-directional data bus. If CRC is enabled via Mode register then CRC code is added at the end of Data Burst. Any DQ from DQ0~DQ3 may indicate the internal Vref level during test via Mode Register Setting MR4 A4=High. During this mode, RTT should be set Hi-Z. Data Strobe: output with read data, input with write data. Edge-aligned with read data, centered in write data. DQSL corresponds to the data on DQ0-DQ7; DQSU corresponds to the data on DQ8-DQ15. The data strobe DQS, DQSL and DQSU are paired with differential signals DQS, DQSL, and DQSU, respectively, to provide differential pair signaling to the system during reads and writes. DDR4 SDRAM supports differential data strobe only and does not support single-ended. Termination Data Strobe is not applicable. The TDQS function must be disabled via mode register A11 = 0 in MR1. The feature command and Address Parity is not supported. This should be treated as NC or RFU. Alert: It has multi functions such as CRC error flag, Command and Address Parity error flag as Output signal. If there is error in CRC, then ALERT goes LOW for the period time interval and goes back HIGH. If there is error in Command Address Parity Check, then ALERT goes LOW for relatively long period until on going DRAM internal recovery transaction to complete. During Connectivity Test mode, this pin works as input. Using this signal or not is dependent on system. In case of not connected as Signal, ALERT Pin must be bounded to VDD on board. Connectivity Test Mode Enable: Required on X16 devices and optional input on x4/x8 with densities equal to or greater than 8Gb.HIGH in this pin will enable Connectivity Test Mode operation along with other pins. It is a CMOS rail to rail signal with AC high and low at 80% and 20% of VDD. Using this signal or not is dependent on System. This pin may be DRAM internally pulled low through a weak pull-down resistor to VSS. No Connect: No internal electrical connection is present. NC VDDQ Supply DQ Power Supply: 1.2 V +/- 0.06 V VSSQ Supply DQ Ground VDD Supply Power Supply: 1.2 V +/- 0.06 V VSS Supply Ground VPP Supply DRAM Activating Power Supply: 2.5V (2.375V min, 2.75V max) VREFCA Supply Reference voltage for CA ZQ Supply Reference Pin for ZQ calibration NOTE Input only pins (BG0, BA0-BA1, A0-A17, ACT, RAS/A16, CAS/A15, WE/A14, CS, CKE, ODT, and RESET) do not supply termination. Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 4 ® Long-term Support World Class Quality IS43/46QR16256A Simplified State Diagram Power applied Power On RESET SRX* MRS Reset SRX* MRS ZQ Calibra on Self Refresh SRX MRS MRS MRS SRE MRS Test Refreshing REF Idle ZQCL, ZQCS TEN=1 Any powered state MRS, MPR, Write Leveling, VrefDQ training PDA mode ZQCL Connectivity TEN=0 RESET Automa c Sequence Command Sequence CKE_L Ini aliza on Procedure SRX* = SRX with NOP IVREFDQ, RTT, etc MPSM PDE ACT CKE_L CKE_L PDX Ac ve Power Down Precharge Power Down Activa ng PDX PDE Bank Ac ve WRITE WRITE READ WRITE A READ READ A READ Wri ng Reading WRITE WRITE A READ A READ A WRITE A Wri ng Reading PRE, PREA PRE, PREA PRE, PREA Precharging Abbr. Function ACT Ac ve PRE Precharge PREA Precharge All ZQCS ZQ Calibra on Short Abbr. Function Read RD, RDS4, RDS8 Read A RDA, RDAS4, RDAS8 Write WR, WRS4, WRS8 with/without CRC Write A WRA, WRAS4, WRAS8 with/without CRC PDE Enter Power-down PDX Exit Power-down SRE Self-Refresh entry SRX Self-Refresh exit RESET Start RESET Procedure TEN Boundary Scan Mode Enable MPR Mul -Purpose Register ZQCL ZQ Calibra on Long REF Refresh, Fine granularity Refresh MRS Mode Register Set Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 Abbr. Function 5 IS43/46QR16256A ® Long-term Support World Class Quality BASIC FUNCTIONALITY The DDR4 SDRAM is a high-speed dynamic random-access memory internally organized with eight-banks (2 bank groups each with 4 banks). The DDR4 SDRAM uses a 8n prefetch architecture to achieve high-speed operation. The 8n prefetch architecture is combined with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write operation for the DDR4 SDRAM consists of a single 8n-bit wide, four clock data transfer at the internal DRAM core and eight corresponding n-bit wide, one-half clock cycle data transfers at the I/O pins. Read and write operation to the DDR4 SDRAM are burst oriented, start at a selected location, and continue for a burst length of eight or a ‘chopped’ burst of four in a programmed sequence. Operation begins with the registration of an ACTIVATE Command, which is then followed by a Read or Write command. The address bits registered coincident with the ACTIVATE Command are used to select the bank and row to be activated (BG0 select the bankgroup; BA0-BA1 select the bank; A0-A14 select the row; refer to Addressing section for more details). The address bits registered coincident with the Read or Write command are used to select the starting column location for the burst operation, determine if the auto precharge command is to be issued (via A10), and select BC4 or BL8 mode ‘on the fly’ (via A12) if enabled in the mode register. Prior to normal operation, the DDR4 SDRAM must be powered up and initialized in a predefined manner. The following sections provide detailed information covering device reset and initialization, register definition, command descriptions, and device operation. Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 6 ® Long-term Support World Class Quality IS43/46QR16256A RESET and Initialization Procedure RESET and Initialization Procedure For power-up and reset ini aliza on, in order to prevent DRAM from func oning improperly, default values for the following MR se ngs are de ned: Default MR se ngs for power-up and reset ini aliza on MR funcƟŽns MR bits Value Gear-down mode MR3 A[3] 1/2 Rate Per DRAM Addressability MR3 A[4] Disable MR4 A[1] Disable CS to Command/Address Latency Max Power Saving Mode MR4 A[8:6] Disable CA Parity Latency Mode MR5 A[2:0] Disable Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 7 IS43/46QR16256A ® Long-term Support World Class Quality Power-Up and Initialization Sequence The following sequence (Step 1-15) is required for power-up and ini aliza on: 1) Apply power (RESET is recommended to be maintained below 0.2 × VDD; all other inputs may be unde ned). RESET needs to be maintained for minimum 200 s with stable power. CKE is pulled LOW any me before RESET is being deasserted (MIN me 10ns). The power voltage ramp me between 300mV to VDD, min must be no greater than 200ms, and, during the ramp, VDD must be greater than or equal to VDDQ and (VDD - VDDQ) < 0.3V. VPP must ramp at the same me or earlier than VDD, and VPP must be equal to or higher than VDD at all mes. During power-up, either of the following condi ons may exist and must be met: Condi on A – VDD and VDDQ are driven from a single-power converter output. – The voltage levels on all balls other than VDD, VDDQ, VSS, and VSSQ must be less than or equal to VDDQ, and VDD on one side and must be greater than or equal to VSSQ and VSS on the other side. – VTT is limited to 0.76V MAX when the power ramp is complete. – VREFCA tracks VDD/2. Condi on B – Apply VDD without any slope reversal before or at the same me as VDDQ. – Apply VDDQ without any slope reversal before or at the same me as VTT and VREFCA. – Apply VPP without any slope reversal before or at the same me as VDD. – The voltage levels on all pins other than VPP, VDD, VDDQ, VSS, and VSSQ must be less than or equal to VDDQ and VDD on one side and must be larger than or equal to VSSQ and VSS on the other side. 2) A er RESET is de-asserted, wait for another 500 s un l CKE becomes ac ve. During this me, the DRAM will start internal state ini aliza on; this will be done independently of external clocks. A reasonable a empt was made in the design to have the DRAM power up with the following default MR se ngs (Refer to the table: default MR se ngs for power-up and reset ini aliza on). 3) Clocks (CK, CK) need to be started and stabilized for at least 10ns or 5 tCK Clocks (CK, CK) need to be started and stabilized for at least 10ns or 5 tCK (whichever is larger) before CKE goes ac ve. Because CKE is a synchronous signal, the corresponding setup me to clock (tIS) must be met. Also, a DESELECT command must be registered (with tIS setup me to clock) at clock edge Td. A er the CKE is registered HIGH a er RESET, CKE needs to be con nuously registered HIGH un l the ini aliza on sequence is nished, including expira on of tDLLK and tZQINIT. 4) The DDR4 SDRAM keeps its ODT in High-Z state as long as RESET is asserted. Further, the SDRAM keeps its ODT in High-Z state a er RESET de-asser on un l CKE is registered HIGH. The ODT input signal may be in an unde ned state un l tIS before CKE is registered HIGH. When CKE is registered HIGH, the ODT input signal may be sta cally held at either LOW or HIGH. If RTT_NOM is to be enabled in MR1, the ODT input signal must be sta cally held LOW. In all cases, the ODT input signal remains sta c un l the power-up ini aliza on sequence is nished, including the expira on of tDLLK and tZQINIT. Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 8 ® Long-term Support World Class Quality IS43/46QR16256A 5) A er CKE is registered HIGH, wait a minimum of RESET CKE EXIT me, tXPR, before issuing the rst MRS command to load mode register (tXPR = MAX (tXS; 5 × tCK). 6) Issue MRS command to load MR3 with all applica on se ngs, wait tMRD. 7) Issue MRS command to load MR6 with all applica on se ngs, wait tMRD. 8) Issue MRS command to load MR5 with all applica on se ngs, wait tMRD. 9) Issue MRS command to load MR4 with all applica on se ngs, wait tMRD. 10) Issue MRS command to load MR2 with all applica on se ngs, wait tMRD. 11) Issue MRS command to load MR1 with all applica on se ngs, wait tMRD. 12) Issue MRS command to load MR0 with all applica on se ngs, wait tMOD. 13) Issue a ZQCL command to start ZQ calibra on. 14) Wait for tDLLK and tZQINIT to complete. 15) The DDR4 SDRAM will be ready for normal opera on. RESET and Initialization Sequence at Power-On Ramping Ta Tb Tc Td Te Tf Tg Th Ti Tj Tk CK, tCKSRX VPP VDD/VDDQ 200 us 500 us tIS 10 ns VALID CKE ** tXPR tMRD tMRD tDLLK tIS CMD 1) BA[2:0] tZQinit tMOD tMRD MRS MRS MRS MRS MRx MRx MRx MRx ZQCL VALID VALID tIS tIS ODT 1) Static LOW in case RTT_Nom is eanbled at time Tg, otherwise static HIGH or LOW VALID DRAM_RTT TIME BREAK DON’T CARE NOTE 1 From the me point Td un l Tk, a DES command must be applied between MRS and ZQCL commands. NOTE 2 MRS commands must be issued to all mode registers that have de ned se ngs. NOTE 3 In general, there is no speci c sequence for se ng the MRS loca ons (except for dependent or co-related features, such as ENABLE DLL in MR1 prior to RESET DLL in MR0, for example). NOTE 4 TEN is not shown; however, it is assumed to be held LOW. Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 9 ® Long-term Support World Class Quality IS43/46QR16256A VDD Slew Rate Symbol Min Max Units NOTE VDD_sl 0.004 600 V/ms 1,2 200 ms 3 VDD_on NOTE 1 Measurement made between 300mV and 80% VDD (minimum level). NOTE 2 The DC bandwidth is limited to 20MHz NOTE 3 Maximum me to ramp VDD from 300 mV to VDD minimum. Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 10 ® Long-term Support World Class Quality IS43/46QR16256A RESET Initialization with Stable Power Sequence The following sequence is required for RESET at no power interrup on ini aliza on: 1. Assert RESET below 0.2 × VDD any me when reset is needed (all other inputs may be unde ned). RESET needs to be maintained for minimum 100ns. CKE is pulled LOW before RESET is de-asserted (MIN me 10ns). 2. Follow Steps 2 to 7 in the Reset and Ini aliza on Sequence at Power-on Ramping procedure. When the reset sequence is complete, the DDR4 SDRAM is ready for normal opera on. RESET Procedure at Power Stable Condition Ta Tb Tc . Td . Te . Tf . Tg . Th . Ti . Tj . Tk . . CK, tCKSRX VPP VDD/VDDQ 500 us tPW_RESET tIS 10 ns VALID CKE tXPR tMRD tMRD tMOD tMRD tZQin tDLLK tIS CMD 1) BA[2:0] MRS MRS MRS MRS MRx MRx MRx MRx ZQCL 1) VALID VALID tIS ODT Static LOW in case RTT_Nom is eanbled at time Tg, otherwise static HIGH or LOW VALID DRAM_RTT TIME BREAK DON’T CARE NOTE 1 From the me point Td un l Tk, a DES command must be applied between MRS and ZQCL commands. NOTE 2 MRS commands must be issued to all mode registers that have de ned se ngs. NOTE 3 In general, there is no speci c sequence for se ng the MRS loca ons (except for dependent or co-related features, such as ENABLE DLL in MR1 prior to RESET DLL in MR0,for example). NOTE 4 TEN is not shown; however, it is assumed to be held LOW. Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 11 IS43/46QR16256A ® Long-term Support World Class Quality PROGRAMMING MODE REGISTERS Mode Register Set (MRS) MRS Purpose Range DescripƟons For applica on exibility, various func ons, features, and modes. Seven Mode Registers. They are divided into various elds depending on func onality and modes. 1. As the default values of the Mode Registers (MRn) are not de ned, contents of Mode Registers must be fully ini alized and/or re-ini alized, i.e., wri en, a er power up and/or reset for proper opera on, as user de ned variables and they must be programmed. 2. MRS command and DLL Reset do not a ect array contents, which mean these commands can be executed any me a er power-up without a ec ng the array contents. 3. When programming the mode registers, even if the user chooses to modify only a sub-set of the MRS elds, all address elds within the accessed mode register must be redefined when the MRS command is issued. 4. The contents of the Mode Registers can be altered by re-execu ng the MRS command during normal opera on as long as the DRAM is in idle state, i.e., all banks are in the precharged state with tRP sa s ed, all data bursts are completed and CKE is high prior to wri ng into the mode register. If the RTT_NOM Feature is enabled in the Mode Register prior and/or a er an MRS Command, the ODT Signal must con nuously be registered LOW ensuring RTT is in an o State prior to the MRS command. The ODT Signal may be registered high a er tMOD has expired. If the RTT_NOM feature is disabled in the Mode Register prior and a er an MRS command, the ODT signal can be registered either LOW or HIGH before, during and a er the MRS command. Regula ons 5. The mode register set command cycle me, tMRD is required to complete the write opera on to the mode register and is the minimum me required between two MRS commands. 6. The most MRS command to Non-MRS command delay, tMOD, is required for the DRAM to update the features, and is the minimum me required from an MRS command to a non-MRS command excluding DES. 7. Some of the Mode Register se ngs a ect address/command/control input func onality. In these cases, func on upda ng takes longer than tMOD so the next MRS command only can be allowed when the func on upda ng by current MRS command completed. These MRS commands do not apply tMRD ming to next MRS command. These MRS command input cases have unique a MR se ng procedure, so refer to individual func on descrip on: ‡ ‡ ‡ ‡ ‡ ‡ ‡ ‡ Gear-down mode Per DRAM Addressability Max Power Saving Mode CS to Command/Address Latency CA Parity Latency Mode VrefDQ training Value VrefDQ Training mode VrefDQ training Range Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 12 IS43/46QR16256A ® Long-term Support World Class Quality tMRD Timing NOTE 1 This ming diagram depicts C/A Parity Mode "Disabled" case. NOTE 2 tMRD applies to all MRS commands with the following excep ons: ‡ Geardown Mode ‡ C/A Parity Mode ‡ CAL Mode ‡ Per DRAM addressability Mode ‡ VrefDQ training value, VreDQ training mode, and VrefDQ Training Range tMOD Timing The MRS command to nonMRS command delay, tMOD, is required for the DRAM to update features, except DLL RESET, and is the minimum me required from an MRS command to a nonMRS command, excluding DES. NOTE 1 This ming diagram depicts C/A Parity Mode "Disabled" case. NOTE 2 tMOD applies to all MRS commands with the following excep ons: ‡ DLL Enable ‡ Geardown Mode ‡ CA Parity Mode ‡ Maximum Power Savings Mode ‡ Per DRAM addressability Mode ‡ VrefDQ training value, internal Vref monitor, VreDQ training mode, and VrefDQ Training Range Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 13 ® Long-term Support World Class Quality IS43/46QR16256A MRS Overview Detail op ons are described on the following pages. MR0 MR1 MR2 A13 A12 RFU1 RFU1 A13 A12 A11 Qoī 2 TDQS A12 A11 A13 RFU 1 RFU 1 A13 MR4 RFU 1 A13 MR5 RFU 1 A13 MR6 MR7 RFU Write CRC A12 A9 A10 A9 A11 A10 A10 A9 A8 Write CMD Latency A11 A10 A9 tRPRE training SRF abort A12 A11 A10 A9 WDBI DM RFU A11 A10 A9 tCCD_L A12 A11 A9 A5 A4 RFU1 A6 A2 BT CL5 A3 A2 AL A5 A4 LPASR A7 A3 A3 A2 CWL A5 A4 A3 A2 PDA Geardown MPR OperaƟon A6 A5 RFU A8 1 A7 A7 A6 RTT_Park A8 1 A8 A7 A6 VrefDQ Training VrefDQ Range A7 A6 RFU 1 A53 ODT IB for PD A5 A0 BL A1 A0 DLL A1 RFU TS CS to CMD/ADDR Latency Mode A1 ODI A6 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 A4 Fine Granularity Refresh Mode A8 RFU A10 A6 A7 1 A5 CL5 A7 A8 RFU tRPRE A6 Wlev A9 A12 A12 A7 TM A8 tWPRE RDBI A8 DLL Rst RTT_NOM RTT_WR MPR Read Format 1 A13 A10 WR & RTP3,4 RFU1 A13 MR3 A11 A0 1 A1 A0 MPR Page SelecƟon A4 A3 A2 A1 A0 Internal Vref TCRM TCRR MPS RFU A3 A2 A4 RFU A4 1 CRC error A3 A1 RFU A2 1 A0 1 A1 A0 A1 A0 VrefDQ Training Value A5 A4 A3 A2 1 14 ® Long-term Support World Class Quality IS43/46QR16256A Mode Register 0 (MR0) BG0 BA1 BA0 MR Select BG0 BA1 BA0 MR Select ņ RAS / CAS / WE / A16 ņ A11 A15 A14 A9 A12 RFU1 RFU1 ņ A10 A13 WR RTP A11 A10 A9 3,4 WR & RTP A8 A7 DLL Rst TM A6 A5 A4 A3 A2 BT CL5 CAS Latency A1 A0 CL5 A8 DLL Reset A3 BT 0 Sequen a l 1 Interl ea ve A1 A0 BL 0 0 0 MR0 0 0 0 10 5 0 NO 0 0 1 MR1 0 0 1 12 6 1 YES 0 1 0 MR2 0 1 0 14 7 0 1 1 MR3 0 1 1 16 8 A6 A5 A4 A2 1 0 0 MR4 1 0 0 18 9 0 0 0 0 9 0 0 8 (Fixed) 1 0 1 MR5 1 0 1 20 10 0 0 0 1 10 0 1 BC4 or 8 (on the y) 1 1 0 MR6 1 1 0 24 12 0 0 1 0 11 1 0 BC4 (Fixed) 1 1 1 DNU 2 1 1 1 RFU RFU 0 0 1 1 12 1 1 RFU 0 1 0 0 13 0 1 0 1 14 0 1 1 0 15 0 1 1 1 16 1 0 0 0 18 1 0 0 1 20 1 0 1 0 22 1 0 1 1 24 1 1 0 0 RFU 1 1 0 1 17 1 1 1 0 19 1 1 1 1 21 BL 6 NOTE 1 Please refer to addressing table. If the address is available, it must be programmed to 0 during MRS NOTE 2 Reserved for Register control word se ng. DRAM ignores MR command with BG0,BA[1:0]=111 and doesn’t respond. NOTE 3 WR (write recovery for autoprecharge)min in clock cycles is calculated by dividing tWR(in ns) by tCK(in ns) and rounding up to the next integer:WRmin[cycles] = Roundup(tWR[ns] / tCK[ns]). The WR value in the mode register must be programmed to be equal or larger than WRmin. The programmed WR value is used with tRP to determine tDAL. NOTE 4 The table shows the encodings for Write Recovery and internal Read command to Precharge command delay. For actual Write recovery ming, please refer to AC ming table. NOTE 5 The table only shows the encodings for a given Cas Latency. For actual supported Cas Latency, please refer to speedbin tables for each frequency. NOTE 6 When CL is equal to 24 or more than 24, AL does not support CL-1. Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 15 ® Long-term Support World Class Quality IS43/46QR16256A Burst Length, Type, and Order Accesses within a given burst may be programmed to sequen al or interleaved order. The ordering of accesses within a burst is determined by the burst length, burst type, and the star ng column address as shown in the following Burst Type and Burst Order table. Burst length op ons include xed BC4, xed BL8, and on-the- y (OTF), which allows BC4 or BL8 to be selected coincident with the registra on of a READ or WRITE command via A12/ BC. Burst Length READ/ WRITE StarƟng Column Address Burst Type (Decimal) SequenƟal Interleaved Notes A2 A1 A0 B0 B1 B2 B3 B4 B5 B6 B7 B0 B1 B2 B3 B4 B5 B6 B7 READ BC4 WRITE BL8 READ WRITE 0 0 0 0 1 2 3 T T T T 0 1 2 3 T T T T 1,3 0 0 1 1 2 3 0 T T T T 1 0 3 2 T T T T 1,2,3 0 1 0 2 3 0 1 T T T T 2 3 0 1 T T T T 1,2,3 0 1 1 3 0 1 2 T T T T 3 2 1 0 T T T T 1,2,3 1 0 0 4 5 6 7 T T T T 4 5 6 7 T T T T 1,2,3 1 0 1 5 6 7 4 T T T T 5 4 7 6 T T T T 1,2,3 1 1 0 6 7 4 5 T T T T 6 7 4 5 T T T T 1,2,3 1 1 1 7 4 5 6 T T T T 7 6 5 4 T T T T 1,2,3 0 V V 0 1 2 3 X X X X 0 1 2 3 X X X X 1,2,4,5 1 V V 4 5 6 7 X X X X 4 5 6 7 X X X X 1,2,4,5 0 0 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 2 0 0 1 1 2 3 0 5 6 7 4 1 0 3 2 5 4 7 6 2 0 1 0 2 3 0 1 6 7 4 5 2 3 0 1 6 7 4 5 2 0 1 1 3 0 1 2 7 4 5 6 3 2 1 0 7 6 5 4 2 1 0 0 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 2 1 0 1 5 6 7 4 1 2 3 0 5 4 7 6 1 0 3 2 2 1 1 0 6 7 4 5 2 3 0 1 6 7 4 5 2 3 0 1 2 1 1 1 7 4 5 6 3 0 1 2 7 6 5 4 3 2 1 0 2 V V V 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 2,4 NOTE 1 In the case of se ng burst l ength to BC4 ( xed) in MR0, the internal WRITE opera on starts two clock cycles earlier than for the BL8 mode. This means that the star ng point for tWR and tWTR will be pulled in by two clocks. In the case of se ng burst length to on-the- y in MR0, the internal WRITE opera on starts at the same point in me as a BL8 (even if BC4 was selected during column me using A12/BC4). This means that if the on-the- y MR0 se ng is used, the star ng point for tWR and tWTR will not be pulled in by two clocks as described in the BC4 ( xed) case. NOTE 2 Bit number(B0…B7) is the value of CA[2:0] that causes this bit to be the rst READ during a burst. NOTE 3 T = Output driver for data and strobes are in High-Z. NOTE 4 V = Valid logic level (0 or 1), but respec ve bu er input ignores level on input pins. NOTE 5 X = “Don’t Care.” CAS Latency (CL) The CAS latency se ng is de ned in the MR0 Register De ni on table. CAS latency is the delay, in clock cycles, between the internal READ command and the availability of the rst bit of output data. DDR4 SDRAM does not support any half-clock latencies. The overall read latency (RL) is de ned as addi ve latency (AL) + CAS latency (CL); RL = AL + CL. Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 16 IS43/46QR16256A ® Long-term Support World Class Quality Test Mode The normal opera ng mode is selected by MR0[7] and all other bits set to the desired values shown in the MR0 Register De ni on table. Programming MR0[7] to a 1 places the DDR4 SDRAM into a DRAM manufacturer de ned test mode that is to be used only by the DRAM manufacturer; and should not be used by the end user. No opera ons or func onality is speci ed if MR0[7] = 1. Write Recovery/Read to Precharge The programmed WR value MR0[11:9] is used for the auto precharge feature along with tRP to determine tDAL. WR (write recovery for auto precharge) MIN in clock cycles is calculated by dividing tWR (in ns) by tCK (in ns) and rounding up to the next integer: WRmin[cycles] = roundup (tWR[ns]/tCK[ns]) The WR must be programmed to be equal to or larger than tWR(MIN). When both DM and Write CRC are enabled in the DRAM mode register, the DRAM calculates CRC before sending the write data into the array; tWR values will change when enabled. If there is a CRC error, the DRAM blocks the write opera on and discards the data. RTP (internal READ command to PRECHARGE command delay for auto precharge) min in clock cycles is calculated by dividing tRTP (in ns) by tCK (in ns) and rounding up to the next integer: RTPmin[cycles] = roundup (tRTP[ns]/tCK[ns]) The RTP value in the mode register must be programmed to be equal or larger than RTPmin. The programmed RTP value is used with tRP to determine the act ming to the same bank. DLL Reset The DLL reset bit is self-clearing, meaning that it returns back to the value of 0 a er the DLL reset func on has been issued. A er the DLL is enabled, a subsequent DLL RESET should be applied. Any me that the DLL reset func on is used, tDLLK must be met before any func ons that require the DLL can be used (for example, READ commands or ODT synchronous opera ons). Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 17 ® Long-term Support World Class Quality IS43/46QR16256A Mode Register 1 (MR1) BG0 BA1 BA0 ņ MR Select ņ A12 BG0 RAS / CAS / A16 A15 WE/ A14 ņ A13 RFU Qoī (Data output disable) 1 A12 Qoī A11 2 A10 A9 TDQS A11 TDQS A8 RTT_NOM A7 Wlev A7 Write Leveling A6 A5 A4 A3 RFU 1 AL A2 A1 ODI DLL ODI Enabled (normal opera on) 0 Disabled 0 Disabled 0 0 RZQ/7(34 ohm) 1 Disabled (both ODI & RTT) 1 Enabled 1 Enabled 0 1 RZQ/5(48 ohm) 1 0 RFU 1 1 RFU MR Select A10 A9 A8 RTT_NOM A4 A3 AL A0 DLL 0 Disabled 1 Enabled 0 0 0 MR0 0 0 0 Disabled 0 0 Disabled 0 0 1 MR1 0 0 1 RZQ/4 (60 ) 0 1 CL-1 0 1 0 MR2 0 1 0 RZQ/2 (120 ) 1 0 CL-2 0 1 1 MR3 0 1 1 RZQ/6 (40 ) 1 1 RFU 1 0 0 MR4 1 0 0 RZQ/1 (240 ) 1 0 1 MR5 1 0 1 RZQ/5 (48 ) 1 1 0 MR6 1 1 0 RZQ/3 (80 ) 1 4 1 1 1 RZQ/7 (34 ) 1 A1 A0 0 BA1 BA0 1 A2 DNU 5 3 NOTE 1 Please refer to addressing table. If the address is available, it must be programmed to 0 during MRS NOTE 2 Outputs disabled - DQs, DQSs, DQSs. NOTE 3 States reversed to “0 as Disable” with respect to DDR4. NOTE 4 Reserved for Register control word se ng. DRAM ignores MR command with BG0,BA[1:0]=111 and doesn’t respond. NOTE 5 Not allowed when 1/4 rate geardown mode is enabled. Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 18 IS43/46QR16256A ® Long-term Support World Class Quality DLL Enable/DLL Disable The DLL must be enabled for normal opera on and is required during power-up ini aliza on and upon returning to normal opera on a er having the DLL disabled. During normal opera on, (DLL-enabled) with MR1[0], the DLL is automa cally disabled when entering the SELF REFRESH opera on and is automa cally re-enabled upon exit of the SELF REFRESH opera on. Any me the DLL is enabled and subsequently reset, tDLLK clock cycles must occur before a READ or SYNCHRONOUS ODT command can be issued to allow me for the internal clock to be synchronized with the external clock. Failing to wait for synchroniza on to occur may result in a viola on of the tDQSCK, tAON, or tAOF parameters. During tDLLK, CKE must con nuously be registered HIGH. DDR4 SDRAM does not require DLL for any WRITE opera on, except when RTT_WR is enabled and the DLL is required for proper ODT opera on. The direct ODT feature is not supported during DLL-o mode. The ODT resistors must be disabled by con nuously registering the ODT pin LOW and/or by programming the RTT_NOM bits MR1[9,6,2] = 000 via a MODE REGISTER SET command during DLL-o mode. The dynamic ODT feature is not supported in DLL-o mode; to disable dynamic ODT externally, use the MRS command to set RTT_WR, MR2[10:9] = 00. Output Driver Impedance Control The output driver impedance of the DDR4 SDRAM device is selected by MR1[2,1]. ODT RTT_NOM Values DDR4 SDRAM is capable of providing three di erent termina on values: RTT_Sta c, RTT_NOM, and RTT_WR. The nominal termina on value, RTT_NOM, is programmed in MR1. A separate value (RTT_WR) may be programmed in MR2 to enable a unique RTT value when ODT is enabled during WRITEs. The RTT_WR value can be applied during WRITEs even when RTT_NOM is disabled. A third RTT value, RTT_Sta c, is programed in MR5. RTT_Sta c provides a termina on value when the ODT signal is LOW. Additive Latency (AL) The addi ve latency (AL) opera on is supported to make command and data bus e cient for sustainable bandwidths in DDR4 SDRAM. In this opera on, the DDR4 SDRAM allows a READ or WRITE command (either with or without AUTO PRECHARGE) to be issued immediately a er the ACTIVE command. The command is held for the me of AL before it is issued inside the device. The read latency (RL) is controlled by the sum of the AL and CAS latency (CL) register se ngs. Write latency (WL) is controlled by the sum of the AL and CAS write latency (CWL) register se ngs. Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 19 ® Long-term Support World Class Quality IS43/46QR16256A Write Leveling For be er signal integrity, DDR4 memory modules use y-by topology for the commands,addresses, control signals, and clocks. Fly-by topology has the bene t of reducing the number of stubs and their length, but it also causes ight- me skew between clock and strobe at every DRAM on the DIMM. This makes it di cult for the controller to maintain tDQSS, tDSS, and tDSH speci ca ons. Therefore, the DDR4 SDRAM supports a write-leveling feature, which allows the controller to compensate for skew. Output Disable The DDR4 SDRAM outputs may be enabled/disabled by MR1[12]. When MR1[12] = 1 is enabled, all output pins (such as DQ, DQS, and DQS) are disconnected from the device, which removes any loading of the output drivers. This feature may be useful when measuring module power, for example.For normal opera on, set MR1[12] = 0. Termination Data Strobe (TDQS) Termina on data strobe (TDQS) is a feature of x8 DDR4 SDRAM and provides addi onal termina on resistance outputs that may be useful in some system con gura ons. Because the TDQS func on is available only in x8 DDR4 SDRAM, it must be disabled for x4 and x16 con gura ons. TDQS is not supported in x4 or x16 con gura ons. When enabled via the mode register, the same termina on resistance func on that is applied to the TDQS and TDQS pins is applied to the DQS and DQS pins. The TDQS, DBI, and data mask func ons share the same pin. When the TDQS func on is enabled via the mode register, the data mask and DBI func ons are not supported. When the TDQS func on is disabled, the data mask and DBI func ons can be enabled separately. TDQS Disabled Enabled Data Mask (DM) WRITE DBI READ DBI Enabled Disabled Enabled or disabled Disabled Enabled Enabled or disabled Disabled Disabled Enabled or disabled Disabled Disabled Disabled Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 20 ® Long-term Support World Class Quality IS43/46QR16256A Mode Register 2 (MR2) BG0 BA1 BA0 ņ ņ MR Select BG0 BA1 BA0 MR Select 0 0 0 MR0 0 0 1 MR1 0 1 0 0 1 1 RAS / CAS / A16 A15 ņ WE / A14 A13 RFU 1 A12 A11 Write CRC A10 A9 RTT_WR A8 A7 RFU 1 A6 LPASR A11 A10 A9 RTT_WR 0 0 0 Disabled(WRITE does not a ect RTT value) MR2 0 0 1 RZQ/2 (120 ) MR3 0 1 0 RZQ/1 (240 ) 1 0 0 MR4 0 1 1 Hi-Z 1 0 1 MR5 A12 Write CRC 1 0 0 RZQ/3 (80 ) 1 1 0 MR6 0 Disabled 1 0 1 RFU 1 1 1 DNU2 1 Enabled 1 1 0 RFU 1 1 1 RFU A7 A6 0 0 Manual Mode- Normal Operaing Temperature Range(TC: 0°C–85°C) 0 1 Manual Mode- Reduced Operaing Temperature Range(TC: 0°C–45°C) 1 0 Manual Mode- Extended Operaing Temperature Range(TC: 0°C–95°C) 1 1 ASR mode - Automa cally switching among all modes A5 A4 A3 A2 CWL A1 RFU A0 1 Low-power auto self refresh (LPASR) Speed Grade in MT/s A5 A4 A3 CWL 1 tCK tWPRE 2 tCK tWPRE 1st Set 2nd Set 1st Set 2nd Set 0 0 0 9 1600 - - - 0 0 1 10 1866 - - - 0 1 0 11 2133 1600 - - 0 1 1 12 2400 1866 - - 1 0 0 14 2666 2133 2400 - 1 0 1 16 3200 2400 2666 2400 1 1 0 18 - 2666 3200 2666 1 1 1 RFU - - - - NOTE 1 Please refer to addressing table. If the address is available, it must be programmed to 0 during MRS NOTE 2 Reserved for Register control word se ng. DRAM ignores MR command with BG0, BA[1:0]=111 and doesn’t respond. Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 21 IS43/46QR16256A ® Long-term Support World Class Quality CAS Write Latency (CWL) CAS write latency (CWL) is de ned by MR2[5:3] as shown in the MR2 Register De ni on table. CWL is the delay, in clock cycles, between the internal WRITE command and the availability of the rst bit of input data. DDR4 SDRAM does not support any half-clock latencies. The overall write latency (WL) is de ned as addi ve latency (AL) + CAS write latency (CWL); WL = AL + CWL. Low-Power Auto Self Refresh (LPASR) Low-power auto self refresh (LPASR) is supported in DDR4 SDRAM. Applica ons requiring SELF REFRESH opera on over di erent temperature ranges can use this feature to op mize the IDD6 current for a given temperature range as speci ed in the MR2 Register De ni on table. Dynamic ODT (RTT_WR) In certain applica ons and to further enhance signal integrity on the data bus, it is desirable to change the termina on strength of the DDR4 SDRAM without issuing an MRS command. Con gure the Dynamic ODT se ngs in MR2[11:9]. In write-leveling mode, only RTT_NOM is available. Write Cyclic Redundancy Check (CRC) Data Bus The Write cyclic redundancy check (CRC) data bus feature during Writes has been added to DDR4 SDRAM. When enabled via the mode register, the data transfer size goes from the normal 8-bit (BL8) frame to a larger 10-bit UI frame, and the extra 2UIs are used for the CRC informa on. Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 22 ® Long-term Support World Class Quality IS43/46QR16256A Mode Register 3 (MR3) BG0 BA1 ņ BA0 RAS / CAS / A16 ņ MR Select A15 WE / A14 ņ A13 RFU 1 A12 A11 MPR Read Format A10 A9 Write CMD Latency A12 A11 MPR Read Format A5 0 0 Seri a l 0 Disabled 0 1 Pa ra l l el 1 Enabled 1 0 Staggered 1 1 RFU Temperature sensor readout A8 A7 A6 Per DRAM Addressability 0 1 0 Page 0 0 1 Page 1 Enabled 1 0 Page 2 1 1 Page 3 4nCK 1600 0 5nCK 1866/2133/2400 1 1/4 ra te 1 0 RFU RFU 1 1 RFU RFU A2 MPR OperaƟon 0 Normal Opera on 1 Data ow from MPR 0 0 0 0 0 0 Fine Granularity Refresh d Norma l (Fi xed 1x) 0 0 1 MR1 0 0 1 Fi xed 2x 0 1 0 MR2 0 1 0 Fi xed 4x 0 1 1 MR3 0 1 1 RFU 1 0 0 MR4 1 0 0 RFU 1 0 1 MR5 1 0 1 On-the- y 1x/2x 1 1 0 MR6 1 1 0 On-the- y 1x/4x 1 1 1 DNU2 1 1 1 RFU BA1 A0 MPR Page SelecƟon 0 MR0 BG0 A1 Disabled(Normal Opera on) 0 A3 A2 MPR Page SelecƟon 1 Speed Bin A3 Geard MPR PDA own Operat A0 0 Write CMD Latency A4 A1 0 A9 TS A4 Geardown d 1/2 ra te A10 A5 Fine Granularity Refresh Mode BA0 MR Select A8 A7 A6 NOTE 1 Please refer to addressing table. If the address is available, it must be programmed to 0 during MRS NOTE 2 Reserved for Register control word se ng. DRAM ignores MR command with BG0,BA[1:0]=111 and doesn’t respond. Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 23 IS43/46QR16256A ® Long-term Support World Class Quality WRITE CMD latency when CRC/DM enabled The Write Command Latency (WCL) must be set when both Write CRC and DM are enabled for Write CRC persistent mode. This provides the extra me required when comple ng a Write burst when Write CRC and DM are enabled. Fine Granularity Refresh Mode This mode had been added to DDR4 to help combat the performance penalty due to refresh lockout at high densi es. Shortening tRFC and increasing cycle me allows more accesses to the chip and can produce higher bandwidth. Temp Sensor Status This mode directs the DRAM to update the temperature sensor status at MPR Page 2, MPR0 [4,3]. The temperature sensor se ng should be updated within 32ms; at the me of MPR Read of the Temperature Sensor Status bits, the temperature sensor status should be no older than 32ms. Per-DRAM Addressability The MRS command mask allows programmability of a given device that may be in the same rank (devices sharing the same command and address signals). As an example, this feature can be used to program di erent ODT or VREF values on DRAM devices within a given rank. Gear-down Mode The DDR4 SDRAM defaults in half-rate (1N) clock mode and u lizes a low frequency MRS command followed by a sync pulse to align the proper clock edge for opera ng the control lines CS, CKE, and ODT when in quarter-rate (2N) mode. For opera on in half-rate mode, no MRS command or sync pulse is required. Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 24 ® Long-term Support World Class Quality IS43/46QR16256A Mode Register 4 (MR4) BG0 BA1 MR Select BA0 ņ RAS / A16 CAS / WE/ A15 A14 ņ ņ RFU A12 tWPRE 0 1nCK toggl e 2nCK toggl e 1 A13 1 A12 A11 A10 A9 tRPRE SRF tWPRE tRPRE training abort A8 A7 A6 A5 CS to CMD/ADDR RFU Latency Mode A4 1 A3 Internal TCRM Vref A2 A1 A0 TCRR MPS RFU1 A10 READ preamble A4 Internal VREF monitor A1 3 0 Di s a bl ed 0 Di s a bl ed 0 Maximum power savings mode Norma l 4 1 Ena bl ed 1 Ena bl ed 1 Ena bl ed A11 tRPRE A9 Self refresh abort mode A3 Temperature controlled refresh mode A2 Temperature controlled refresh range 0 1nCK toggl e 3 0 Di s a bl ed 0 Di s a bl ed 0 Norma l tempera ture mode 1 2nCK toggl e 1 Ena bl ed 1 Ena bl ed 1 Extended tempera ture d BG0 BA1 BA0 MR Select A8 A7 A6 CAL 0 0 0 MR0 0 0 0 Di s a bl ed 0 0 1 MR1 0 0 1 3 0 1 0 MR2 0 1 0 4 0 1 1 MR3 0 1 1 5 1 0 0 MR4 1 0 0 6 1 0 1 MR5 1 0 1 8 1 1 0 MR6 1 1 0 RFU 1 1 1 DNU2 1 1 1 RFU NOTE 1 Please refer to addressing table. If the address is available, it must be programmed to 0 during MRS NOTE 2 Reserved for Register control word se ng .DRAM ignores MR command with BG0,BA[1:0]=111 and doesn’t respond. NOTE 3 Not allowed when 1/4 rate Gear-down mode is enabled. NOTE 4 When opera ng in 2tCK Write Preamble Mode, CWL must be programmed to a value at least 1 clock greater than the lowest CWL se ng supported in the applicable tCK range. Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 25 IS43/46QR16256A ® Long-term Support World Class Quality WRITE Preamble DDR4 SDRAM introduces a programmable WRITE preamble tWPRE that can either be set to 1tCK or 2 tCK via the MR3 register. Note the 1tCK se ng is similar to DDR3; however, the 2tCK se ng is di erent. When opera ng in 2tCK Write Preamble Mode, CWL must be programmed to a value at least 1 clock greater than the lowest CWL se ng supported in the applicable tCK range. Check the table of CWL Selec on for details. READ Preamble DDR4 SDRAM introduces a programmable READ preamble tRPRE that can be set to either 1tCK or 2tCK via the MR3 register. Note that both the 1tCK and 2tCK DDR4 preamble se ngs are di erent from what DDR3 SDRAM de ned. Both of these READ preamble se ngs may require the memory controller to train (or READ-level) its data strobe receivers using the READ preamble training. READ Preamble Training DDR4 supports programmable READ preamble se ngs (1tCK or 2tCK). This mode can be used by the memory controller to train or READ level its data strobe receivers. Temperature-Controlled Refresh (MR4[3] = 1 & MR2[6:7]=11) When temperature-controlled refresh mode is enabled, the DDR4 SDRAM may adjust the internal refresh period to be longer than tREFI of the normal temperature range by skipping external refresh commands with the proper gear ra o. For example, the DRAM temperature sensor detected less than 45° C. Normal temperature mode covers the range of 0° C to 85° C, while the extended temperature range covers 0° C to 95° C. Command Address Latency (CAL) DDR4 supports the command address latency (CAL) func on as a power savings feature. This feature can be enabled or disabled via the MRS se ng. CAL is de ned as the delay in clock cycles (tCAL) between a CS registered LOW and its corresponding registered command and address. The value of CAL (in clocks) must be programmed into the mode register and is based on the roundup (in clocks) of [tCK(ns)/tCAL(ns)]. Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 26 IS43/46QR16256A ® Long-term Support World Class Quality Internal Vref Monitor DDR4 generates its own internal VrefDQ. This mode is allowed to be enabled during VrefDQ training and when enabled, Vref_ me-short and Vref_ me-long need to be increased by 10ns if DQ0, or DQ1, or DQ2, or DQ3 have 0pF loading; and add an addi onal 15ns per pF of added loading. Maximum Power Savings Mode This mode provides the lowest power mode where data reten on is not required. When DDR4 SDRAM is in the maximum power saving mode, it does not need to guarantee data reten on or respond to any external command (except maximum power saving mode exit command and during the asser on of RESET signal LOW). Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 27 ® Long-term Support World Class Quality IS43/46QR16256A Mode Register 5 (MR5) BG0 BA1 ņ BA0 ņ MR Select RAS / CAS/ WE / A16 A15 A14 ņ A13 RTT_PARK ODT IB for PD 0 Di s a bl ed 0 Di s a bl ed 0 ODT Input Buīer for Power Down Ena bl ed 1 Ena bl ed 1 Ena bl ed 1 Di s a bl ed MR0 0 1 Ena bl ed 1 0 MR2 0 1 1 MR3 1 0 0 MR4 1 0 1 MR5 1 1 0 MR6 1 1 1 0 A53 A6 A5 MR1 0 RFU1 A7 WRITE DBI 1 0 0 A8 A11 0 0 DM A9 READ DBI Data mask (DM) Di s a bl ed BA0 A10 A12 A10 BA1 A11 RFU1 RDBI WDBI MR Select BG0 A12 DNU 2 A4 A3 RFU1 CRC error A2 A1 RFU1 0 CRC Error Status Cl ea r 1 Error A3 A0 Parked ODT Value (RTT_PARK) A8 A7 A6 0 0 0 Di s a bl ed 0 0 1 RZQ/4 (60 ) 0 1 0 RZQ/2 (120 ) 0 1 1 RZQ/6 (40 ) 1 0 0 RZQ/1 (240 ) 1 0 1 RZQ/5 (48 ) 1 1 0 RZQ/3 (80 ) 1 1 1 RZQ/7 (34 ) NOTE 1 Please refer to addressing table. If the address is available, it must be programmed to 0 during MRS NOTE 2 Reserved for Register control word se ng. DRAM ignores MR command with BG0,BA[1:0]=111 and doesn’t respond. NOTE 3 When RTT_NOM Disable is set in MR1, A5 of MR5 will be ignored. Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 28 IS43/46QR16256A ® Long-term Support World Class Quality Data Bus Inversion (DBI) The data bus inversion (DBI) func on has been added to DDR4 SDRAM and is supported for x8 and x16 con gura ons only (x4 is not supported). The DBI func on shares a common pin with the DM and TDQS func ons. The DBI func on applies to both READ and WRITE opera ons and cannot be enabled at the same me the DM func on is enabled. Refer to the TDQS Func on Matrix table for valid con gura ons for all three func ons (TDQS/DM/DBI). Data Mask (DM) The data mask (DM) func on, also described as a par al write, has been added to DDR4 SDRAM and is supported for x8 and x16 con gura ons only (x4 is not supported). The DM func on shares a common pin with the DBI and TDQS func ons. The DM func on applies only to WRITE opera ons and cannot be enabled at the same me the DBI func on is enabled. Refer to the TDQS Func on Matrix table for valid con gura ons for all three func ons (TDQS/DM/DBI). CA Parity Persistent Error Mode Normal CA Parity Mode (CA Parity Persistent Mode disabled) no longer performs CA parity checking while the parity error status bit remains set at 1. However, with CA Parity Persistent Mode enabled, CA parity checking con nues to be performed when the parity error status bit is set to a 1. ODT Input Buffer for Power Down Determines whether the ODT input bu er is on or o during Power Down. If the ODT input bu er is con gured to be on (enabled during power down), the ODT input signal must be at a valid logic level. If the input bu er is con gured to be o (disabled during power down), the ODT input signal may be oa ng and the DRAM does not provide R TT_NOM termina on. The DRAM may, however, provide R _Park termina on depending on the MR se ngs. This is primarily for addi onal power savings. CA Parity Error Status DRAM will set the error status bit to 1 upon detec ng a parity error. The parity error status bit remains set at 1 un l the DRAM Controller clears it explicitly using an MRS command. CRC Error Status DRAM will set the error status bit to 1 upon detec ng a CRC error. The CRC error status bit remains set at 1 un l the DRAM controller clears it explicitly using an MRS command. Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 29 ® Long-term Support World Class Quality IS43/46QR16256A Mode Register 6 (MR6) BG0 BA1 ņ BA0 ņ MR Select RAS/ CAS/ WE / A16 A15 A14 ņ A13 RFU A12 1 A11 A10 3 A9 A8 RFU tCCD_L 1 A7 A6 VrefDQ Training VrefDQ Range A5 A4 A3 A2 A1 A0 VrefDQ Training Value BG0 BA1 BA0 MR Select A12 A11 A10 tCCD_L.m in(nCK) Remark A7 VrefDQ Training Enable A6 VrefDQ Range 0 0 0 MR0 0 0 0 4 ” 2400Mbps 0 Di s a bl ed 0 Ra nge 1 0 0 1 MR1 0 0 1 5 TBD 1 Ena bl ed 1 Ra nge 2 0 1 0 MR2 0 1 0 6 TBD 0 1 1 MR3 0 1 1 7 TBD 1 0 0 MR4 1 0 0 8 TBD 1 0 1 MR5 1 0 1 RFU 1 1 0 MR6 1 1 0 RFU 1 1 1 DNU2 1 1 1 RFU MR6 Range 1 Range 2 MR6 Range 1 Range 2 MR6 Range 1 Range 2 [5:0] (MR6[6]=0) (MR6[6]=1) [5:0] (MR6[6]=0) (MR6[6]=1) [5:0] (MR6[6]=0) (MR6[6]=1) 00 0000 60.00% 45.00% 00 1101 68.45% 53.45% 01 1010 76.90% 61.90% MR6 [5:0] 10 0111 Range 1 Range 2 (MR6[6]=0) (MR6[6]=1) 85.35% 70.35% 00 0001 60.65% 45.65% 00 1110 69.10% 54.10% 01 1011 77.55% 62.55% 10 1000 86.00% 71.00% 00 0010 61.30% 46.30% 00 1111 69.75% 54.75% 01 1100 78.20% 63.20% 10 1001 86.65% 71.65% 00 0011 61.95% 46.95% 01 0000 70.40% 55.40% 01 1101 78.85% 63.85% 10 1010 87.30% 72.30% 00 0100 00 0101 62.60% 63.25% 47.60% 48.25% 01 0001 01 0010 71.05% 71.70% 56.05% 56.70% 01 1110 01 1111 79.50% 80.15% 64.50% 65.15% 10 1011 10 1100 87.95% 88.60% 72.95% 73.60% 00 0110 63.90% 48.90% 01 0011 72.35% 57.35% 10 0000 80.80% 65.80% 10 1101 89.25% 74.25% 00 0111 64.55% 49.55% 01 0100 73.00% 58.00% 10 0001 81.45% 66.45% 10 1110 89.90% 74.90% 00 1000 65.20% 50.20% 01 0101 73.65% 58.65% 10 0010 82.10% 67.10% 10 1111 90.55% 75.55% 00 1001 65.85% 50.85% 01 0110 74.30% 59.30% 10 0011 82.75% 67.75% 11 0000 91.20% 76.20% 00 1010 00 1011 66.50% 67.15% 51.50% 52.15% 01 0111 01 1000 74.95% 75.60% 59.95% 60.60% 10 0100 10 0101 83.40% 84.05% 68.40% 69.05% 91.85% 92.50% 76.85% 77.50% 00 1100 67.80% 52.80% 01 1001 76.25% 61.25% 10 0110 84.70% 69.70% 11 0001 11 0010 11 0011 to 111111 Reserved Reserved NOTE 1 Please refer to addressing table. If the address is available, it must be programmed to 0 during MRS NOTE 2 Reserved for Register control word se ng. DRAM ignores MR command with BG0,BA[1:0]=111 and doesn’t respond. NOTE 3 tCCD_L should be programmed according to the value de ned in AC parameter table per opera ng frequency. Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 30 IS43/46QR16256A ® Long-term Support World Class Quality tCCD_L Programming The DRAM Controller must program the correct tCCD_L value. tCCD_L will be programmed according to the value de ned in the AC parameter table per opera ng frequency. VREFDQ Training Enable VREFDQ Training is where the DRAM internally generates it’s own VREFDQ used by the DQ input receivers. The DRAM controller must use a MRS protocol (adjust up, adjust down, etc.) for se ng and calibra ng the internal VREFDQ level. The procedure is a series of Writes and Reads in conduc on with VREFDQ adjustments to op mize and verify the data eye. Enabling VREFDQ Training should be used whenever MR6[6:0] register values are being wri en to. VREFDQ Training Range DDR4 de nes two VREFDQ training ranges - Range 1 and Range 2. Range 1 supports VREFDQ between 60% and 92% of VDDQ while Range 2 supports VREFDQ between 45% and 77% of VDDQ. Range 1 is targeted for module based designs and Range 2 is added targe ng point-to point designs. VREFDQ Training Value Fi y se ngs provided 0.65% of granularity steps sizes for both Range 1 and Range 2 of VREFDQ. Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 31 ® Long-term Support World Class Quality IS43/46QR16256A Mode Register 7 (MR7) DRAM MR7 Ignore The DDR4 SDRAM shall ignore any access to MR7 for all DDR4 SDRAM.Any bit se ng within MR7 may not take any e ect in the DDR4 SDRAM. BG0 BA1 ņ BA0 ņ MR Select BG0 BA1 BA0 MR Select 0 0 0 MR0 0 0 1 MR1 0 1 0 MR2 0 1 1 MR3 1 0 0 MR4 1 0 1 MR5 1 1 0 MR6 1 1 1 DNU RAS / CAS / WE / A16 A15 A14 A13 A12 A11 A10 ņ A9 A8 A7 RFU A6 A5 A4 A3 A2 A1 A0 1 2 NOTE 1 Please refer to addressing table. If the address is available, it must be programmed to 0 during MRS NOTE 2 Reserved for Register control word se ng. DRAM ignores MR command with BG0,BA1;BA0=111 and doesn’t respond. Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 32 ® Long-term Support World Class Quality IS43/46QR16256A Truth Table Command Truth Table Note 1,2,3 and 4 apply to the entire Command truth table. Note 5 applies to all Read/Write commands. [BG = Bank group address;BA = Bank address; RA =Row address; CA = Column address; BC = Burst chop; X = Don’t Care; V = H or L] CKE Symbol Function Prev. Pres. MRS REF SRE MODE REGISTER SET Self refresh entry H H H H H L SRX Self refresh exit L H Single-bank PRECHARGE Device DESELECTED H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H PDE Power-down entry H L PDX Power-down exit L H ZQCL ZQCS ZQ CALIBRATION LONG H H H H PRE PREA RFU ACT WR WRS4 WRS8 WRA WRAS4 WRAS8 RD RDS4 RDS8 RDA RDAS4 RDAS8 NOP DES REFRESH PRECHARGE all banks Reserved for future use Bank ACTIVATE Fixed BL8 or BC4 WRITE BC4OTF BL8OTF WRITE with auto precharge Fixed BL8 or BC4 BC4OTF BL8OTF Fixed BL8 or BC4 READ BC4OTF BL8OTF READ with auto precharge Fixed BL8 or BC4 BC4OTF BL8OTF NO OPERATION ZQ CALIBRATION SHORT CS ACT L L L H L L L L L L L L L L L L L L L L L L H L H L H L L A A10 A RAS CAS WE BG BA C A12 Notes /A16 /A15 /A14 [1:0] [1:0] [2:0] / BC [13,11] /AP [9:0] H L L L H L L H H L L H X X X X H H H H H L H L H L H L H L H H L Row Address(RA) H H L L H H L L H H L L H H L L H H L L H H L L H H L H H H L H H H L H H H L H H H L H H H L H H H H H X X X X H H H H X X X X H H H H X X X X H H H L H H H L BG V V X V BG V BA V V X V BA V V V V X V V V BG BG BG BG BG BG BG BG BG BG BG BG BG V X V X V X X X BA BA BA BA BA BA BA BA BA BA BA BA BA V X V X V X X X V V V V V V V V V V V V V V X V X V X X X OP code 12 V V V V V V V V 7,9 X X X X 7,8,9,10 V V V V V V L V V V H V RFU Row Address(RA) V V L CA L V L CA H V L CA V V H CA L V H CA H V H CA V V L CA L V L CA H V L CA V V H CA L V H CA H V H CA V V V V 10 X X X X V V V V 6 X X X X 6 V V V V X X X X X X H X X X L X NOTE 1 All DDR4 SDRAM commands are de ned by states of CS, ACT , RAS/A16, CAS /A15, WE/A14 and CKE at the rising edge of the clock. The MSB of BG, BA, RA and CA are device density and conura on dependant. When ACT = H; pins RAS/A16, CAS /A15, and WE/A14 are used as command pins RAS, CAS , and WE respec vely. When ACT = L; pins RAS/A16, CAS /A15, and WE/A14 are used as address pins A16, A15, and A14 respec vely. NOTE 2 RESET is Low enable command which will be used only for asynchronous reset so must be maintained HIGH during any func on. NOTE 3 Bank Group addresses (BG) and Bank addresses (BA) determine which bank within a bank group to be operated upon. For MRS commands the BG and BA selects the speci c Mode Register loca on. NOTE 4 “V” means “H or L (but a de ned logic level)” and “X” means either “de ned or unde ned (like oa ng) logic level”. NOTE 5 Burst reads or writes cannot be terminated or interrupted and Fixed/on-the-Fly BL will be de ned by MRS. NOTE 6 The Power Down Mode does not perform any refresh opera on. NOTE 7 The state of ODT does not a ect the states described in this table. The ODT func on is not available during Self Refresh. NOTE 8 Controller guarantees self refresh exit to be synchronous. NOTE 9 VPP and VREF(VrefCA) must be maintained during Self Refresh opera on. NOTE 10 The No Opera on command should be used in cases when the DDR4 SDRAM is in Gear Down Mode and Max Power Saving Mode Exit NOTE 11 Refer to the CKE Truth Table for more detail with CKE transi on. Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 33 ® Long-term Support World Class Quality IS43/46QR16256A CKE Truth Table CKE Current State2 Previous Cycle1 (N-1) Present Cycle1 (N) Command (N) 3 RAS, CAS, WE, CS Action(N) 3 Notes L L X Maintain power down 14, 15 L H DESELECT Power down exit 11, 14 L L X Maintain self refresh 15, 16 L H DESELECT Self refresh exit 8, 12, 16 Bank(s) Ac ve H L DESELECT Ac ve power down entry 11, 13, 14 Reading H L DESELECT Power down entry 11, 13, 14, 17 Wri ng H L DESELECT Power down entry 11, 13, 14, 17 Precharging H L DESELECT Power down entry 11, 13, 14, 17 Refreshing H L DESELECT Precharge power down entry 11 H L DESELECT Precharge power down entry 11,13, 14, 18 L REFRESH Self refresh 9, 13, 18 Power Down Self Refresh All banks idle H For more details with all signals See “Command Truth Table”. NOTE 1 NOTE 2 NOTE 3 NOTE 4 NOTE 5 NOTE 6 NOTE 7 NOTE 8 NOTE 9 NOTE 10 NOTE 11 NOTE 12 NOTE 13 NOTE 14 NOTE 15 NOTE 16 NOTE 17 NOTE 18 NOTE 19 NOTE 20 CKE (N) is the logic state of CKE at clock edge N; CKE (N-1) was the state of CKE at the previous clock edge. Current state is de ned as the state of the DDR4 SDRAM immediately prior to clock edge N. COMMAND (N) is the command registered at clock edge N, and ACTION (N) is a result of COMMAND (N),ODT is not included here. All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document. The state of ODT does not a ect the states described in this table. The ODT func on is not available during Self-Refresh. During any CKE transi on (registra on of CKE H->L or CKE L->H), the CKE level must be maintained un l 1nCK prior to tCKEmin being sa s ed (at which me CKE may transi on again). DESELECT and NOP are de ned in the Command Truth Table. On Self-Refresh Exit DESELECT commands must be issued on every clock edge occurring during the tXS period. Read or ODT commands may be issued only a er tXSDLL is sa s ed. Self-Refresh mode can only be entered from the All Banks Idle state. Must be a legal command as de ned in the Command Truth Table. Valid commands for Power-Down Entry and Exit are DESELECT only. Valid commands for Self-Refresh Exit are DESELECT only except for Gear Down mode and Max Power Saving exit. NOP is allowed for these 2 modes. Self-Refresh can not be entered during Read or Write opera ons. For a detailed list of restric ons, see “Self-Refresh Opera on” and “Power-Down Modes”. The Power-Down does not perform any refresh opera ons. “X” means “don’t care“ (including oa ng around VREF) in Self-Refresh and Power-Down. It also applies to Address pins. VPP and VREF(VrefCA) must be maintained during Self-Refresh opera on. If all banks are closed at the conclusion of the read, write or precharge command, then Precharge Power-Down is entered, otherwise Ac ve Power-Down is entered. ‘Idle state’ is de ned as all banks are closed (tRP, tDAL, etc. sa s ed), no data bursts are in progress, CKE is high, and all mings from previous opera ons are sa s ed (tMRD, tMOD, tRFC, tZQinit, tZQoper, tZQCS, etc.) as well as all Self-Refresh exit and Power-Down Exit parameters are sa s ed (tXS, tXP,etc). Self refresh mode can be entered only from the all banks idle state. For more details about all signals, see the Command truth table; must be a legal command as de ned in the table. Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 10 34 IS43/46QR16256A ® Long-term Support World Class Quality NOP Command The NO OPERATION (NOP) command was originally used to instruct the selected DDR4 SDRAM to perform a NOP (CS = LOW and ACT, RAS/A16, CAS/A15, and WE/A14 = HIGH). This prevented unwanted commands from being registered during idle or wait states. The NOP command general support has been removed and should not be used unless speci cally allowed; which is when exi ng Max Power Saving Mode or when entering Gear-down Mode. DESELECT Command The DESELECT func on (CS HIGH) prevents new commands from being executed by the DDR4 SDRAM. The DDR4 SDRAM is e ec vely deselected. Opera ons already in progress are not a ected. Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 35 ® Long-term Support World Class Quality IS43/46QR16256A DLL On/Off DLL-Off Mode DLL-o mode is entered by se ng MR1 bit A0 to 0, which will disable the DLL for subsequent opera ons un l the A0 bit is set back to 1. The MR1 A0 bit for DLL control can be switched either during ini aliza on or during self refresh mode. Refer to Input Clock Frequency Change for more details. The maximum clock frequency for DLL-o mode is speci ed by the parameter tCKDLL_OFF. There is no minimum frequency limit besides the need to sa sfy the refresh interval, tREFI. Due to latency counter and ming restric ons, only one CL value in MR0 and CWL in MR2 is supported. The DLL-o mode is only required to support se ng both CL = 10 and CWL = 9. DLL-o mode will a ect the read data clock-to-data strobe rela onship (tDQSCK), but not the data strobe-to-data rela onship (tDQSQ, tQH). Special a en on is needed to line up read data to the controller me domain. Compared with DLL-on mode, where tDQSCK starts from the rising clock edge (AL + CL) cycles a er the READ command, the DLL-o mode tDQSCK starts (AL + CL - 1) cycles a er the READ command. Another di erence is that tDQSCK may not be small compared to tCK (it might even be larger than tCK), and the di erence between tDQSCK MIN and tDQSCK MAX is signi cantly larger than in DLL-on mode. The tDQSCK (DLL_o ) values are vendor-speci c. DLL-Off Mode Read Timing Operation T0 T1 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 CK CK CMD BA RD A DQSdiff_DLL_on RL=AL+CL=10 (CL=10, AL=0) CL=10 DQ_DLL_on RL (DLL_diff = AL + (CL-1) = 9 f tDQSCK(DLL_off)_min DQSdiff_DLL_off DQ_DLL_off tDQSCK(DLL_off)_max DQSdiff_DLL_off DQ_DLL_off Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 36 IS43/46QR16256A ® Long-term Support World Class Quality DLL On/Off Switching Procedure DDR4 DLL-o mode is entered by se ng MR1 bit A0 to 1; this will disable the DLL for subsequent opera ons un l the A0 bit is set back to 0. To switch from DLL on to DLL o requires the frequency to be changed during self refresh, as outlined in the following procedure: 1. Star ng from the idle state (all banks pre-charged, all mings ful lled, and DRAM on-die termina on resistors, RTT_NOM, must be in the high impedance state before MRS to MR1 to disable the DLL.) 2. Set MR1 bit A0 to 1 to disable the DLL. 3. Wait tMOD. 4. Enter self refresh mode; wait un l (tCKSRE) is sa s ed. 5. Change frequency, following the guidelines in the Input Clock Frequency Change sec on. 6. Wait un l a stable clock is available for at least (tCKSRX) at DRAM inputs. 7. Star ng with the SELF REFRESH EXIT command, CKE must con nuously be registered HIGH un l all tMOD mings from any MRS command are sa s ed. In addi on, if any ODT features were enabled in the mode registers when self refresh mode was entered, the ODT signal must con nuously be registered LOW un l all tMOD mings from any MRS command are sa s ed. If RTT_NOM was disabled in the mode registers when self refresh mode was entered, the ODT signal is "Don't Care." 8. Wait tXS_FAST, tXS_ABORT, or tXS, and then set mode registers with appropriate values (an update of CL, CWL, and WR may be necessary; a ZQCL command can also be issued a er tXS_FAST). tXS: ACT, PRE, PREA, REF, SRE, PDE, WR, WRS4, WRS8, WRA, WRAS4, WRAS8, RD, RDS4, RDS8, RDA, RDAS4, RDAS8 tXS_FAST: ZQCL, ZQCS, MRS commands. For MRS commands, only CL and WR/RTP registers in MR0, the CWL register in MR2, and geardown mode in MR3 are allowed to be accessed provided the device is not in per-device addressability mode. Access to other device mode registers must sa sfy tXS ming. tXS_ABORT: If the bit is enabled, then the device aborts any ongoing refresh and does not increment the refresh counter. The controller can issue a valid command a er a delay of tXS_ABORT. Upon exi ng from self refresh, the DDR4 SDRAM requires a minimum of one extra REFRESH command before it is put back into self refresh mode. This requirement remains the same regardless of the se ng of the MRS bit for self refresh abort. 9. Wait for tMOD, and then the DRAM is ready for the next command. Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 37 ® Long-term Support World Class Quality IS43/46QR16256A DLL Switch Sequence from DLL On to DLL Off CK Ta Tb0 Tb1 Tc Td Te0 Te1 Tf Tg Th VALID VALID VALID CK tIS tCPDED tCKSRE 4 tCKSRX5 CKE tCKESR tIS ODT VALID tMOD COMMAND MRS2) ADDR tXS_FAST SRE3) DES SRX VALID VALID VALID VALID VALID VALID 6) VALID tXS_ABORT tRP tXS Enter Self Refresh Exit Self Refresh DON’ T CARE NOTE 1 NOTE 2 NOTE 3 NOTE 4 NOTE 5 NOTE 6 NOTE 7 Star ng in the idle state. RTT in stable state. Disable DLL by se ng MR1 bit A0 to 0. Enter SR. Change frequency. Clock must be stable tCKSRX. Exit SR. Update mode registers allowed with DLL_o se ngs met. Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 TIME BREAK 38 IS43/46QR16256A ® Long-term Support World Class Quality DLL Off to DLL On Procedure To switch from DLL o to DLL on (with required frequency change) during self refresh: 1. Star ng from the idle state (all banks pre-charged, all mings ful lled, and DRAM on-die termina on resistors (RTT) must be in the high impedance state before self refresh mode is entered.) 2. Enter self refresh mode; wait un l tCKSRE sa s ed. 3. Change frequency, following the guidelines in the Input Clock Frequency Change sec on. 4. Wait un l a stable clock is available for at least (tCKSRX) at DRAM inputs. 5. Star ng with the SELF REFRESH EXIT command, CKE must con nuously be registered HIGH un l tDLLK ming from the subsequent DLL RESET command is sa s ed. In addi on, if any ODT features were enabled in the mode registers when self refresh mode was entered, the ODT signal must con nuously be registered LOW or HIGH un l tDLLK mings from the subsequent DLL RESET command is sa s ed. If RTT_NOM disabled in the mode registers when self refresh mode was entered, the ODT signal is "Don't Care." 6. Wait tXS or tXS_ABORT, depending on bit x in RMy, then set MR1 bit A0 to 0 to enable the DLL. 7. Wait tMRD, then set MR1 bit A8 to 1 to start DLL Reset. 8. Wait tMRD, then set mode registers with appropriate values (an update of CL, CWL, and WR may be necessary. A er tMOD is sa s ed from any proceeding MRS command, a ZQCL command can also be issued during or a er tDLLK.) 9. Wait for tMOD, then DRAM is ready for the next command. (Remember to wait tDLLK a er DLL RESET before applying any command requiring a locked DLL.) In addi on, wait for tZQoper in case a ZQCL command was issued. Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 39 ® Long-term Support World Class Quality IS43/46QR16256A DLL Switch Sequence from DLL Off to DLL On CK Ta Tb0 Tb1 Tc Td Te0 Te1 Tf Tg Th CK tIS tCPDED tCKSRF 3 tCKSRX4 CKE VALID VALID VALID tCKESR tIS VALID ODT tXS_ABORT COMMAND DES SRF ADDR 2 DES SRF 5 VALID tRP Enter Self Refresh NOTE 1 NOTE 2 NOTE 3 NOTE 4 NOTE 5 NOTE 6 NOTE 7 NOTE 8 VALID VALID VALID VALID VALID tXS Exit Self Refresh DON’ T CARE tMRD TIME BREAK Star ng in the idle state. Enter SR. Change frequency. Clock must be stable tCKSRX. Exit SR. Set DLL to on by se ng MR1 ro A0 = 0. Update mode registers. Issue any valid command. Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 VALID 40 IS43/46QR16256A ® Long-term Support World Class Quality Input Clock Frequency Change A er the DDR4 SDRAM is ini alized, the DDR4 SDRAM requires the clock to be stable during almost all states of normal opera on. This means that a er the clock frequency has been set and is to be in the stable state, the clock period is not allowed to deviate except for what is allowed for by the clock ji er and SSC (spread spectrum clocking) speci ca ons. The input clock frequency can be changed from one stable clock rate to another stable clock rate only when in self refresh mode. Outside of self refresh mode, it is illegal to change the clock frequency. A er the DDR4 SDRAM has been successfully placed in self refresh mode and tCKSRE has been sa s ed, the state of the clock becomes a "Don’t Care." Following a "Don’t Care," changing the clock frequency is permissible, provided the new clock frequency is stable prior to tCKSRX. When entering and exi ng self refresh mode for the sole purpose of changing the clock frequency, the self refresh entry and exit speci ca ons must s ll be met as outlined in Self-Refresh Opera on. Because DDR4 DLL lock me ranges from 597nCK at 1333MT/s to 1024nCK at 3200MT/s, addi onal MRS commands may need to be issued for the new clock frequency. If DLL is enabled, tDLLK must be programmed according to the value de ned in AC parameter tables, and the DLL must be RESET by an explicit MRS command (MR0[8]=1) when the input clock frequency is di erent before and a er self refresh. The DDR4 SDRAM input clock frequency can change only within the minimum and maximum opera ng frequency speci ed for the par cular speed grade. Any frequency change below the minimum opera ng frequency would require the use of DLL_on mode to DLL_o mode transi on sequence (see DLL On/O Switching Procedure). Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 41 ® Long-term Support World Class Quality IS43/46QR16256A Write Leveling For be er signal integrity, the DDR4 memory module adopted y-by topology for the commands, addresses, control signals, and clocks. The y-by topology has bene ts from reducing number of stubs and their length, but it also causes ight me skew between clock and strobe at every DRAM on the DIMM. This makes it di cult for the Controller to maintain tDQSS, tDSS, and tDSH speci ca on. Therefore, the DDR4 SDRAM supports a write-leveling feature to allow the controller to compensate for skew. This feature may not be required under some system condi ons, provided the host can maintain the tDQSS, tDSS, and tDSH speci ca ons. The memory controller can use the write leveling feature and feedback from the DDR4 SDRAM to adjust the DQS - DQS to CK - CK rela onship. The memory controller involved in the leveling must have an adjustable delay se ng on DQS DQS to align the rising edge of DQS - DQS with that of the clock at the DRAM pin. The DRAM asynchronously feeds back CK - CK, sampled with the rising edge of DQS - DQS, through the DQ bus. The controller repeatedly delays DQS - DQS un l a transi on from 0 to 1 is detected. The DQS - DQS delay established though this exercise would ensure tDQSS speci ca on. Besides tDQSS, tDSS and tDSH speci ca on also needs to be ful lled. One way to achieve this is to combine the actual tDQSS in the applica on with an appropriate duty cycle and ji er on the DQS - DQS signals. Depending on the actual tDQSS in the applica on, the actual values for tDQSL and tDQSH may have to be be er than the absolute limits provided in the AC Timing Parameters sec on in order to sa sfy tDSS and tDSH speci ca on. A conceptual ming of this scheme is shown below. Write-Leveling Concept T0 T1 T2 T3 T4 T5 T6 T7 CK Source CK diff_DQS Destination CK Tn T0 T1 T2 T3 T4 T5 T6 CK diff_DQS All DQs 0 or 1 0 0 0 Push DQS to capture 0-1 transition diff_DQS All DQs 0 or 1 1 1 1 DQS - DQS driven by the controller during leveling mode must be terminated by the DRAM based on the ranks populated. Similarly, the DQ bus driven by the DRAM must also be terminated at the controller. All data bits carry the leveling feedback to the controller across the DRAM con gura ons x4, x8, and x16. On a x16 device, both byte lanes should be leveled independently. Therefore, a separate feedback mechanism should be available for each byte lane. The upper data bits should provide the feedback of the upper di _DQS(di _UDQS)-to-clock rela onship; the lower data bits would indicate the lower di _DQS(di _LDQS)-to-clock rela onship. Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 42 ® Long-term Support World Class Quality IS43/46QR16256A The Figure below is another representa ve way to view the write leveling procedure. Although it shows the clock varying to a sta c strobe, this is for illustra ve purpose only; the clock does not actually change phase, the strobe is what is actually varied. By issuing mul ple WL bursts, the DQS strobe can be varied to capture when the clock edge arrives at the DRAM clock input bu er fairly accurately. DRAM Setting for Write Leveling and DRAM Termination Function in that Mode DRAM enters into write leveling mode if A7 in MR1 is HIGH, and a er nishing leveling, DRAM exits write leveling mode if A7 in MR1 is LOW (see the MR leveling table below). Note that in write leveling mode, only DQS/DQS termina ons are ac vated and deac vated via the ODT pin, unlike normal opera on (see DRAM termina on table below). MR Settings for Leveling Procedures FuncƟon MR1 Enable Disable Write Leveling enable A7 1 0 Qo (Data output disable) A12 0 1 DRAM Termination Function in Leveling Mode DQS/DQS TerminaƟon DQ TerminaƟon RTT_NOM with ODT HIGH On O RTT_PARK with ODT LOW On O ODT Pin at DRAM NOTE 1 In write-leveling mode with its output bu er disabled (MR1[bit7] = 1 with MR1[bit12] =1) all RTT_NOM and RTT_PARK se ngs are supported; in write-leveling mode with its output bu er enabled (MR1[bit7] = 1 with MR1[bit12] = 0) RTT_NOM and RTT_PARK se ngs are supported while RTT_WR i s not allowed. Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 43 IS43/46QR16256A ® Long-term Support World Class Quality Procedure Description The memory controller ini ates the leveling mode of all DRAM by se ng bit 7 of MR1 to 1. When entering write leveling mode, the DQ pins are in unde ned driving mode. During write leveling mode, only the DESELECT command is supported, as well as an MRS command to change the Qo bit (MR1[A12]) and an MRS command to exit write leveling (MR1[A7]). Upon exi ng write leveling mode, the MRS command performing the exit (MR1[A7] = 0) may also change the other MR1 bits. Because the controller levels one rank at a me, the output of other ranks must be disabled by se ng MR1 bit A12 to 1. The controller may assert ODT a er tMOD, at which me the DRAM is ready to accept the ODT signal. The controller may drive DQS LOW and DQS HIGH a er a delay of tWLDQSEN, at which me the DRAM has applied on-die termina on on these signals. A er tDQSL and tWLMRD, the controller provides a single DQS, DQS edge which is used by the DRAM to sample CK - CK driven from the controller. tWLMRD(max) ming is controller dependent. DRAM samples CK - CK status with the rising edge of DQS - DQS and provides feedback on all the DQ bits asynchronously a er tWLO ming. There is a DQ output uncertainty of tWLOE de ned to allow mismatch on DQ bits. The tWLOE period is de ned from the transi on of the earliest DQ bit to the corresponding transi on of the latest DQ bit. There are no read strobes (DQS, DQS) needed for these DQs. Controller samples incoming DQ and decides to increment or decrement DQS - DQS delay se ng and launches the next DQS - DQS pulse a er some me, which is controller dependent. A er a 0-to-1 transi on is detected, the controller locks the DQS - DQS delay se ng, and write leveling is achieved for the device. The following gure shows the ming diagram and parameters for the overall write leveling procedure. Write-Leveling Sequence NOTE 1 DDR4 SDRAM drives leveling feedback on all DQs NOTE 2 MRS : Load MR1 to enter write leveling mode NOTE 3 DES : Deselect NOTE 4 di _DQS is the di eren al data strobe (DQS-DQS). Timing reference points are the zero crossings. DQS is shown with solid line, DQS is shown with do ed line NOTE 5 CK/CK : CK is shown with solid dark line, where as CK is drawn with do ed line. NOTE 6 DQS , DQS needs to ful ll minimum pulse width requirements tDQSH(min) and tDQSL(min) as de ned for regular Writes; the max pulse width is system dependent NOTE 7 tMOD(Min) = max(24nCK, 15ns), WL = 9 (CWL = 9, AL = 0, PL = 0), DODTLon = WL -2 = 7 NOTE 8 tWLDQSEN must be sa s ed following equa on when using ODT. - tWLDQSEN > tMOD(Min) + ODTLon + tADC : at DLL = Enable - tWLDQSEN > tMOD(Min) + tAONAS : at DLL = Disable Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 44 ® Long-term Support World Class Quality IS43/46QR16256A Write-Leveling Mode Exit Write leveling mode should be exited as follows: 1. A er the last rising strobe edge (see ~T0), stop driving the strobe signals (see ~Tc0). Note that from this point now on, DQ pins are in unde ned driving mode and will remain unde ned, un l tMOD a er the respec ve MR command (Te1). 2. Drive ODT pin LOW (tIS must be sa s ed) and con nue registering LOW (see Tb0). 3. A er the RTT is switched o , disable write-leveling mode via the MRS command (see Tc2). 4. A er tMOD is sa s ed (Te1), any valid command can be registered. (MR commands can be issued a er tMRD [Td1]). Write-Leveling Exit CK T0 T1 T2 Ta0 Tb0 Tc0 DES DES DES DES DES DES Tc1 Tc2 DES MRS Td0 Td1 Te0 Te1 DES VALID CK COMMAND DES MRS tMRD ADDRESS VALID tMOD tIS ODT ODTLoff tADCmin RTT_NOM DQS, DQS RTT_NOM RTT_PARK tADCmax DQS, DQS RTT_NOM All DQs DQs tWLO Result=1 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 45 ® Long-term Support World Class Quality IS43/46QR16256A CS to Command Address Latency (CAL) DDR4 supports the Command Address Latency (CAL) func on as a power savings feature. This feature can be enabled or disabled via the MRS se ng. CAL ming is de ned as the delay in clock cycles (tCAL) between a CS registered LOW and its corresponding registered command and address. The value of CAL in clocks must be programmed into the mode register (see MR1 Register De ni on table) and is based on the equa on tCK(ns) / tCAL(ns), rounded up in clocks. CAL Timing Definition 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 CK CS CMD/ADDR tCAL CS used to wake up the receivers. CAL gives the DRAM me to enable the command and address receivers before a command is issued. A er the command and the address are latched, the receivers can be disabled if CS returns to HIGH. For consecu ve commands, the DRAM will keep the command and address input receivers enabled for the dura on of the command sequence. CAL Timing Example (Consecutive CS = LOW) 1 2 3 4 5 6 7 8 9 10 11 12 CK CS CMD/ADDR When the Command Address Latency mode, CAL, is enabled; addi onal me is required for the MRS command to complete. The earliest the next valid command can be issued is tMOD_CAL which should be equal to tMOD+tCAL. The two following gures are examples. Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 46 ® Long-term Support World Class Quality IS43/46QR16256A CAL Enable Timing - tMOD_CAL Ta0 Ta1 Ta2 MRS DES Tb0 Tb1 Tb2 Tc0 MRS DES VALID CK CK COMMAND (w/o CS) DES CS tCAL tMOD_CAL NOTE 1 Command Address Latency mode is enabled at T1. tMOD_CAL, MRS to Valid Command Timing with CAL Enabled T0 Ta0 Ta1 Ta2 Tb0 Tb1 MRS DES DES DES Tb2 Tc0 CK CK COMMAND (w/o CS) CS DES VALID tCAL tCAL tMOD_CAL NOTE 1 MRS at Ta1 may or may not modify CAL, tMOD_CAL is computed based on new tCAL se ng if modi ed. When the Command Address Latency mode is enabled or being enabled, the earliest the next MRS command can be issued is tMRD_CAL is equal to tMOD+tCAL. The two following gures are examples. CAL Enabling MRS to Next MRS Command, tMRD_CAL Ta0 Ta1 Ta2 Tb0 Tb1 Tb2 Tc0 CK CK COMMAND (w/o CS) MRS DES DES DES DES MRS CS tCAL tMRD_CAL NOTE 1 Command Address Latency mode is enabled at T1. Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 47 ® Long-term Support World Class Quality IS43/46QR16256A tMRD_CAL, Mode Register Cycle Time With CAL Enabled T0 Ta0 Ta1 Ta2 Tb0 Tb1 Tb2 Tc0 MRS DES DES DES DES MRS CK CK COMMAND (w/o CS) CS tCAL tCAL tMRD_CAL NOTE 1 MRS at Ta1 may or may not modify CAL, tMRD_CAL is computed based on new tCAL se ng if modi ed. Command Address Latency Examples: Consecu ve READ BL8 with two di erent CALs and 1tCK Preamble in Di erent Bank Group shown in gures below. Self Refresh Entry, Exit Timing with CAL NOTE 1 tCAL = 3nCK, tCPDED = 4nCK, tCKSRE = 8nCK, tCKSRX = 8nCK, tXS_FAST = tRFC4(min) + 10ns NOTE 2 CS = H, ACT = Don't Care, RAS /A16 = Don't Care, CAS /A15 = Don't Care, WE/A14 = Don't Care NOTE 3 Only MRS (limited to those described in the Self-Refresh Opera on sec on). ZQCS or ZQCL command allowed. Power Down Entry, Exit Timing with CAL NOTE 1 tCAL = 3nCK, tCPDED = 4nCK, tPD = 6nCK, tXP = 5nCK Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 48 ® Long-term Support World Class Quality IS43/46QR16256A Low-Power Auto Self Refresh Mode (LPASR) An auto self refresh mode is provided for applica on ease. Auto self refresh mode is enabled by se ng MR2[6] = 1 and MR2[7] = 1. The device will manage self refresh entry over the supported temperature range of the DRAM. In this mode, the device will change its self refresh rate as the DRAM opera ng temperature changes, going lower at low temperatures and higher at high temperatures. Manual Self Refresh Mode If auto self refresh mode is not enabled, the low-power auto self refresh mode register must be manually programmed to one of the three self refresh opera ng modes. This mode provides the exibility to select a xed self refresh opera ng mode at the entry of the self refresh, according to the system memory temperature condi ons. The user is responsible for maintaining the required memory temperature condi on for the mode selected during the self refresh opera on. The user may change the selected mode a er exi ng self refresh and before entering the next self refresh. If the temperature condi on is exceeded for the mode selected, there is a risk to data reten on resul ng in loss of data. Auto Self Refresh Mode MR2 [7] MR2 [6] Low-Power Auto Self Refresh Mode 0 0 Normal 0 1 Extended Temp 1 0 Reduced Temp 1 1 Auto Self Refresh Self Refresh OperaƟon Fixed normal self refresh rate maintains data reten on at the normal opera ng temperature. User is required to ensure that 85°C DRAM TCASEMAX is not exceeded to avoid any risk of data loss. 1 2 3 Fixed high self refresh rate op mizes data reten on to support the extended temperature range. Variable or xed self refresh rate or any other DRAM power consump on reduc on control for the reduced temperature range. User is required to ensure 45°C DRAM TCASEMAX is not exceeded to avoid any risk of data loss. Auto self refresh mode enabled. Self refresh power consump on and data reten on are op mized for any given opera ng temperature condi on. NOTE 1 The Normal range depends on product’s grade. - Commercial Grade = 0°C ~85°C - Industrial Grade (-I) = -40°C ~85°C NOTE 2 The Extended range depends on product’s grade. - Commercial Grade = 85°C ~95°C - Industrial Grade (-I) = 85°C ~95°C NOTE 3 The Reduced range depends on product’s grade. - Commercial Grade = 0°C ~45°C - Industrial Grade (-I) = -40°C ~45°C Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 49 IS43/46QR16256A ® Long-term Support World Class Quality Self Refresh Exit with No Operation command Self Refresh Exit with No Opera on command (NOP) allows for a common command/address bus between ac ve DRAM and DRAM in Max Power Saving Mode. Self Refresh Mode may exit with No Opera on commands (NOP) provided: (1) The DRAM entered Self Refresh Mode with CA Parity and CAL disabled. (2) tMPX_S and tMPX_LH are sa s ed. (3) NOP commands are only issued during tMPX_LH window. No other command is allowed during tMPX_LH window a er SRX command is issued. NOTE 1 NOTE 2 NOTE 3 NOTE 4 NOTE 5 NOTE 6 CS = L, ACT = H, RAS/A16 = H, CAS/A15 = H, WE/A14 = H at Tb2 ( No Opera on command ) SRX at Tb2 is only allowed when DRAM shared Command/Address bus is under exi ng Max Power Saving Mode. Valid commands not requiring a locked DLL Valid commands requiring a locked DLL tXS_FAST and tXS_ABORT are not allowed this case. Dura on of CS Low around CKE rising edge must sa sfy tMPX_S and tMPX_LH as de ned by Max Power Saving Mode AC parameters. Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 50 ® Long-term Support World Class Quality IS43/46QR16256A Multipurpose Register (MPR) The mul purpose register (MPR) func on, MPR Access Mode, is used to write/read specialized data to/from the DRAM. The MPR consists of four logical Pages, MPR Page 0 through MPR Page 3, with each Page having four 8-bit registers, MPR0 through MPR3. MPR mode enable and Page selec on is done with MRS commands. Data Bus Inversion (DBI) is not allowed during MPR Read opera on. Prior to issuing the MRS command, all banks must be in the idle state (all banks precharged and tRP met). A er MPR is enabled, any subsequent RD or RDA commands will be redirected to a speci c mode register. Once the MPR Access Mode is enabled (MR3[2] = 1), only the following commands are allowed: MRS, RD, RDA WR, WRA, DES, REF and Reset; RDA/WRA have the same func onality as RD/WR which means the auto precharge part of RDA/WRA is ignored. The mode register loca on is speci ed with the READ command using address bits. The MR is split into upper and lower halves to align with a burst length limita on of 8. Power Down mode and Self-Refresh command are not allowed during MPR enable Mode. No other command can be issued within tRFC a er a REF command has been issued; 1x Refresh {only} is to be used during MPR Access Mode. While in MPR Access Mode, MPR read or write sequences must be completed prior to a refresh command. The reset func on is supported during MPR mode, which requires re-ini aliza on of the DDR4 SDRAM. Allow 1. 2. Not Allow MPR Read with BL8 or BC4 (A[2:0] = 000 or 100) MRS, RD, RDA WR, WRA, DESELECT, REFRESH and Reset 1. 2. 3. BL OTF Data Bus Inversion (DBI) Power Down mode and Self-Refresh MPR pages A er power-up, the content of MPR page 0 has the default values, de ned in the MPR Data Format table. MPR page 0 can be rewri en via an MPR WRITE command. The DRAM maintains the default values unless it is re-wri en by the DRAM controller. If DRAM’s controller does overwrite the default values (Page 0 only), the device will maintain the new values unless re-ini alized or power loss. MPR Page 2 Page 3 Readout of the contents of the MRn registers RFU ‡ RAS (reliability, accessibility and Can be ‡ DRAM controller receiver training. ‡ Mode Register Con rma on. used for ‡ DRAM controller DQS to DQ phase training. serviceability) Support: Logging of C/A N/A. DeĮniƟon Page 0 WRITE and READ system pa erns used for data bus calibra on Page 1 Readout of the error frame when the C/A parity is enabled ‡ Clock to address phase training. parity and CRC error informa on Readout format serial, parallel, or staggered Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 serial serial serial 51 ® Long-term Support World Class Quality IS43/46QR16256A MPR Block Diagram Bit Number of MPR Definition MPR Page 128 bits ＝ MPR LocaƟon × MPRx (MR3[1:0]) MPRy (MPR BA[1:0]) Address Bit × MPR burst bit (BL8) DRAM Address to MPR UI Translation MPR Loca on DRAM Address - Ax MPR UI - Uix [7] A7 UI0 [6] A6 UI1 [5] A5 UI2 [4] A4 UI3 [3] A3 UI4 [2] A2 UI5 [1] A1 UI6 [0] A0 UI7 MPR necessary settings MPR Read Format MPR OperaƟon MPR Page SelecƟon MPR LocaƟon MR3[12:11] MR3[2] MR3[1:0] MPR BA[1:0] MR3 MPR Read A12 A11 Format MR3 A2 MPR OperaƟon MR3 A1 MPR Page A0 SelecƟon MPR MPR BA1 BA0 LocaƟon 0 0 Serial 0 Normal Opera on 0 0 Page 0 0 0 MPR0 0 1 Parallel 1 Data ow from MPR 0 1 Page 1 0 1 MPR1 1 0 Staggered 1 0 Page 2 1 0 MPR2 1 1 RFU 1 1 Page 3 1 1 MPR3 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 52 ® Long-term Support World Class Quality IS43/46QR16256A MPR Page and MPRx Definitions MPR Page Purpose MR3[1:0] 00 Page 0 01 Page 1 Training Pa erns MPR LocaƟon BA[1:0] MPR Bit Write LocaƟon [7:0] 7 6 5 4 3 2 UI0 UI1 UI2 UI3 UI4 UI5 UI6 UI7 00 = MPR0 0 1 0 1 0 1 0 1 01 = MPR1 0 0 1 1 0 0 1 1 10 = MPR2 0 0 0 0 1 1 1 1 11 = MPR3 0 0 0 0 0 0 0 0 00 = MPR0 A7 A6 A5 A4 A3 A2 A1 A0 01 = MPR1 CAS/A15 WE/A14 A13 A12 A11 A10 A9 PAR ACT BG1 BG0 BA1 BA0 A17 RFU RFU C/A Parity 10 = MPR2 Error Log CA Parity Error 1 Status CA Parity Latency 00 = MPR0 RFU RFU MR5 MR5 MR5 [A2] [A1] [A0] CRC Write Enable RFU A10 A9 Vref DQ Tmg range Vref DQ training Value Geardown Enable MR6 MR6 MR3 A6 A5 10 = MPR2 A4 A3 A2 A1 11 = MPR3 A10 A5 A0 A3 CAS Write Latency RFU MR0 A6 RFU RFU MR2 A12 CAS Latency 11 Page 3 RAS/A16 RTT_WR MR2 Refer to next table 01 = MPR1 A8 2 4 Temperature 5 Sensor Status MRS Readout 0 Read Burst Order (serial mode) CRC Error 11 = MPR3 Status 10 Page 2 1 A4 MR2 A2 A5 A4 A3 RTT_NOM RTT_PARK Driver Impedance MR1 MR5 MR1 A9 A6 A8 A7 00 = MPR0 Don't care 01 = MPR1 Don't care 10 = MPR2 Don't care 11 = MPR3 Don't care A6 A2 A1 NOTE 1 MPR page 1 used for C/A parity error log readout is enabled by se ng A[2] in MR3. NOTE 2 For higher density of DRAM, where A[17] is not used, MPR page 1’s MPR2[1] should be treated as don’t care. NOTE 3 If a device is used in monolithic applica on, where C[2:0] are not used, then MPR page 1’s MPR3[2:0] should be treated as don’t care. NOTE 4 MPR page 1’s MPR3 bit 0-2 (CA parity latency) re ects the latest programmed CA parity latency values. NOTE 5 MPR page 2’s Temperature Sensor Readout MPR0 bit A4 MPR0 bit A3 Refresh Rate Range 0 0 Sub 1x refresh ( >tREFI) 0 1 1x refresh rate (= tREFI) 1 0 2x refresh rate (1/2 x tREFI) 1 1 RFU Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 MR3[5] MR3 bit A5=1 (Temperature sensor readout = Enabled) DRAM updates the temperature sensor status to MPR Page 2 (MPR0 bits A[4:3]). Temperature data is guaranteed by the DRAM to be no more than 32ms old at the me of MPR Read of the Temperature Sensor Status bits. MR3 bit A5=0 (Temperature sensor readout = Disabled) DRAM disables updates to the temperature sensor status in MPR Page 2(MPR0-bit A[4:3]) 53 IS43/46QR16256A ® Long-term Support World Class Quality MPR Reads The DRAM is required to drive associated strobes with the read data similar to normal opera on (such as using MRS preamble se ngs). Timing in MPR Mode should follow below rules: t Reads (back-to-back) from Page 0 may use tCCD_S ming between read commands. t Reads (back-to-back) from Pages 1, 2, or 3 may not use tCCD_S ming between read commands; tCCD_L must be used for ming between read commands. The following steps are required to use the MPR to read out the contents of a mode register (MPR Page x, MPRy). 1. The DLL must be locked if enabled. 2. Precharge all; wait un l tRP is sa s ed. 3. MRS command to MR3[2] = 1 (Enable MPR data ow), MR3[12:11] = MPR Read Format, and MR3[1:0] = MPR Page. a. MR3[12:11] MPR Read Format: 00 = Serial read format 01 = Parallel read format 10 = staggered read format 11 = RFU b. MR3[1:0] MPR Page: 00 = MPR Page 0 01 = MPR Page 1 10 = MPR Page 2 11 = MPR Page 3 4. tMRD and tMOD must be sa s ed. 5. Redirect all subsequent READ commands to speci c MPRx loca on. 6. Issue RD or RDA command: a. BA1 and BA0 indicate MPRx loca on: 00 = MPR0 01 = MPR1 10 = MPR2 11 = MPR3 b. A12/BC = 0 or 1; BL8 or BC4 Fixed only, BC4 OTF not supported. If BL=8 and MR0 A[1:0] = 01, A12/BC must be set to 1 during MPR Read commands. c. A[2] = burst type dependant: BL8: A[2] = 0 with burst order xed at 0, 1, 2, 3, 4, 5, 6, 7 BL8: A[2] = 1 with burst order xed at 4, 5, 6, 7, 0, 1, 2, 3 BC4: A[2] = 0 with burst order xed at 0, 1, 2, 3, T, T, T, T BC4: A[2] = 1 with burst order xed at 4, 5, 6, 7, T, T, T, T d. A[1:0] = 00, data burst is xed nibble start at 00. e. Remaining address inputs, including A10, and BG1 and BG0 are don’t care. 7. A er RL = AL + CL, DRAM bursts data from MPRx loca on; MPR readout format determined by MR3 [A12,11,1,0]. 8. Steps 5 through 7 may be repeated to read addi onal MPRx loca ons. 9. A er the last MPRx Read burst, tMPRR must be sa s ed prior to exi ng. 10. Issue MRS command to exit MPR mode; MR[3] = 0. 11. Once tMOD sequence is completed; the DRAM is ready for normal opera on from the core such as ACT. Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 54 ® Long-term Support World Class Quality IS43/46QR16256A MPR Readout Serial Format Serial format implies that the same pa ern is returned on all DQ lanes. MPR Readout Parallel Format Parallel format implies that the MPR data is returned in the rst data UI and then repeated in the remaining UIs of the burst as shown in the MPR Readout Parallel Format table. Data pa ern loca on 0 is the only loca on used for the parallel format. RD/RDA from data pa ern loca ons 1, 2, and 3 are not allowed with parallel data return mode. Example: The pa ern programmed in the data pa ern loca on 0 is 0111 1111. The x4 con gura on only outputs the rst four bits (0111 in this example). For the x16 con gura on, the same pa ern is repeated on both the upper and lower bytes. Serial X4 Device Serial UI0 UI1 DQ0 0 1 DQ1 0 1 DQ2 0 1 DQ3 0 1 X8 Device Serial UI0 UI1 DQ0 0 1 DQ1 0 1 DQ2 0 1 DQ3 0 1 DQ4 0 1 DQ5 0 1 DQ6 0 1 DQ7 0 1 X16 Device Serial UI0 UI1 DQ0 0 1 DQ1 0 1 DQ2 0 1 DQ3 0 1 DQ4 0 1 DQ5 0 1 DQ6 0 1 DQ7 0 1 DQ8 0 1 DQ9 0 1 DQ10 0 1 DQ11 0 1 DQ12 0 1 DQ13 0 1 DQ14 0 1 DQ15 0 1 Parallel UI2 UI3 UI4 UI5 UI6 UI7 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 UI2 UI3 UI4 UI5 UI6 UI7 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 UI2 UI3 UI4 UI5 UI6 UI7 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 X4 Device Parallel UI0 DQ0 0 DQ1 1 DQ2 1 DQ3 1 X8 Device Parallel UI0 DQ0 0 DQ1 1 DQ2 1 DQ3 1 DQ4 1 DQ5 1 DQ6 1 DQ7 1 UI1 UI2 UI3 UI4 UI5 UI6 UI7 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 UI1 UI2 UI3 UI4 UI5 UI6 UI7 0 1 1 1 1 1 1 1 X16 Device Parallel UI0 UI1 DQ0 0 0 DQ1 1 1 DQ2 1 1 DQ3 1 1 DQ4 1 1 DQ5 1 1 DQ6 1 1 DQ7 1 1 DQ8 0 0 DQ9 1 1 DQ10 1 1 DQ11 1 1 DQ12 1 1 DQ13 1 1 DQ14 1 1 DQ15 1 1 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 UI2 UI3 UI4 UI5 UI6 UI7 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 55 ® Long-term Support World Class Quality IS43/46QR16256A MPR Readout Staggered Format Staggered format of data return is de ned as the staggering of the MPR data across the lanes. In this mode, an RD/RDA command is issued to a speci c data pa ern loca on and then the data is returned on the DQ from each of the di erent data pa ern loca ons. For the x4 con gura on, an RD/RDA to data pa ern loca on 0 will result in data from loca on 0 being driven on DQ0, data from loca on 1 being driven on DQ1, data from loca on 2 being driven on DQ2, and so on. Similarly, an RD/RDA command to data pa ern loca on 1 will result in data from loca on 1 being driven on DQ0, data from loca on 2 being driven on DQ1, data from loca on 3 being driven on DQ2, and so on. It is expected that the DRAM can respond to back to back RD/RDA commands to the MPR for all DDR4 frequencies so that a stream as follows can be created on the data bus with no bubbles or clocks between read data. In this case system memory controller issues a sequence of RD(MPR0), RD(MPR1), RD(MPR2), RD(MPR3), RD(MPR0), RD(MPR1), RD(MPR2), and RD(MPR3). For the x8 con gura on, the same pa ern is repeated on the lower nibble as on the upper nibble. READs to other MPR data pa ern loca ons follow the same format as the x4 case. MPR Readout Staggered Format, x4 MPR0(BA[1:0]=''00') MPR0(BA[1:0]=''01') MPR0(BA[1:0]=''10') MPR0(BA[1:0]=''11') Stagger UI0-7 Stagger UI0-7 Stagger UI0-7 Stagger UI0-7 DQ0 MPR0 DQ0 MPR1 DQ0 MPR2 DQ0 MPR3 DQ1 MPR1 DQ1 MPR2 DQ1 MPR3 DQ1 MPR0 DQ2 MPR2 DQ2 MPR3 DQ2 MPR0 DQ2 MPR1 DQ3 MPR3 DQ3 MPR0 DQ3 MPR1 DQ3 MPR2 MPR Readout Staggered Format, x4 – Consecutive READs Stagger UI0-7 UI 8-15 UI 16-23 UI 24-31 UI 32-39 UI 40-47 UI 48-55 UI 56-63 DQ0 MPR0 MPR1 MPR2 MPR3 MPR0 MPR1 MPR2 MPR3 DQ1 MPR1 MPR2 MPR3 MPR0 MPR1 MPR2 MPR3 MPR0 DQ2 MPR2 MPR3 MPR0 MPR1 MPR2 MPR3 MPR0 MPR1 DQ3 MPR3 MPR0 MPR1 MPR2 MPR3 MPR0 MPR1 MPR2 MPR Readout Staggered Format, x8 and x16 X8 X16 Stagger UI0-7 Stagger UI0-7 Stagger UI0-7 DQ0 MPR0 DQ0 MPR0 DQ8 MPR0 DQ1 MPR1 DQ1 MPR1 DQ9 MPR1 DQ2 MPR2 DQ2 MPR2 DQ10 MPR2 DQ3 MPR3 DQ3 MPR3 DQ11 MPR3 DQ4 MPR0 DQ4 MPR0 DQ12 MPR0 DQ5 MPR1 DQ5 MPR1 DQ13 MPR1 DQ6 MPR2 DQ6 MPR2 DQ14 MPR2 DQ7 MPR3 DQ7 MPR3 DQ15 MPR3 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 56 IS43/46QR16256A ® Long-term Support World Class Quality MPR Read Waveforms MPR READ Timing NOTE 1 Mul purpose registers Read/Write Enable (MR3 A2 = 1). Redirect all subsequent reads and writes to MPR loca ons. NOTE 2 Address se ng: A[1:0] = “00”b (data burst order is xed star ng at nibble, always 00b here) A[2]= 0b (For BL = 8, burst order is xed at 0, 1, 2, 3, 4, 5, 6, 7) BA1 and BA0 indicate the MPR loca on A10 and other address pins are "Don’t Care" including BG1 and BG0. A12 is don’t care when MR0 A[1:0] = 00 or 10, and must be 1b when MR0 A[1:0] = 01 NOTE 3 Mul purpose registers Read/Write Disable (MR3 A2 = 0). NOTE 4 Con nue with regular DRAM command. NOTE 5 Parity latency (PL) is added to data output delay when C/A parity latency mode is enabled. BL = 8, AL = 0, CL = 11, CAL = 3, Preamble = 1tCK. MPR Back-to-Back READ Timing NOTE 1 Mul purpose registers Read/Write Enable (MR3 A2 = 1). Redirect all subsequent reads and writes to MPR loca ons. NOTE 2 Address se ng: A[1:0] = 00b (data burst order is xed star ng at nibble, always 00b here) A[2] = 0b (for BL = 8, burst order is xed at 0, 1, 2, 3, 4, 5, 6, 7; for BC = 4, burst order is xed at 0, 1, 2, 3, T, T, T, T) BA1 and BA0 indicate the MPR loca on A10 and other address pins are "Don’t Care" including BG1 and BG0. A12 is "Don’t Care" when MR0 A[1:0] = 00 or 10, and must be 1b when MR0 A[1:0] = 01 NOTE 3 Parity latency (PL) is added to data output delay when C/A parity latency mode is enabled. Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 57 IS43/46QR16256A ® Long-term Support World Class Quality MPR READ-to-WRITE Timing NOTE 1 Address se ng: A[1:0] = 00b (data burst order is xed star ng at nibble, always 00b here) A[2]= 0b (for BL = 8, burst order is xed at 0, 1, 2, 3, 4, 5, 6, 7) BA1 and BA0 indicate the MPR loca on A10 and other address pins are "Don’t Care" including BG1 and BG0. A12 is "Don’t Care" when MR0 A[1:0] = 00, and must be 1b when MR0 A[1:0] = 01 NOTE 2 Address se ng: BA1 and BA0 indicate the MPR loca on A [7:0] = data for MPR BA1 and BA0 indicate the MPR loca on A10 and other address pins are "Don’t Care" NOTE 3 Parity latency (PL) is added to data output delay when C/A parity latency mode is enabled. Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 58 IS43/46QR16256A ® Long-term Support World Class Quality MPR Writes MPR Access Mode allows 8-bit writes to the MPR loca on using the address bus A7:0. Data Bus Inversion (DBI) is not allowed during MPR Write opera on. The DRAM will maintain the new wri en values unless re-ini alized or power loss. The following steps are required to use the MPR to write to mode register MPR Page 0, MPRy). 1. The DLL must be locked if enabled. 2. Precharge all; wait un l tRP is sa s ed. 3. MRS command to MR3[2] = 1 (Enable MPR data ow) and MR3[1:0] = 00 (MPR Page 0); 01, 10, 11 = Not allowed. 4. tMRD and tMOD must be sa s ed. 5. Redirect all subsequent Write commands to speci c MPRx loca on. 6. Issue WR or WRA command: a. BA1 and BA0 indicate MPRx loca on: 00 = MPR0 01 = MPR1 10 = MPR2 11 = MPR3 b. A[7:0] = data for MPR Page 0, mapped A[7:0] to UI[0:7] . c. Remaining address inputs, including A10, BG0 and BG1 are don’t care. 7. tWR_MPR must be sa s ed to complete MPR Write. 8. Steps 5 through 7 may be repeated to write addi onal MPRx loca ons. 9. A er the last MPRx Write, tMPRR must be sa s ed prior to exi ng. 10. Issue MRS command to exit MPR mode; MR[3] = 0. 11. Once tMOD sequence is completed; the DRAM is ready for normal opera on from the core such as ACT. Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 59 IS43/46QR16256A ® Long-term Support World Class Quality MPR Write Waveforms MPR WRITE and WRITE-to-READ Timing NOTE 1 Mul purpose registers Read/Write Enable (MR3 A2 = 1). NOTE 2 Address se ng: BA1 and BA0 indicate the MPR loca on A10 and other address pins are "Don’t Care" NOTE 3 Parity latency (PL) is added to data output delay when C/A parity latency mode is enabled. MPR Back-to-Back WRITE Timing NOTE 1 Address se ng: BA1 and BA0 indicate the MPR loca on A [7:0] = data for MPR A10 and other address pins are "Don’t Care" Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 60 IS43/46QR16256A ® Long-term Support World Class Quality MPR Refresh Waveforms REFRESH Timing NOTE 1 Mul purpose registers Read/Write Enable (MR3 A2 = 1). Redirect all subsequent read and writes to MPR loca ons. NOTE 2 1x refresh is only allowed when MPR mode is enabled. READ-to-REFRESH Timing NOTE 1 Address se ng: A[1:0] = 00b (data burst order is xed star ng at nibble, always 00b here) A[2]= 0b (for BL = 8, burst order is xed at 0, 1, 2, 3, 4, 5, 6, 7) BA1 and BA0 indicate the MPR loca on A10 and other address pins are "Don’t Care" including BG1 and BG0. A12 is "Don’t Care" when MR0 A[1:0] = 00 or 10, and must be 1b when MR0 A[1:0] = 01 NOTE 2 1x refresh is only allowed when MPR mode is enabled. Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 61 IS43/46QR16256A ® Long-term Support World Class Quality WRITE-to-REFRESH Timing NOTE 1 Address se ng: BA1 and BA0 indicate the MPR loca on A [7:0] = data for MPR A10 and other address pins are "Don’t Care" NOTE 2 1x refresh is only allowed when MPR mode is enabled. Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 62 ® Long-term Support World Class Quality IS43/46QR16256A Gear-down Mode The DDR4 SDRAM defaults in 1/2 rate (1N) clock mode and u lizes a low frequency MRS command followed by a sync pulse to align the proper clock edge for opera ng the control lines CS, CKE, and ODT when in 1/4 rate (2N) mode. For opera on in 1/2 rate mode, no MRS command or sync pulse is required. External Clock Internal Clock Set 2N mode CMD/ADDR/CTRL MRS NOP Valid The general sequence for opera on in 1/4 rate during ini aliza on is as follows: 1. DDR4 SDRAM defaults to a 1/2 rate (1N mode) internal clock at power-up/reset. 2. Asser on of reset. 3. Asser on of CKE enables the rank. 4. CAL and CA parity mode must be disabled prior to Gear-down MRS command. They can be enabled again a er tSYNC_GEAR and tCMD_GEAR periods are sa s ed. 5. MRS is accessed with a low frequency NxtCK MRS Gear-down CMD. (NtCK sta c MRS command is quali ed by 1N CS.) 6. The memory controller shall send a 1N sync pulse with a low frequency N*tCK NOP CMD;. Clock tSYNC_GEAR is an even number of clocks; sync pulse on even edge from MRS CMD. 7. Normal opera on in 2N mode starts tCMD_GEAR clocks later. When opera ng in 1/4 rate Gear-down Mode, the following MR se ngs apply: t CAS Latency (MR0 [6:4,2]): Even numbers t Write Recovery and Read to Precharge (MR0 [11:9]) : Even numbers t CAS Write Latency (MR2 A[5:3]) : Even numbers t CS to Command/Address Latency Mode (MR4 [8:6]) : Even numbers t CA Parity Latency Mode (MR5 [2:0]) : Even numbers t Addi ve Latency (MR1 [4:3]): CL–2 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 63 IS43/46QR16256A ® Long-term Support World Class Quality Gear down (2N) mode entry sequence during initialization NOTE 1 The diagram below represents the opera on of geardown(1/2 rate to 1/4 rate)mode during normal opera on with CKE and Reset set high. Clock Mode Change from 1/2 Rate to 1/4 Rate (Normal Operation) If the opera on is in 1/2 rate (1N) mode before and a er self refresh, no MRS command or sync pulse is required a er self refresh exit. However, if the clock mode is set to 1/4 rate (2N) before and a er self refresh mode, the DDR4 SDRAM requires an MRS command and sync pulse as shown in the gure below. Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 64 IS43/46QR16256A ® Long-term Support World Class Quality Clock Mode Change After Exiting Self Refresh NOTE 1 CKE High Assert to Gear Down Enable Time (tXS, tXS_Abort) depend on MR se ng. A correspondence of tXS/tXS_Abort and MR Se ng is as follows. - MR4[A9] = 0 : tXS - MR4[A9] = 1 : tXS_Abort Comparison Between Gear-down Disable and Gear-down Enable NOTE 1 NOTE 2 NOTE 3 NOTE 4 BL=8, tRCD=CL=16 DOUT n = data-out from column n. DES commands are shown for ease of illustra on; other commands may be valid at these mes. CA Parity = Disable, CS to CA Latency = Disable, Read DBI= Disable. Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 65 IS43/46QR16256A ® Long-term Support World Class Quality Maximum Power-Saving Mode (MPSM) This mode provides the lowest power mode where data reten on is not required. When DDR4 SDRAM is in the maximum power-saving mode, it does not maintain data reten on or respond to any external command, except the MAXIMUM POWER SAVING MODE EXIT command and during the asser on of RESETsignal LOW. This mode is more like a “hibernate mode” than a typical power savings mode. The intent is to be able to park the DRAM at very low powered state so the device can be switched to an ac ve state via PDA mode. Maximum Power-Saving Mode Entry Max power saving mode is entered through an MRS command. For devices with shared control/address signals, a single DRAM device can be entered into the max power saving mode using the per DRAM Addressability MRS command. Large CS hold me to CKE upon the mode exit could cause DRAM malfunc on; thus, it is required CA parity, CAL and Gear-down modes are disabled prior to the max power saving mode entry MRS command. The MRS command may use both address and DQ informa on as de ned in Per DRAM Addressability sec on. A er tMPED from the MRS mode entry command, the DRAM is not responsive to any input signals except CKE, CS, and RESET. All other inputs are disabled (external input signals may become hi-Z). The system will provide a valid clock un l tCKMPE expires at which me clock inputs (CK, CK) should be disabled (external clock signals may become hi-Z). Maximum Power Saving Mode Entry Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 66 IS43/46QR16256A ® Long-term Support World Class Quality Maximum Power-Saving Mode Entry in PDA The sequence and ming required for the maximum power saving mode with the per DRAM addressability (PDA) enabled is illustrated in Figure below. CKE Transition during Maximum Power-Saving Mode The following gure shows how to maintain maximum power-saving mode even though the CKE input may toggle. To prevent the device from exi ng the mode, CS should be HIGH at the CKE LOW-to-HIGH edge, with appropriate setup (tMPX_S) and hold (tMPX_H) mings. CKE Transition Limitation to hold Maximum Power Saving Mode Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 67 IS43/46QR16256A ® Long-term Support World Class Quality Maximum Power-Saving Mode Exit To exit the maximum power-saving mode, CS should be LOW at the CKE LOW-to-HIGH transi on, with appropriate setup (tMPX_S) and hold (tMPX_LH) mings as shown in the gure below. Because the clock receivers (CK, CK) are disabled during this mode, CS = LOW is captured by the rising edge of the CKE signal. If the CS signal level is detected LOW, the DRAM clears the maximum power saving mode MRS bit and begins the exit procedure from this mode. The external clock must be restarted and stable by tCKMPX ming before the device can exit the maximum power saving mode. During the exit me (tXMP) only NOP and DES commands are allowed, NOP during tMPX_LH, and DES the remainder of tXMP. Once tXMP expires, valid commands not requiring a locked DLL are allowed and a er tXMP_DLL expires valid commands requiring a locked DLL are allowed. Maximum Power-Saving Mode Exit Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 68 IS43/46QR16256A ® Long-term Support World Class Quality Command/Address Parity (CAP) This feature is not supported in this product. Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 69 ® Long-term Support World Class Quality IS43/46QR16256A Per-DRAM Addressability (PDA Mode) DDR4 allows programmability of a single, speci c DRAM on a rank. As an example, this feature can be used to program di erent ODT or VREF values on each DRAM on a given rank. Since PDA mode may be used to program op mal Vref for the DRAM, the data set up for rst DQ0 transfer or the hold me for the last DQ0 transfer cannot be guaranteed. The DRAM may sample DQ0 on either the rst falling or second rising DQS transfer edge. This supports a common implementa on between BC4 and BL8 modes on the DRAM. The DRAM controller is required to drive DQ0 to a ‘Stable Low or High’ during the length of the data transfer for BC4 and BL8 cases. 1. Before entering Per-DRAM addressability mode, write leveling is required. BL8 or BC4 may be used. 2. Before entering per-DRAM addressability mode, the following MR se ngs are possible: RTT_PARK MR5 A[8:6] = Enabled RTT_NOM MR1 A[9, 6, 2] = Enabled 3. Enable per-DRAM addressability mode using MR3 [4] = 1. (The default programmed value of MR3[4] = 0 .) 4. In the per-DRAM addressability mode, all MRS commands are quali ed with DQ0. The device captures DQ0 by using DQS and DQS signals. If the value on DQ0 is low, the DRAM executes the MRS command. If the value on DQ0 is high, the DRAM ignores the MRS command. The controller can choose to drive all the DQ bits. 5. Program the desired DRAM and mode registers using the MRS command and DQ0. 6. In per-DRAM addressability mode, only MRS commands are allowed. 7. The MODE REGISTER SET command cycle me in per-DRAM addressability mode, AL + CWL + 3.5nCK + tMRD_PDA is required to complete the WRITE opera on to the mode register and is the minimum me required between two MRS commands. 8. Remove the device from per-DRAM addressability mode by se ng MR3[4] = 0. (This command requires DQ0 = 0.) NOTE: Removing the device from per-DRAM addressability mode will require programming the en re MR3 when the MRS command is issued. This may impact some per-DRAM addressability values programmed within a rank as the EXIT command is sent to the rank. In order to avoid such a case, the PDA Enable/Disable Control bit is located in a mode register that does not have any Per-DRAM addressability mode controls. In per-DRAM addressability mode, the device captures DQ0 using DQS and DQS like normal WRITE opera on; however, dynamic ODT is not supported. Extra care is required for the ODT se ng. If RTT_NOM MR1 [10:8] = Enable, DDR4 SDRAM data termina on needs to be controlled by the ODT pin and applies the same ming parameters as de ned in direct ODT func on that is shown below. Symbol Parameter DODTLon Direct ODT turn on latency DODTLoī Direct ODT turn o latency tADC RTT change ming skew tAONAS Asynchronous RTT_NOM turn-on delay tAOFAS Asynchronous RTT_NOM turn-o delay Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 70 IS43/46QR16256A ® Long-term Support World Class Quality PDA Operation Enabled, BL8 (seeted device) NOTE 1 RTT_PARK = Enable, RTT_NOM = Enable, Write Preamble Set = 2tCK and DLL = ON, CA parity is used MRS w/ per DRAM addressability (PDA) Exit (selected device) NOTE 1 RTT_PARK = Enable; RTT_NOM = Enable, Write Preamble Set = 2tCK and DLL = ON. Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 71 IS43/46QR16256A ® Long-term Support World Class Quality PDA using Burst Chop 4 (selected device) Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 72 ® Long-term Support World Class Quality IS43/46QR16256A VREFDQ Training The data bus is terminated to VDDQ so that the Vref level will change based on drive strength and loading. Therefore VrefDQ is not any more supplied externally, but VrefDQ is generated internally in the DRAM. The DRAM VREFDQ does not have a default value upon power-up and must be set to the desired value, usually via VREFDQ training. The DDR4 DRAM memory controller is responsible for VREFDQ calibra on to determine the best internal VREFDQ level. The VREFDQ calibra on is enabled/disabled via MR6 [7], MR6 [6] selects Range 1 (60% to 92.5% of VDDQ) or Range 2 (45% to 77.5% of VDDQ), and an MRS protocol using MR6 [5:0] to adjust up and adjust down the VREFDQ level. MR6 [6:0] bits can be altered via MR command set if MR6 [7] is disabled. The DRAM controller will likely use a series of Writes and Reads in conduc on with VREFDQ adjustments to obtain the best VREFDQ which in turn op mizes the data eye. DDR4 SDRAM internal VREFDQ speci ca on parameters: voltage range, step-size, VREF step me, VREF full step me, and VREF valid level. The voltage opera ng range speci es the minimum required VREF se ng range for DDR4 DRAM devices. The minimum range is de ned by VREFDQ,min and VREFDQ,max. As noted, a calibra on sequence, determined by the DRAM controller, should be performed to adjust VREFDQ and op mize the ming and voltage margin of the DRAM data input receivers. VREFDQ Voltage Range VDDQ Vrefmax Vref Range Vrefmin Vswing Small System Variance Vswing Large Total Range Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 73 ® Long-term Support World Class Quality IS43/46QR16256A VREFDQ Range and Levels A[5:0] Range 1 (A6=0) Range 2 (A6=1) A[5:0] Range 1 (A6=0) Range 2 (A6=1) A[5:0] Range 1 (A6=0) Range 2 (A6=1) A[5:0] Range 1 (A6=0) Range 2 (A6=1) 00 0000 60.00% 45.00% 00 1101 68.45% 53.45% 01 1010 76.90% 61.90% 10 0111 85.35% 70.35% 00 0001 60.65% 45.65% 00 1110 69.10% 54.10% 01 1011 77.55% 62.55% 10 1000 86.00% 71.00% 00 0010 61.30% 46.30% 00 1111 69.75% 54.75% 01 1100 78.20% 63.20% 10 1001 86.65% 71.65% 00 0011 61.95% 46.95% 01 0000 70.40% 55.40% 01 1101 78.85% 63.85% 10 1010 87.30% 72.30% 00 0100 62.60% 47.60% 01 0001 71.05% 56.05% 01 1110 79.50% 64.50% 10 1011 87.95% 72.95% 00 0101 63.25% 48.25% 01 0010 71.70% 56.70% 01 1111 80.15% 65.15% 10 1100 88.60% 73.60% 00 0110 63.90% 48.90% 01 0011 72.35% 57.35% 10 0000 80.80% 65.80% 10 1101 89.25% 74.25% 00 0111 64.55% 49.55% 01 0100 73.00% 58.00% 10 0001 81.45% 66.45% 10 1110 89.90% 74.90% 00 1000 65.20% 50.20% 01 0101 73.65% 58.65% 10 0010 82.10% 67.10% 10 1111 90.55% 75.55% 00 1001 65.85% 50.85% 01 0110 74.30% 59.30% 10 0011 82.75% 67.75% 11 0000 91.20% 76.20% 00 1010 66.50% 51.50% 01 0111 74.95% 59.95% 10 0100 83.40% 68.40% 11 0001 91.85% 76.85% 00 1011 67.15% 52.15% 01 1000 75.60% 60.60% 10 0101 84.05% 69.05% 11 0010 92.50% 77.50% 00 1100 67.80% 52.80% 01 1001 76.25% 61.25% 10 0110 84.70% 69.70% 11 0011 to 111111 Reserved Reserved VREFDQ Step Size The VREF step size is de ned as the step size between adjacent steps. VREF step size ranges from 0.5% VDDQ to 0.8% VDDQ. However, for a given design, DRAM has one value for VREF step size that falls within the range. The VREF set tolerance is the varia on in the VREF voltage from the ideal se ng. This accounts for accumulated error over mul ple steps. There are two ranges for VREF set tolerance uncertainty. The range of VREF set tolerance uncertainty is a func on of number of steps n. The VREF set tolerance is measured with respect to the ideal line which is based on the two endpoints where the endpoints are at the MIN and MAX VREF values for a speci ed range. Example of VREF Set Tolerance and Step Size Vref Actual Vref Output Straight Line (endpoint Fit) Vref Set Tolerance Vref Stepsize Digital Code Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 74 ® Long-term Support World Class Quality IS43/46QR16256A VREFDQ Increment and Decrement Timing The VREF increment/decrement step mes are de ne by V REF_ me-short and VREF_ me-long. VREF_ me-short and VREF_ me-long are de ned from t0 to t1, where t1 is referenced to the VREF voltage at the nal DC level within the V REF valid tolerance (VREF_val_tol). The VREF valid level is de ned by VREF_val tolerance to qualify the step me t1. This parameter is used to insure an adequate RC me constant behavior of the voltage level change a er any V REF increment/decrement adjustment. VREF_ me-short is for a single stepsize increment/decrement change in V REF voltage. VREF_ me-long is the me including up to VREF,min to VREF,max or VREF,max to VREF,min change in VREF voltage. Note: t0 - is referenced to the MRS command clock t1 - is referenced to VREF_tol Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 75 ® Long-term Support World Class Quality IS43/46QR16256A VREFDQ Short and Long Timing Diagram for VREF_time Parameter An MRS command to the mode register MR6[5:0] is used to program the VREF value. The minimum me required between two VREF MRS commands is VREF_ me-short for single step and VREF_ me-long for a full voltage range step. VREFDQ training mode is enabled or disabled by MR6[7] and training range is selected by MR6[6]. When VREFDQ training mode is entered or exited, the parameters tVREFDQE and tVREFDQX need to be sa s ed inorder to prevent excessive current consump on as well as provide stable opera on. Vref_time for short and long timing diagram t0 t1 CK CK CMD MRS Vref Setting Adjustment DQ Old Vref Setting Vref Updating Vref Setting New Vref Setting Vref_time-Short/Long VREFDQ Training Mode Entry and Exit Timing Diagram NOTE 1 New VREFDQ value is not allowed with MRS command during training mode exit. NOTE 2 Depending on the step size of the latest programmed VREF value, Vref_ me_short or Vref_ me_long must be sa s ed before disabling VrefDQ training mode. Speed Parameter DDR4-2133,2400,2666,3200 Symbol Min Max Units NOTE VrefDQ training Enter VrefDQ training mode to the rst valid command delay tVREFDQE 150 – ns Exit VrefDQ training mode to the rst valid command delay tVREFDQX 150 – ns Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 76 ® Long-term Support World Class Quality IS43/46QR16256A VREF Step Single Step Size Increment Case Vref Voltage Vref (VDDQ DC) Stepsize Vref_val_tol t1 Time VREF Step Single Step Size Decrement Case Vref Voltage t1 Stepsize Vref_val_tol Vref (VDDQ DC) Time Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 77 ® Long-term Support World Class Quality IS43/46QR16256A VREF Full Step From VREF,min to VREF,maxCase Vref Voltage Vref (VDDQ DC) Vrefmax Vref_val_tol Full Range Step t1 Vrefmin Time VREF Full Step From VREF,max to VREF,minCase Vref Voltage Vrefmax Full Rang Step t1 Vref_val_tol Vref (VDDQ DC) Vrefmin Time Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 78 ® Long-term Support World Class Quality IS43/46QR16256A VREFDQ Supply and Calibration Ranges The DDR4 SDRAM internally generates its own VREFDQ. DRAM internal VREFDQ speci ca on parameters: voltage range, step-size, VREF step me, VREF full step me, and V REF valid level. The voltage opera ng range speci es the minimum required VREF se ng range for DDR4 DRAM devices. The minimum range is de ned by V REFDQ,min and VREFDQ,max. A calibra on sequence should be performed by the DRAM controller to adjust V REFDQ and op mize the ming and voltage margin of the DRAM data input receivers. VREFDQ Specification Symbol Prarmeter Min Typ Max Unit NOTE VrefDQ R1 Range 1 VrefDQ opera ng points 60% – 92% VDDQ 1, 11 VrefDQ R2 Range 2 VrefDQ opera ng points 45% – 77% VDDQ 1, 11 Vref step Vref Stepsize Vref_set_tol Vref_Ɵme-Short Vref_Ɵme-Long Vref_val_tol Vref Set Tolerance 0.50% 0.65% 0.80% VDDQ 2 -1.625% 0.00% 1.625% VDDQ 3, 4, 6 -0.15% 0.00% 0.15% VDDQ 3, 5, 7 – – 60 ns 8, 12 – – 150 ns 9,12 -0.15% 0.00% 0.15% VDDQ 10 Vref Step Time Vref Valid tolerance NOTE 1 VREF(DC) voltage is referenced to VDDQ(DC). VDDQ(DC) is 1.2V. NOTE 2 VREF step size increment/decrement range. VREF at DC level. NOTE 3 VREF_new = VREF_old ± n × VREF_step; n = number of steps. If increment, use “+;” if decrement,use “-.” NOTE 4 For n >4, the minimum value of VREF se ng tolerance = VREF_new - 1.625% × VDDQ. The maximum value of VREF se ng tolerance = VREF_new + 1.625% × VDDQ. NOTE 5 For n 4, the minimum value of VREF se ng tolerance = VREF_new - 0.15% × VDDQ. The maximum value of VREF se ng tolerance = VREF_new + 0.15% × VDDQ. NOTE 6 Measured by recording the MIN and MAX values of the VREF output over the range,drawing a straight line between those points, and comparing all other VREF output se ngs to that line. NOTE 7 Measured by recording the MIN and MAX values of the VREF output across four consecu ve steps (n = 4), drawing a straight line between those points, and comparing al VREF output se ngs to that line. NOTE 8 Time from MRS command to increment or decrement one step size for VREF. NOTE 9 Time from MRS command to increment or decrement more than one step size up to the full range of VREF. NOTE 10 Only applicable for DRAM component-level test/characteriza on purposes. Not applicable for normal mode of opera on. VREF valid quali es the step mes, which will be characterized at the component level. NOTE 11 DRAM range 1 or range 2 is set by the MRS6[6]6. NOTE 12 If the Vref monitor is enabled, Vref_ me-long and Vref_ me-short must be derated by: +10ns if DQ bus load is 0pF and an addi onal +15ns/pF of DQ bus loading. Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 79 ® Long-term Support World Class Quality IS43/46QR16256A VREFDQ Ranges MR6 [6] selects Range 1 (60% to 92.5% of VDDQ) or Range 2 (45% to 77.5% of VDDQ), and MR6 [5:0] sets the VREFDQ level, as listed in the table below. The values in MR6 [6:0] will update the V DDQ Range and level independent of MR6 [7] se ng. It is recommended MR6 [7] be enabled when changing the se ngs in MR6 [6:0] and it is highly recommended MR6 [7] be enabled when changing the se ngs in MR6 [6:0] mul ple mes during a calibra on rou ne. VREFDQ Range and Levels MR6 [5:0] 00 0000 Range 1 Range 2 (MR6[6]=0) (MR6[6]=1) 60.00% 45.00% MR6 [5:0] 00 1101 Range 1 Range 2 (MR6[6]=0) (MR6[6]=1) 68.45% 53.45% MR6 [5:0] 01 1010 Range 1 Range 2 (MR6[6]=0) (MR6[6]=1) 76.90% 61.90% MR6 [5:0] 10 0111 Range 1 Range 2 (MR6[6]=0) (MR6[6]=1) 85.35% 70.35% 00 0001 60.65% 45.65% 00 1110 69.10% 54.10% 01 1011 77.55% 62.55% 10 1000 86.00% 71.00% 00 0010 61.30% 46.30% 00 1111 69.75% 54.75% 01 1100 78.20% 63.20% 10 1001 86.65% 71.65% 00 0011 61.95% 46.95% 01 0000 70.40% 55.40% 01 1101 78.85% 63.85% 10 1010 87.30% 72.30% 00 0100 62.60% 47.60% 01 0001 71.05% 56.05% 01 1110 79.50% 64.50% 10 1011 87.95% 72.95% 00 0101 63.25% 48.25% 01 0010 71.70% 56.70% 01 1111 80.15% 65.15% 10 1100 88.60% 73.60% 00 0110 63.90% 48.90% 01 0011 72.35% 57.35% 10 0000 80.80% 65.80% 10 1101 89.25% 74.25% 00 0111 64.55% 49.55% 01 0100 73.00% 58.00% 10 0001 81.45% 66.45% 10 1110 89.90% 74.90% 00 1000 65.20% 50.20% 01 0101 73.65% 58.65% 10 0010 82.10% 67.10% 10 1111 90.55% 75.55% 00 1001 65.85% 50.85% 01 0110 74.30% 59.30% 10 0011 82.75% 67.75% 11 0000 91.20% 76.20% 00 1010 66.50% 51.50% 01 0111 74.95% 59.95% 10 0100 83.40% 68.40% 11 0001 91.85% 76.85% 00 1011 67.15% 52.15% 01 1000 75.60% 60.60% 10 0101 84.05% 69.05% 11 0010 92.50% 77.50% 00 1100 67.80% 52.80% 01 1001 76.25% 61.25% 10 0110 84.70% 69.70% 11 0011 to 111111 Reserved Reserved Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 80 ® Long-term Support World Class Quality IS43/46QR16256A Connectivity Test Mode (CT) Connec vity Test (CT) mode is similar to boundary scan tes ng but is designed to signi cantly speed up tes ng of electrical con nuity of pin interconnec ons on the PC boards between the DDR4 and the memory controller. Designed to work seamlessly with any boundary scan device, CT mode is supported in x16 DDR4 SDRAMs. When TEN pin asserted HIGH, this causes the device to enter the CT mode. In CT mode, the normal memory func on inside the device is bypassed and the I/O pins appear as a set of test input and output pins to the external controlling agent. The TEN pin is dedicated to the connec vity check func on and will not be used during normal device opera on. Contrary to other conven onal shi register-based test modes, where test pa erns are shi ed in and out of the memory devices serially during each clock, the DDR4 CT mode allows test pa erns to be entered on the test input pins in parallel and the test results to be extracted from the test output pins of the device in parallel at the same me, signi cantly increasing the speed of the connec vity check. When placed in CT mode, the device appears as an asynchronous device to the external controlling agent. A er the input test pa ern is applied, the connec vity test results are available for extrac on in parallel at the test output pins a er a xed propaga on delay me. Note: A reset of the device is required a er exi ng CT mode (see RESET and Ini aliza on Procedure). Boundary Scan Mode Pin Map and Switching Levels Only digital pins can be tested via the CT mode. For the purposes of a connec vity check, all the pins used for digital logic in the DDR4 memory device are classi ed as one of the following 5 types: Types CT Mode Pins 1 Test Enable TEN 2 Chip Select CS 3 Test Input 8 4 5 Test Output Pin Names during Normal Memory OperaƟon 1,5 Switching Level CMOS (20% / 80% VDD) 7 VREFCA ± 200mV A BA[1:0], BG[1:0], A[9:0], A10/AP, A11, A12/BC, A13, WE/A14, CAS/A15, RAS/A16, CKE, ACT, ODT, CK, CK, PAR B LDM/LDBI, UDM/UDBI, DM/DBI C ALERT 1,6 CMOS (20% / 80% VDD) D RESET 1,10 CMOS (20% / 80% VDD) 9 DQ[15:0], DQSU, DQSU, DQSL, DQSL, DQS, DQS VREFCA ± 200mV VREFDQ ± 200mV VTT ± 100mV NOTE 1 NOTE 2 NOTE 3 NOTE 4 NOTE 5 NOTE 6 NOTE 7 CMOS is rail-to-rail signal with DC high at 80% and DC low at 20% of VDD, i.e, 960mV for DC high and 240mV for DC low. VREFCA should be at VDD/2. VREFDQ should be at VDDQ/2. VTT should be set to VDD/2. Connec vity Test Mode is ac ve when TEN is HIGH and inac ve when TEN is LOW. TEN must be LOW during normal opera on. ALERTswitching level is not a nal se ng. When asserted LOW, this pin enables the test output pins in the DDR4 memory device. When de-asserted, the output pins in the DDR4 memory device will be High-Z. The CS pin in the device serves as the CS pin in CT mode. NOTE 8 A group of pins used during normal DDR4 DRAM opera on designated as test input pins. These pins are used to enter the test pa ern in CT mode. NOTE 9 A group of pins used during normal DDR4 DRAM opera on designated as test output pins. These pins are used for extrac on of the connec vity test results in CT mode. NOTE 10 Fixed high level is required during CT mode, same as normal func on. Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 81 IS43/46QR16256A ® Long-term Support World Class Quality Min Terms Definition for Logic Equations Min Term Equations MTx is an inernal signal to be used to generate the signal to drive the output signals.. MT0 = XOR (A1, A6, PAR) MT1 = XOR (A8, ALERT, A9) MT2 = XOR (A2, A5, A13) MT3 = XOR (A0 A7, A11) MT4 = XOR (CK, ODT, CAS/A15) MT5 = XOR (CKE, RAS/A16, A10/AP) MT6 = XOR (ACT, A4, BA1) MT7 = XOR ((UDM / UDBI), (LDM/ LDBI), CK) MT8 = XOR (WE / A14, A12 / BC, BA0) MT9 = XOR (BG0, A3, (RESETand TEN)) Output equations for x16 devices DQ0 = MT0 DQ1 = MT1 DQ2 = MT2 DQ3 = MT3 DQ4 = MT4 DQ5 = MT5 DQ6 = MT6 DQ7 = MT7 DQ8 = !DQ0 DQ9 = !DQ1 DQ10 = !DQ2 DQ11 = !DQ3 DQ12 = !DQ4 DQ13 = !DQ5 DQ14 = !DQ6 DQ15 = !DQ7 DQSL = MT8 DQSL = MT9 DQSU = !DQSL DQSU = !DQSL Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 82 ® Long-term Support World Class Quality IS43/46QR16256A CT Input Timing Requirements During CT Mode, input levels are de ned below. 1. TEN pin : CMOS rail-to-rail with DC high and low at 80% and 20% of VDD. 2. CS : Pseudo differential signal referring to VrefCA 3. Test Input pin A : Pseudo differential signal referring to VrefCA 4. Test Input pin B : Pseudo differential signal referring to internal Vref 0.5*VDD 5. RESET: CMOS DC high above 70 % VDD 6. ALERT: Terminated to VDD. Swing level is TBD. Prior to the asser on of the TEN pin, all voltage supplies must be valid and stable. Upon the asser on of the TEN pin, the CK and CK signals will be ignored and the DDR4 memory device enter into the CT mode a er tCT_Enable. In the CT mode, no refresh ac vi es in the memory arrays, ini ated either externally (i.e., auto-refresh) or internally (i.e., self-refresh), will be maintained. The TEN pin may be asserted a er the DRAM has completed power-on; once the DRAM is ini alized and VREFdq is calibrated, CT Mode may no longer be used. The TEN pin may be de-asserted at any me in the CT mode. Upon exi ng the CT mode, the states of the DDR4 memory device are unknown and the integrity of the original content of the memory array is not guaranteed and therefore the reset ini aliza on sequence is required. All output signals at the test output pins will be stable within tCT_valid a er the test inputs have been applied to the test input pins with TEN input and CS input maintained High and Low respec vely. Connectivity Test Mode Entry Symbol Min tCT_Enable 200 - ns tCT_Valid - 200 ns Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 Max Unit 83 IS43/46QR16256A ® Long-term Support World Class Quality ACTIVATE Command The ACTIVATE command is used to open (ac vate) a row in a par cular bank for subsequent access. The values on the BG[1:0] inputs select the bank group; the BA[1:0] inputs select the bank within the bank group; and the address provided on inputs A[17:0] selects the row within the bank. This row remains ac ve (open) for accesses un l a PRECHARGE command is issued to that bank. A PRECHARGE command must be issued before opening a di erent row in the same bank. Bank-to-bank command ming for ACTIVATE commands uses two di erent ming parameters, depending on whether the banks are in the same or di erent bank group. tRRD_S (short) is used for ming between banks located in di erent bank groups. tRRD_L (long) is used for ming between banks located in the same bank group. Another ming restric on for consecu ve ACTIVATE commands (issued at tRRD (MIN) is tFAW ( h ac vate window). Since there is a maximum of four banks in a bank group, the tFAW parameter applies across di erent bank groups because ve ac vate commands issued at tRRD_L (MIN) to the same bank group would be limited by tRC. tRRD Timing NOTE 1 tRRD_S; ACTIVATE-to-ACTIVATE command period (short); applies to consecu ve ACTIVATE commands to di erent bank groups (i.e., T0 and T4) . NOTE 2 tRRD_L; ACTIVATE-to-ACTIVATE command period (long); applies to consecu ve ACTIVATE commands to the di erent banks in the same bank group (i.e., T4 and T10). Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 84 IS43/46QR16256A ® Long-term Support World Class Quality tFAW Timing NOTE 1 tFAW; four ac vate window. Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 85 IS43/46QR16256A ® Long-term Support World Class Quality PRECHARGE Command The PRECHARGE command is used to deac vate the open row in a par cular bank or the open row in all banks. The bank(s) will be available for a subsequent row ac va on for a speci ed me (tRP) a er the PRECHARGE command is issued. An excep on to this is the case of concurrent auto precharge, where a READ or WRITE command to a di erent bank is allowed as long as it does not interrupt the data transfer in the current bank and does not violate any other ming parameters. Once a bank has been precharged, it is in the idle state and must be ac vated prior to any READ or WRITE commands being issued to that bank. A PRECHARGE command is allowed if there is no open row in that bank (idle state) or if the previously open row is already in the process of precharging. However, the precharge period will be determined by the last PRECHARGE command issued to the bank. The auto-precharge func on is engaged when a Read or Write command is issued with A10 High. The auto-precharge func on u lizes the RAS lockout circuit to internally delay the precharge opera on un l the array restore opera on has completed. The RAS lockout circuit feature allows the precharge opera on to be par ally or completely hidden during burst read cycles when the auto-precharge func on is engaged. The precharge opera on will not begin un l a er the last data of the burst write sequence is properly stored in the memory array. Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 86 IS43/46QR16256A ® Long-term Support World Class Quality REFRESH Command The REFRESH command (REF) is used during normal opera on of the device. This command is nonpersistent, so it must be issued each me a refresh is required. The device requires REFRESH cycles at an average periodic interval of tREFI. When CS, RAS/A16 and CAS/A15 are held LOW and WE/A14 HIGH at the rising edge of the clock, the chip enters a REFRESH cycle. All banks of the SDRAM must be precharged and idle for a minimum of the precharge me tRP (MIN) before the REFRESH command can be applied. The refresh addressing is generated by the internal DRAM refresh controller. This makes the address bits “Don’t Care” during a REFRESH command. An internal address counter supplies the addresses during the REFRESH cycle. No control of the external address bus is required once this cycle has started. When the REFRESH cycle has completed, all banks of the SDRAM will be in the precharged (idle) state. A delay between the REFRESH command and the next valid command, except DES, must be greater than or equal to the minimum REFRESH cycle me tRFC (MIN). The tRFC ming parameter depends on memory density. In general, a REFRESH command needs to be issued to the device regularly every tREFI interval. To allow for improved e ciency in scheduling and switching between tasks, some exibility in the absolute refresh interval is provided for postponing and pullingin the refresh command. A limited number Refresh commands can be postponed depending on Refresh mode: maximum of 8 Refresh commands can be postponed when the device is in 1X refresh mode; a maximum of 16 Refresh commands can be postponed when the device is in 2X refresh mode, and a maximum of 32 Refresh commands can be postponed when the device is in 4X refresh mode. At any point in me no more than a total of 8, 16, 32 Refresh commands are allowed to be postponed. When 8 consecu ve Refresh commands are postponed, the resul ng maximum interval between the surrounding Refresh commands is limited to 9 x tREFI (). For both the 2X and 4X Refresh modes, the maximum consecu ve Refresh commands allowed is limited to 17 x tREFI2 and 36 xtREFI4, respec vely. A limited number Refresh commands can be pulled-in as well. A maximum of 8 addi onal Refresh commands can be issued in advance or “pulled-in” in 1X refresh mode; a maximum of 16 addi onal Refresh commands can be issued when in advance in 2X refresh mode; and a maximum of 32 addi onal Refresh commands can be issued in advance when in 4X refresh mode; with each Refresh command reducing the number of regular Refresh commands required later by one. Note that pulling in more than the maximum allowed Refresh command, Refresh commands in advance does not further reduce the number of regular Refresh commands required later, so that the resul ng maximum interval between two surrounding Refresh commands is limited to 9 x tREFI, 18 x tRFEI2 and 36 x tREFI4 respec vely. At any given me, a maximum of 16 REF commands can be issued within 2 x tREF; 32 REF2 commands can be issued within 4 x tREF; and 64 REF4 commands can be issued within 8 x tREFI4. Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 87 ® Long-term Support World Class Quality IS43/46QR16256A REFRESH Command Timing CK CK Command T0 REF T1 DES DES Ta0 Ta1 REF DES tRFC Tb0 DES VALID Tab1 Tb2 Tb3 VALID VALID VALID Tc0 VALID REF Tc1 VALID Tc2 Tc3 VALID VALID tRFC(min) tREFI(max.9 χtREFI) DRAM must be idle DRAM must be idle Time Break Don’t care NOTE 1 Only DES commands allowed a er REFRESH command registered un l tRFC (MIN) expires. NOTE 2 Time interval between two REFRESH commands may be extended to a maximum of 9 x tREFI. Postponing REFRESH Commands (Example of 1X Refresh mode) tREFI 9 χtREFI t tREFI 8REF-Commands postponed Pulling In REFRESH Commands (Example of 1X Refresh mode) tREFI 9 χtREFI t tREFI 8 REF-Commands pulled-in Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 88 ® Long-term Support World Class Quality IS43/46QR16256A Temperature-Controlled Refresh Mode (TCR) During normal opera on, TCR mode disabled, the DRAM must have a Refresh command issued once every tREFI, except for what is allowed by pos ng (see Refresh Command sec on). This means a refresh command must be issued once every 3.9 s if TC greater than or equal to 85° C and once every 7.8 s if TC less than 85° C, as shown in table below. Normal tREFI Refresh (TCR Disabled) Temperature Tc < +45 C +45 C ≤ Tc < +85 C +85 C ≤ Tc < +95 C Normal Temperature External Refresh Period Internal Refresh Period 7.8 s 7.8 s Extended Temperature External Refresh Period Internal Refresh Period 3.9 s 3.9 s (Not Applicable) NOTE 1 If TC is less than +85°C then the external refresh period can be 7.8 s if the DRAM can arbitrate between the temperature switching at the 85°C point. TCR Mode When TCR mode is enabled, the DRAM will register the externally supplied Refresh Command and adjust the internal refresh period to be longer than tREFI of the normal temperature range, when allowed, by skipping REFRESH commands with the proper gear ra o. TCR Mode has two ranges to select between - Normal Temperature Range and Extended Temperature Range; the correct range must be selected so the internal control operates correctly The DRAM is to have the correct REFRESH rate applied externally; the internal refresh rate is determined by the DRAM based upon the temperature. TCR Mode - Normal Temperature Range REFRESH commands are to be issued to DRAM with the refresh period equal to or shorter than tREFI of normal temperature range (0°C to +85°C). In this mode, the system guarantees that the DRAM temperature does not exceed 85°C. The DRAM may adjust the internal refresh period to be longer than tREFI of the normal temperature range by skipping external REFRESH commands with the proper gear ra o when T C is below 45°C. The internal refresh period is automa cally adjusted inside the DRAM and the DRAM controller does not need to provide any addi onal control. TCR Mode - Extended Temperature Range REFRESH commands should be issued to DRAM with the refresh period equal to or shorter than tREFI of extended temperature range (+85°C to +95°C). Even though the external Refresh supports the extended temperature range, the DRAM will adjust its internal refresh period to tREFI of the normal temperature range by skipping external REFRESH commands with proper gear ra o when opera ng in the normal temperature range (0°C to +85°C). The DRAM may adjust the internal refresh period to be longer than tREFI of the normal temperature range by skipping external REFRESH commands with the proper gear ra o when T C is below 45°C. The internal refresh period is automa cally adjusted inside the DRAM and the DRAM controller does not need to provide any addi onal control. Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 89 ® Long-term Support World Class Quality IS43/46QR16256A Normal tREFI Refresh (Temperature-Controlled Refresh Enabled) Normal Temperature Temperature Extended Temperature External Refresh Period Internal Refresh Period Tc < +45 C 7.8 s >> 7.8 s +45 C ≤ Tc < +85 C 7.8 s 7.8 s +85 C ≤ Tc < +95 C External Refresh Period Internal Refresh Period >> 7.8 s 7.8 s 3.9 s (Not Applicable) 3.9 s NOTE 1 If the external refresh period is 7.8 s then DRAM will refresh internally at half the listed refresh rate and will violate refresh speci ca ons. TCR Mode Example Controller External tREFI 3.9μs REFRESH 85ǡC to 95ǡC External tREFI 3.9μs REFRESH REFRESH REFRESH REFRESH REFRESH REFRESH REFRESH REFRESH REFRESH REFRESH REFRESH REFRESH REFRESH Controller issues REFRESH commands at Extended Temperature rate External REFRESH commands not ignored Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 45ǡC to 85ǡC 7.8μs REFRESH REFRESH REFRESH REFRESH Every other external REFRESH ignored REFRESH At low temperature, more REFRESH commands can be ignored 90 ® Long-term Support World Class Quality IS43/46QR16256A Fine Granularity Refresh Mode (FGRM) Mode Register and Command Truth Table The REFRESH cycle me (tRFC) and the average refresh interval (tREFI) of DDR4 SDRAM can be programmed by the MRS command. The appropriate se ng in the mode register will set a single set of REFRESH cycle me and average refresh interval for the DDR4 SDRAM device ( xed mode), or allow the dynamic selec on of one of two sets of REFRESH cycle me and average refresh interval for the DDR4 SDRAM device (on-the- y mode [OTF]). OTF mode must be enabled by MRS before any OTF REFRESH command can be issued. MRS Definition MR3[8] MR3[7] MR3[6] Fine Granularity Refresh 0 0 0 Normal mode (Fixed 1x) 0 0 1 Fixed 2x 0 1 0 Fixed 4x 0 1 1 Reserved 1 0 0 Reserved 1 0 1 Enable on the y 1x/2x 1 1 0 Enable on the y 1x/4x 1 1 1 Reserved There are two types of OTF modes (1x/2x and 1x/4x modes) that are selectable by programming the appropriate values into the mode register. When either of the two OTF modes is selected, DDR4 SDRAM evaluates the BG0 bit when a REFRESH command is issued, and, depending on the status of BG0, it dynamically switches its internal refresh con gura on between 1x and 2x (or 1x and 4x) modes, then executes the corresponding REFRESH opera on. REFRESH Command Truth Table BG1 BG0 BA0-1 A10/ AP A[9:0], A[12:11], A17 H H V V V L V V V V V V H V H V V V RAS CAS WE /A16 /A15 /A14 H H L L L L H L L REFRESH CS ACT Fixed rate OTF – 1x OTF – 2x OTF – 4x L L L Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 MR3[8:6] 0vv 1vv 101 110 91 ® Long-term Support World Class Quality IS43/46QR16256A tREFI and tRFC Parameters The default refresh rate mode is xed 1x mode where REFRESH commands should be issued with the normal rate, i.e. tREFI1 = tREFI(base) (for TCASE 85°C), and the dura on of each REFRESH command is the normal refresh cycle me (tRFC1). In 2x mode (either xed 2x or OTF 2x mode), REFRESH commands should be issued to the DRAM at the double frequency (tREFI2 = tREFI(base)/2) of the normal refresh rate. In 4x mode, REFRESH command rate should be quadrupled (tREFI4 = tREFI(base)/4). Per each mode and command type, tRFC parameter has di erent values as de ned in the following table. For discussion purposes, the REFRESH command that should be issued at the normal refresh rate and has the normal refresh cycle dura on may be referred to as a REF1x command. The refresh command that should be issued at the double frequency (tREFI2 = tREFI(base)/2) may be referred to as a REF2x command. Finally, the REFRESH command that should be issued at the quadruple rate (tREFI4 = tREFI(base)/4) may be referred to as a REF4x command. In the xed 1x refresh rate mode, only REF1x commands are permi ed. In the xed 2x refresh rate mode, only REF2x commands are permi ed. In the xed 4x refresh rate mode, only REF4x commands are permi ed. When the on-the- y 1x/2x refresh rate mode is enabled, both REF1x and REF2x commands are permi ed. When the OTF 1x/4x refresh rate mode is enabled, both REF1x and REF4x commands are permi ed. tREFI and tRFC Parameters Refresh Mode Parameter tREFI (base) o 1X mode tREFI1 o 0 C ” TCASE ” 85 C o o 85 C < TCASE ” 95 C tRFC1 (min) o 2X mode tREFI2 4X mode s tREFI(base)/2 s tREFI(base)/2 s tREFI(base)/4 s 160 ns o tREFI(base)/4 s o tREFI(base)/8 s 110 ns 85 C < TCASE ” 95 C tRFC4 (min) Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 tREFI(base) o 0 C ϴ Write commands can issue precharge automatically with a Write with auto-precharge command (WRA); and is enabled by A10 high. ͻtƌŝƚĞĐommand with A10 = 0 (WR) performs standard Write, bank remains active after write burst. ͻtƌŝƚĞĐŽŵŵĂŶĚǁŝƚŚϭϬсϭ;tZͿƉĞƌĨŽƌŵƐtƌŝƚĞǁŝƚŚĂƵƚŽ-precharge, back goes in to precharge after write burst. Data mask (DM) function is supported for the x8 and x16 configurations only (not supported on x4). The DM function shares a common pin with the '%, and TDQS functions. The DM function only applies to WRITE operations and cannot be enabled at the same time the DBI function is enabled. ͻ/Ĩ'0 is sampled LOW on a given byte lane, the DRAM masks the write data received on the DQ inputs. ͻ/Ĩ'0 is sampled HIGH on a given byte lane, the DRAM does not mask the data and writes this data into the DRAM core. ͻ/ĨZtƌŝƚĞŝƐĞŶĂďůĞĚ͕ƚŚĞŶDĞŶĂďůĞĚ;ǀŝĂDZ^Ϳ͕ǁŝůůƐĞůĞĐƚĞĚďĞƚǁĞĞŶtƌŝƚĞZ non-Persistent Mode (DM disabled) and Write CRC Persistent Mode (DM enabled). WRITE Burst Operation, WL = 9 (AL = 0, CWL = 9, BL8) TRANSITIONING DA TA   NOTE 1 BL8, WL = 0, AL = 0, CWL = 9, Preamble = 1 tCK. NOTE 2 DINn = data-out from column n. NOTE 3 DES commands are shown for ease of illustration; other commands may be valid at these times. NOTE 4 BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during WRITE command at T0. NOTE 5 C/A Parity = Disable, &6 to C/A Latency = Disable, Read DBI = Disable. Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 164 ® Long-term Support World Class Quality IS43/46QR16256A WRITE Burst Operation, WL = 19 (AL = 10, CWL = 9, BL8) T RA NS IT IONING DA TA  NOTE 1 BL8, WL = 19, AL = 10 (CL - 1), CWL = 9, Preamble = 1 tCK. NOTE 2 DINn = data-out from column n. NOTE 3 DES commands are shown for ease of illustration; other commands may be valid at these times. NOTE 4 BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during WRITE command at T0. NOTE 5 C/A Parity = Disable, &6 to C/A Latency = Disable, Read DBI = Disable. ! WRITE Operation Followed by another WRITE Operation Various Burst Read examples are shown below. Consecutive WRITE (BL8) with 1tCK Preamble in Different Bank Group ! NOTE 1 BL8, AL = 0, CWL = 9, Preamble = 1 tCK. NOTE 2 DIN n (or b) = data-in from column n (or column b). NOTE 3 DES commands are shown for ease of illustration; other commands may be valid at these times. NOTE 4 BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during WRITE commands at T0 and T4. NOTE 5 CA parity = disable, &6 to CA latency = disable, Write DBI = disable, Write CRC = disable. NOTE6 The write recovery time (tWR) and write timing parameter (tWTR) are referenced from the first rising clock edge after the last write data shown at T17. Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 165 IS43/46QR16256A ® Long-term Support World Class Quality Consecutive WRITE (BL8) with 2tCK Preamble in Different Bank Group NOTE 1 BL8, AL = 0, CWL = 9+1=107, Preamble = 2 tCK. NOTE 2 DIN n (or b) = data-in from column n (or column b). NOTE 3 DES commands are shown for ease of illustra on; other commands may be valid at these mes. NOTE 4 BL8 se ng ac vated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during WRITE commands at T0 and T4. NOTE 5 CA parity = disable, CS to CA latency = disable, Write DBI = disable, Write CRC = disable. NOTE 6 The write recovery me (tWR) and write ming parameter (tWTR) are referenced from the rst rising clock edge a er the last write data shown at T17. NOTE 7 When opera ng in 2tCK Write Preamble Mode, CWL may need to be programmed to a value at least 1 clock greater than the lowest CWL se ng supported in the applicable tCK range. That means CWL = 9 is not allowed when opera ng in 2tCK Write Preamble Mode. Nonconsecutive WRITE (BL8) with 1 tCK Preamble in Same or Different Bank Group NOTE 1 BL8, AL = 0, CWL = 9, Preamble = 1 tCK, tCCD_S/L = 5 tCK. NOTE 2 DIN n (or b) = data-in from column n (or column b). NOTE 3 DES commands are shown for ease of illustra on; other commands may be valid at these mes. NOTE 4 BL8 se ng ac vated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during WRITE commands at T0 and T5. NOTE 5 CA parity = disable, CS to CA latency = disable, Write DBI = disable, Write CRC = disable. NOTE 6 The write recovery me (tWR) and write ming parameter (tWTR) are referenced from the rst rising clock edge a er the last write data shown at T18. Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 166 IS43/46QR16256A ® Long-term Support World Class Quality Nonconsecutive WRITE (BL8) with 2 tCK Preamble in Same or Different Bank Group NOTE 1 BL8, AL = 0, CWL = 9+1=108, Preamble = 2 tCK, tCCD_S/L = 6 tCK. NOTE 2 DIN n (or b) = data-in from column n (or column b). NOTE 3 DES commands are shown for ease of illustra on; other commands may be valid at these mes. NOTE 4 BL8 se ng ac vated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during WRITE commands at T0 and T6. NOTE 5 CA parity = disable, CS to CA latency = disable, Write DBI = disable, Write CRC = disable. NOTE 6 tCCD_S/L = 5 isn’t allowed in 2tCK preamble mode. NOTE 7 The write recovery me (tWR) and write ming parameter (tWTR) are referenced from the rst rising clock edge a er the last write data shown at T17. NOTE 8 When opera ng in 2tCK Write Preamble Mode, CWL may need to be programmed to a value at least 1 clock greater than the lowest CWL se ng supported in the applicable tCK range. That means CWL = 9 is not allowed when opera ng in 2tCK Write Preamble Mode. WRITE (BC4) OTF to WRITE (BC4) OTF with 1 tCK Preamble in Different Bank Group NOTE 1 BC4, AL = 0, CWL = 9, Preamble = 1 tCK. NOTE 2 DIN n (or b) = data-in from column n (or column b). NOTE 3 DES commands are shown for ease of illustra on; other commands may be valid at these mes. NOTE 4 BC4 se ng ac vated by MR0[1:0] = 01 and A12 = 0 during WRITE commands at T0 and T4. NOTE 5 CA parity = disable, CS to CA latency = disable, Write DBI = disable, Write CRC = disable. NOTE 6 The write recovery me (tWR) and write ming parameter (tWTR) are referenced from the rst rising clock edge a er the last write data shown at T17. Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 167 IS43/46QR16256A ® Long-term Support World Class Quality WRITE (BC4) OTF to WRITE (BC4) OTF with 2 tCK Preamble in Different Bank Group NOTE 1 BC4, AL = 0, CWL = 9+1=107, Preamble = 2 tCK. NOTE 2 DIN n (or b) = data-in from column n (or column b). NOTE 3 DES commands are shown for ease of illustra on; other commands may be valid at these mes. NOTE 4 BC4 se ng ac vated by MR0[1:0] = 01 and A12 = 1 during WRITE commands at T0 and T4. NOTE 5 CA parity = disable, CS to CA latency = disable, Write DBI = disable, Write CRC = disable. NOTE 6 The write recovery me (tWR) and write ming parameter (tWTR) are referenced from the rst rising clock edge a er the last write data shown at T18. NOTE 7 When opera ng in 2tCK Write Preamble Mode, CWL may need to be programmed to a value at least 1 clock greater than the lowest CWL se ng supported in the applicable tCK range. That means CWL = 9 is not allowed when opera ng in 2tCK Write Preamble Mode. WRITE (BC4) Fixed to WRITE (BC4) Fixed with 1 tCK Preamble in Different Bank Group NOTE 1 BC4, AL = 0, CWL = 9, Preamble = 1 tCK. NOTE 2 DIN n (or b) = data-in from column n (or column b). NOTE 3 DES commands are shown for ease of illustra on; other commands may be valid at these mes. NOTE 4 BC4 se ng ac vated by MR0[1:0] = 01 and A12 = 0 during WRITE commands at T0 and T4. NOTE 5 CA parity = disable, CS to CA latency = disable, Write DBI = disable, Write CRC = disable. NOTE 6 The write recovery me (tWR) and write ming parameter (tWTR) are referenced from the rst rising clock edge a er the last write data shown at T15. Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 168 IS43/46QR16256A ® Long-term Support World Class Quality WRITE (BL8) to WRITE (BC4) OTF with 1tCK Preamble in Different Bank Group NOTE 1 BL=8/BC=4, AL =0, CL = 9, Preamble = 1 tCK NOTE 2 DIN n (or b) = data-in from column n (or column b). NOTE 3 DES commands are shown for ease of illustra on; other commands may be valid at these mes. NOTE 4 BL8 se ng ac vated by MR0[1:0] = 01 and A12 = 1 during WRITE command at T0. BC4 se ng ac vated by MR0[1:0] = 01 and A12 = 0 during WRITE command at T4. NOTE 5 CA parity = disable, CS to CA latency = disable, Read DBI = disable, Write CRC = disable. NOTE 6 The write recovery me (tWR) and write ming parameter (tWTR) are referenced from the rst rising clock edge a er the last write data shown at T17. WRITE (BL8) to READ (BL8) with 1tCK Preamble in Same Bank Group NOTE 1 BL = 8, AL = 0, CWL = 9, CL = 11, Preamble = 1tCK NOTE 2 DIN n = data-in to column n (or column b). DOUT b = data-out from column b. NOTE 3 DES commands are shown for ease of illustra on; other commands may be valid at these mes. NOTE 4 BL8 se ng ac vated by either MR0[A1:A0 = 0:0] or MR0[A1:A0 = 0:1] and A12 = 1 during WRITE command at T0 and READ command at T17. NOTE 5 CA Parity = Disable, CS to CA Latency = Disable, Write DBI = Disable. NOTE 6 The write ming parameter (tWTR_L) are referenced from the rst rising clock edge a er the last write data shown at T13. Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 169 IS43/46QR16256A ® Long-term Support World Class Quality WRITE (BC4)OTF to READ (BC4)OTF with 1tCK Preamble in Different Bank Group NOTE 1 BC = 4, AL = 0, CWL = 9, CL = 11, Preamble = 1tCK NOTE 2 DIN n = data-in to column n (or column b). DOUT b = data-out from column b. NOTE 3 DES commands are shown for ease of illustra on; other commands may be valid at these mes. NOTE 4 BC4 se ng ac vated by MR0[A1:A0 = 0:1] and A12 = 0 during WRITE command at T0 and READ command at T15. NOTE 5 CA Parity = Disable, CS to CA Latency = Disable, Write DBI = Disable. NOTE 6 The write ming parameter (tWTR_S) are referenced from the rst rising clock edge a er the last write data shown at T13. WRITE (BC4)OTF to READ (BC4)OTF with 1tCK Preamble in Same Bank Group NOTE 1 BC = 4, AL = 0, CWL = 9, CL = 11, Preamble = 1tCK NOTE 2 DIN n = data-in to column n (or column b). DOUT b = data-out from column b. NOTE 3 DES commands are shown for ease of illustra on; other commands may be valid at these mes. NOTE 4 BC4 se ng ac vated by MR0[A1:A0 = 0:1] and A12 = 0 during WRITE command at T0 and READ command at T17. NOTE 5 CA Parity = Disable, CS to CA Latency = Disable, Write DBI = Disable. NOTE 6 The write ming parameter (tWTR_L) are referenced from the rst rising clock edge a er the last write data shown at T13. Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 170 IS43/46QR16256A ® Long-term Support World Class Quality WRITE (BC4)Fixed to READ (BC4)Fixed with 1tCK Preamble in Different Bank Group NOTE 1 BC = 4, AL = 0, CWL = 9, CL = 11, Preamble = 1tCK NOTE 2 DIN n = data-in to column n (or column b). DOUT b = data-out from column b. NOTE 3 DES commands are shown for ease of illustra on; other commands may be valid at these mes. NOTE 4 BC4 se ng ac vated by MR0[A1:A0 = 1:0]. NOTE 5 CA Parity = Disable, CS to CA Latency = Disable, Write DBI = Disable. NOTE 6 The write ming parameter (tWTR_S) are referenced from the rst rising clock edge a er the last write data shown at T11. WRITE (BC4)Fixed to READ (BC4)Fixed with 1tCK Preamble in Same Bank Group NOTE 1 BC = 4, AL = 0, CWL = 9, CL = 11, Preamble = 1tCK NOTE 2 DIN n = data-in to column n (or column b). DOUT b = data-out from column b. NOTE 3 DES commands are shown for ease of illustra on; other commands may be valid at these mes. NOTE 4 BC4 se ng ac vated by MR0[A1:A0 = 1:0]. NOTE 5 CA Parity = Disable, CS to CA Latency = Disable, Write DBI = Disable. NOTE 6 The write ming parameter (tWTR_L) are referenced from the rst rising clock edge a er the last write data shown at T11. Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 171 IS43/46QR16256A ® Long-term Support World Class Quality WRITE (BL8) to WRITE (BC4) OTF with 1tCK Preamble in Different Bank Group NOTE 1 BL = 8 / BC = 4, AL = 0, CWL = 9, Preamble = 1tCK NOTE 2 DIN n (or b) = data-in to column n (or column b). NOTE 3 DES commands are shown for ease of illustra on; other commands may be valid at these mes. NOTE 4 BL8 se ng ac vated by MR0[A1:A0 = 0:1] and A12 =1 during WRITE command at T0. BC4 se ng ac vated by MR0[A1:A0 = 0:1] and A12 =0 during WRITE command at T4. NOTE 5 CA Parity = Disable, CS to CA Latency = Disable, Write DBI = Disable. NOTE 6 The write recovery me (tWR) and write ming parameter (tWTR) are referenced from the rst rising clock edge a er the last write data shown at T17 WRITE (BC4) OTF to WRITE (BL8) with 1tCK Preamble in Different Bank Group NOTE 1 BL = 8 / BC = 4, AL = 0, CWL = 9, Preamble = 1tCK NOTE 2 DIN n (or b) = data-in to column n (or column b). NOTE 3 DES commands are shown for ease of illustra on; other commands may be valid at these mes. NOTE 4 BC4 se ng ac vated by MR0[A1:A0 = 0:1] and A12 =0 during WRITE command at T0. BL8 se ng ac vated by MR0[A1:A0 = 0:1] and A12 =1 during WRITE command at T4. NOTE 5 CA Parity = Disable, CS to CA Latency = Disable, Write DBI = Disable. NOTE 6 The write recovery me (tWR) and write ming parameter (tWTR) are referenced from the rst rising clock edge a er the last write data shown at T17 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 172 IS43/46QR16256A ® Long-term Support World Class Quality WRITE (BL8/BC4) OTF to PRECHARGE Operation with 1tCK Preamble NOTE 1 BL = 8 / BC = 4, AL = 0, CWL = 9, Preamble = 1tCK, tWR = 12 NOTE 2 DIN n = data-in to column n. NOTE 3 DES commands are shown for ease of illustra on; other commands may be valid at these mes. NOTE 4 BC4 se ng ac vated by MR0[A1:A0 = 0:1] and A12 =0 during WRITE command at T0. BL8 se ng ac vated by MR0[A1:A0 = 0:0] or MR0[A1:0 = 01] and A12 =1 during WRITE command at T0. NOTE 5 CA Parity = Disable, CS to CA Latency = Disable, Write DBI = Disable. NOTE 6 The write recovery me (tWR) is referenced from the rst rising clock edge a er the last write data shown at T13. tWR speci es the last burst write cycle un l the precharge command can be issued to the same bank. WRITE (BC4) Fixed to PRECHARGE Operation with 1tCK Preamble NOTE 1 BC = 4, AL = 0, CWL = 9, Preamble = 1tCK, tWR = 12 NOTE 2 DIN n = data-in to column n. NOTE 3 DES commands are shown for ease of illustra on; other commands may be valid at these mes. NOTE 4 BC4 se ng ac vated by MR0[A1:A0 = 1:0]. NOTE 5 CA Parity = Disable, CS to CA Latency = Disable, Write DBI = Disable. NOTE 6 The write recovery me (tWR) is referenced from the rst rising clock edge a er the last write data shown at T11. tWR speci es the last burst write cycle un l the precharge command can be issued to the same bank. Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 173 IS43/46QR16256A ® Long-term Support World Class Quality WRITE (BL8/BC4) OTF with Auto PRECHARGE Operation and 1tCK Preamble NOTE 1 BL = 8 / BC = 4, AL = 0, CWL = 9, Preamble = 1tCK, WR = 12 NOTE 2 DIN n = data-in to column n. NOTE 3 DES commands are shown for ease of illustra on; other commands may be valid at these mes. NOTE 4 BC4 se ng ac vated by MR0[A1:A0 = 0:1] and A12 =0 during WRITE command at T0. BL8 se ng ac vated by either MR0[A1:0 = 00] or MR0[A1:0 = 01] and A12 =1 during WRITE command at T0. NOTE 5 CA Parity = Disable, CS to CA Latency = Disable, Write DBI = Disable. NOTE 6 The write recovery me (WR) is referenced from the rst rising clock edge a er the last write data shown at T13. WR speci es the last burst write cycle un l the precharge command can be issued to the same bank. WRITE (BC4) Fixed with Auto PRECHARGE Operation and 1tCK Preamble NOTE 1 BC = 4, AL = 0, CWL = 9, Preamble = 1tCK, WR = 12 NOTE 2 DIN n = data-in to column n. NOTE 3 DES commands are shown for ease of illustra on; other commands may be valid at these mes. NOTE 4 BC4 se ng ac vated by MR0[A1:A0 = 1:0]. NOTE 5 CA Parity = Disable, CS to CA Latency = Disable, Write DBI = Disable. NOTE 6 The write recovery me (tWR) is referenced from the rst rising clock edge a er the last write data shown at T11. WR speci es the last burst write cycle un l the precharge command can be issued to the same bank. Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 174 IS43/46QR16256A ® Long-term Support World Class Quality WRITE (BL8/BC4) OTF with 1tCK Preamble and DBI NOTE 1 BL = 8 / BC = 4, AL = 0, CWL = 9, Preamble = 1tCK NOTE 2 DIN n = data-in to column n. NOTE 3 DES commands are shown for ease of illustra on; other commands may be valid at these mes. NOTE 4 BC4 se ng ac vated by MR0[A1:A0 = 0:1] and A12 =0 during WRITE command at T0. BL8 se ng ac vated by either MR0[A1:A0 = 0:0] or MR0[A1:A0 = 0:1] and A12 =1 during WRITE command at T0. NOTE 5 CA Parity = Disable, CS to CA Latency = Disable, Write DBI = Enable, CRC = Disable. NOTE 6 The write recovery me (tWR_DBI) and write ming parameter (tWTR_DBI) are referenced from the rst rising clock edge a er the last write data shown at T13. WRITE (BC4) Fixed with 1tCK Preamble and DBI NOTE 1 BC = 4, AL = 0, CWL = 9, Preamble = 1tCK NOTE 2 DIN n = data-in to column n. NOTE 3 DES commands are shown for ease of illustra on; other commands may be valid at these mes. NOTE 4 BC4 se ng ac vated by MR0[A1:A0 = 1:0]. NOTE 5 CA Parity = Disable, CS to CA Latency = Disable, Write DBI = Enable, CRC = Disable. NOTE 6 The write recovery me (tWR_DBI) and write ming parameter (tWTR_DBI) are referenced from the rst rising clock edge a er the last write data shown at T11. Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 175 IS43/46QR16256A ® Long-term Support World Class Quality Consecutive WRITE (BL8) with 1tCK Preamble and CA Parity in Different Bank Group NOTE 1 BL = 8, AL = 0, CWL = 9, PL = 4, Preamble = 1tCK NOTE 2 DIN n (or b) = data-in to column n(or column b). NOTE 3 DES commands are shown for ease of illustra on; other commands may be valid at these mes. NOTE 4 BL8 se ng ac vated by either MR0[A1:A0 = 0:0] or MR0[A1:A0 = 0:1] and A12 =1 during WRITE command at T0 and T4. NOTE 5 CA Parity = Enable, CS to CA Latency = Disable, Write DBI = Disable. NOTE 6 The write recovery me (tWR) and write ming parameter (tWTR) are referenced from the rst rising clock edge a er the last write data shown at T21. Consecutive WRITE (BL8/BC4) OTF with 1tCK Preamble and Write CRC in Same or Different Bank Group NOTE 1 NOTE 2 NOTE 3 NOTE 4 NOTE 5 NOTE 6 NOTE 7 BL = 8/BC = 4, AL = 0, CWL = 9, Preamble = 1tCK, tCCD_S/L = 5 DIN n (or b) = data-in to column n (or column b). DES commands are shown for ease of illustra on; other commands may be valid at these mes. BL8 se ng ac vated by either MR0[A1:0 = 00] or MR0[A1:0 = 01] and A12 = 1 during WRITE command at T0 and T5. BC4 se ng ac vated by MR0[A1:A0 = 0:1] and A12 = 0 during WRITE command at T0 and T5. C/A Parity = Disable, CS to C/A Latency = Disable, Write DBI = Disable, Write CRC = Enable. The write recovery me (tWR) and write ming parameter (tWTR) are referenced from the rst rising clock edge a er the last write data shown at T18 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 176 IS43/46QR16256A ® Long-term Support World Class Quality Consecutive WRITE (BC4)Fixed with 1tCK Preamble and Write CRC in Same or Different Bank Group NOTE 1 NOTE 2 NOTE 3 NOTE 4 NOTE 5 NOTE 6 BL = 8, AL = 0, CWL = 9, Preamble = 1tCK, tCCD_S/L = 5 DIN n (or b) = data-in to column n(or column b). DES commands are shown for ease of illustra on; other commands may be valid at these mes. BC4 se ng ac vated by MR0[A1:A0 = 1:0] at T0 and T5. CA Parity = Disable, CS to CA Latency = Disable, Write DBI = Disable, Write CRC = Enable. The write recovery me (tWR) and write ming parameter (tWTR) are referenced from the rst rising clock edge a er the last write data shown at T16. Nonconsecutive WRITE (BL8/BC4) OTF with 1tCK Preamble and Write CRC in Same or Different Bank Group NOTE 1 NOTE 2 NOTE 3 NOTE 4 NOTE 5 NOTE 6 NOTE 7 BL = 8, AL = 0, CWL = 9, Preamble = 1tCK, tCCD_S/L = 6 DIN n (or b) = data-in to column n(or column b). DES commands are shown for ease of illustra on; other commands may be valid at these mes. BL8 se ng ac vated by either MR0[A1A:0 = 0:0] or MR0[A1A:0 = 0:1] and A12 =1 during WRITE command at T0 and T6. BC4 se ng ac vated by MR0[A1:A0 = 0:1] and A12 =0 during WRITE command at T0 and T6. CA Parity = Disable, CS to CA Latency = Disable, Write DBI = Disable, Write CRC = Enable. The write recovery me (tWR) and write ming parameter (tWTR) are referenced from the rst rising clock edge a er the last write data shown at T19. Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 177 IS43/46QR16256A ® Long-term Support World Class Quality Nonconsecutive WRITE (BL8/BC4) OTF with 2tCK Preamble and Write CRC in Same or Different Bank Group NOTE 1 BL = 8, AL = 0, CWL = 9 + 1 = 109, Preamble = 2tCK, tCCD_S/L = 7 NOTE 2 DIN n (or b) = data-in to column n(or column b). NOTE 3 DES commands are shown for ease of illustra on; other commands may be valid at these mes. NOTE 4 BL8 se ng ac vated by either MR0[A1:A0 = 0:0] or MR0[A1:A0 = 0:1] and A12 =1 during WRITE command at T0 and T7. NOTE 5 BC4 se ng ac vated by MR0[A1:A0 = 0:1] and A12 =0 during WRITE command at T0 and T7. NOTE 6 CA Parity = Disable, CS to CA Latency = Disable, Write DBI = Disable, Write CRC = Enable. NOTE 7 tCCD_S/L = 6 isn’t allowed in 2tCK preamble mode. NOTE 8 The write recovery me (tWR) and write ming parameter (tWTR) are referenced from the rst rising clock edge a er the last write data shown at T21. NOTE 9 When opera ng in 2tCK Write Preamble Mode, CWL must be programmed to a value at least 1 clock greater than the lowest CWL se ng supported in the applicable tCK range. That means CWL = 9 is not allowed when opera ng in 2tCK Write Preamble Mode Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 178 IS43/46QR16256A ® Long-term Support World Class Quality WRITE (BL8/BC4)OTF/Fixed with 1tCK Preamble and Write CRC and DM in Same or Different Bank Group NOTE 1 BL = 8 / BC = 4, AL = 0, CWL = 9, Preamble = 1tCK NOTE 2 DIN n = data-in to column n. NOTE 3 DES commands are shown for ease of illustra on; other commands may be valid at these mes. NOTE 4 BL8 se ng ac vated by either MR0[A1:A0 = 0:0] or MR0[A1:A0 = 0:1] and A12 = 1 during WRITE command at T0. NOTE 5 BC4 se ng ac vated by either MR0[A1:A0 = 1:0] or MR0[A1:A0 = 0:1] and A12 = 0 during READ command at T0. NOTE 6 CA Parity = Disable, CS to CA Latency = Disable, Write DBI = Disable, Write CRC = Enable, DM = Enable. NOTE 7 The write recovery me (tWR_CRC_ DM) and write ming parameter (tWR_S_CRC_ DM/tWR_L_CRC_ DM) are referenced from the rst rising clock edge a er the last write data shown at T13. Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 179 ® Long-term Support World Class Quality IS43/46QR16256A ZQ Calibration Commands ZQ Calibra on command is used to calibrate DRAM RON and ODT values. The device needs a longer me to calibrate the output driver and on-die termina on circuits at ini aliza on and a rela vely smaller me to perform periodic calibra ons. The ZQCL command is used to perform the ini al calibra on during the power-up ini aliza on sequence. This command may be issued at any me by the controller depending on the system environment. The ZQCL command triggers the calibra on engine inside the DRAM and, once calibra on is achieved, the calibrated values are transferred from the calibra on engine to DRAM IO, which is re ected as an updated output driver and on-die termina on values. The rst ZQCL command issued a er reset is allowed a ming period of tZQinit to perform the full calibra on and the transfer of values. All other ZQCL commands except the rst ZQCL command issued a er RESET are allowed a ming period of tZQoper. The ZQCS command is used to perform periodic calibra ons to account for voltage and temperature varia ons. A shorter ming window is provided to perform the calibra on and transfer of values as de ned by ming parameter tZQCS. One ZQCS command can e ec vely correct a minimum of 0.5 % (ZQ correc on) of RON and RTT impedance error within 64 nCK for all speed bins assuming the maximum sensi vi es speci ed in the Output Driver and ODT Voltage and Temperature Sensi vity tables. The appropriate interval between ZQCS commands can be determined from these tables and other applica on-speci c parameters. One method for calcula ng the interval between ZQCS commands, given the temperature (Tdri rate) and voltage (Vdri rate) dri rates that the device is subjected to in the applica on, is illustrated. The interval could be de ned by the following formula: ZQCorrecƟon (TSens x TdriŌrate) + (VSens x VdriŌrate) where TSens = max(dRTTdT, dRONdTM) and VSens = max(dRTTdV, dRONdVM) de ne the temperature and voltage sensi vi es. o o For example, if TSens = 1.5% / C, VSens = 0.15% / mV, Tdri rate = 1 C / sec and Vdri rate = 15 mV /sec, then the interval between ZQCS commands is calculated as: 0.5 (1.5 x 1) + (0.15 x 15) = 0.133 у 128ms No other ac vi es should be performed on the DRAM channel by the controller for the dura on of tZQinit, tZQoper, or tZQCS. The quiet me on the DRAM channel allows accurate calibra on of output driver and on-die termina on values. Once DRAM calibra on is achieved, the device should disable the ZQ current consump on path to reduce power. All banks must be precharged and tRP met before ZQCL or ZQCS commands are issued by the controller. ZQ calibra on commands can also be issued in parallel to DLL lock me when coming out of self refresh. Upon self refresh exit, the device will not perform an IO calibra on without an explicit ZQ calibra on command. The earliest possible me for a ZQ calibra on command (short or long) a er self refresh exit is tXSF. In systems that share the ZQ resistor between devices, the controller must not allow any overlap of tZQoper, tZQinit, or tZQCS between the devices. Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 180 IS43/46QR16256A ® Long-term Support World Class Quality ZQ Calibration Timing NOTE 1 CKE must be con nuously registered HIGH during the calibra on procedure. NOTE 2 On-die termina on must be disabled via the ODT signal or MRS during the calibra on procedure or the DRAM will automa cally disable R . NOTE 3 All devices connected to the DQ bus should be High Z during the calibra on procedure. Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 181 ® Long-term Support World Class Quality IS43/46QR16256A On-Die Termination (ODT) On-die termina on (ODT) is a feature of the DDR4 SDRAM that enables the DRAM to change termina on resistance for each DQ, DQS, DQS, and DMfor x4 and x8 con gura on (and DQS, TDQS, for x8 con gura on, when enabled via A11 = 1 in MR1) via the ODT control pin or WRITE command or default parking value with MR se ng. For x16 con gura on, ODT is applied to each UDQ, LDQ, LDQS, LDQS, UDQS, UDQS, UDM and LDM signal. The ODT feature is designed to improve signal integrity of the memory channel by allowing the DRAM controller to independently change termina on resistance for any or all DRAM devices. More details about ODT control modes and ODT ming modes can be found further down in this document. The ODT feature is turned o and not supported in self refresh mode. Functional Representation of ODT ODT To other circuity like VDDQ RTT switch DQ, DQS, DM , TDQS The switch is enabled by the internal ODT control logic, which uses the external ODT pin and other control informa on. The value of RTT is determined by the se ngs of mode register bits (see Mode Register). The ODT pin will be ignored if the mode register MR1 is programmed to disable RTT_NOM [MR1[9,6,2] = 0,0,0] and in self refresh mode. ODT Mode Register and ODT State Table The ODT mode of the DDR4 device has four states: data termina on disable, R TT_NOM, RTT_WR and RTT_PARK. The ODT mode is enabled if any of MR1[10,9,8] (RTT_NOM), MR2[11:9] (RTT_WR), or MR5[8:6] (RTT_PARK) are non-zero. When enabled, the value of RTT is determined by the se ngs of these bits. RTT control of each RTT condi on is possible with WR/RD command and ODT pin. RTT_WR: The rank that is being wri en to provide termina on regardless of ODT pin status (either HIGH or LOW). RTT_NOM: DRAM turns ON RTT_NOM if it sees ODT asserted (except when ODT is disabled by MR1). RTT_PARK: Default parked value set via MR5 to be enabled and ODT pin is driven LOW. The Termina on State Table below shows various interac ons. The RTT values have the following priority: Data termina on disable RTT_WR RTT_NOM RTT_PARK Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 182 ® Long-term Support World Class Quality IS43/46QR16256A Termination State Table RTT_PARK MR5[8:6] RTT_NOM MR1[10:8] Enabled Enabled Disabled Enabled Disabled Disabled ODT pin DRAM terminaƟon state Note HIGH RTT_NOM 1,2 LOW RTT_PARK 1,2 Don’t care RTT_PARK 1,2,3 HIGH RTT_NOM 1,2 LOW Hi-Z 1,2 Don’t care Hi-Z 1,2,3 NOTE 1 When a READ command is executed, DRAM termina on state will be High-Z for de ned period independent of ODT pin and MR se ng of RTT_PARK/RTT_NOM. This is described in the ODT During Read sec on. NOTE 2 If RTT_WR is enabled, RTT_WR will be ac vated by WRITE command for de ned period me independent of ODT pin and MR se ng of RTT_PARK /RTT_NOM. This is described in the Dynamic ODT sec on. NOTE 3 If RTT_NOM MR is disabled, ODT receiver power will be turned o to save power. On-die termina on e ec ve resistances are de ned and can be selected by any or all of the following op ons: MR1[10:8] (RTT_NOM) - Disable, 240 , 120 , 80 , 60 , 48 , 40 , and 34 . MR2[11:9] (RTT_WR) - Disable, 240 ,120 , and 80 . MR5[8:6] (RTT_PARK) - Disable, 240 , 120 , 80 , 60 , 48 , 40 , and 34 . ODT is applied to the following inputs: X4: DQs, DM, DQS, and DQS inputs. X8: DQs, DM, DQS, DQS, TDQS, and TDQS inputs. X16: DQs, LDM, UDM, LDQS, LDQS, UDQS, and UDQS inputs. ODT Definition of Voltages and Currents Chip In Termination Mode ODT VDDQ To other circuity like RCV, ... RTT DQ Iout Vout VSSQ Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 183 ® Long-term Support World Class Quality IS43/46QR16256A Synchronous ODT Mode Synchronous ODT mode is selected whenever the DLL is turned on and locked. Based on the power-down de ni on, these modes include the following: Any bank ac ve with CKE HIGH Refresh with CKE HIGH Idle mode with CKE HIGH Ac ve power-down mode (regardless of MR1 bit A10) Precharge power-down mode In synchronous ODT mode, RTT_NOM will be turned on DODTLon clock cycles a er ODT is sampled HIGH by a rising clock edge and turned o DODTLo clock cycles a er ODT is registered LOW by a rising clock edge. The ODT latency is determined by the programmed values for: CWL (CAS Write Latency), AL (addi ve Latency), and PL (Parity Latency) as well as the programmed state of the preamble. ODT Latency and Posted ODT In synchronous ODT mode, the ODT latencies are summarized in the table below. For details, refer to the latency de ni ons. ODT Latency at DDR4-2133/-2400/-2666/-3200 Symbol Parameter 1 tCK Preamble 2 tCK Preamble DODTLon Direct ODT turn on Latency CWL + AL + PL – 2 CK CWL + AL + PL – 3 CK DODTLoī Direct ODT turn o Latency CWL + AL + PL – 2 CK CWL + AL + PL – 3 CK RODTLoī Read command to internal ODT turn o Latency CWL + AL + PL – 2 CK CWL + AL + PL – 3 CK RODTLon4 Read command to RTT_PARK turn on Latency in BC4- xed RODTLo + 4 RODTLo + 5 RODTLon8 Read command to RTT_PARK turn on Latency in BC4/BL8-OTF RODTLo + 6 RODTLo + 7 Unit tCK NOTE 1 Applicable when WRITE CRC is disabled. Timing Parameters In synchronous ODT mode, the following parameters apply: DODTLon, DODTLo , RODTLo , RODTLon4, RODTLon8, tADC (MIN) (MAX). tADC (MIN) and tADC (MAX) are minimum and maximum R TT change ming skew between di erent termina on values. These ming parameters apply to both the synchronous ODT mode and the data termina on disable mode. When ODT is asserted, it must remain HIGH un l minimum ODTH4 (BC = 4) or ODTH8 (BL = 8) is sa s ed. If Write CRC Mode or 2 tCK Preamble Mode is enabled, ODTH should be adjusted to account for these. ODTH is measured from ODT rst registered HIGH to ODT rst registered LOW or from the registra on of a WRITE command. Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 184 IS43/46QR16256A ® Long-term Support World Class Quality Synchronous ODT Timing with BL8 NOTE 1 Example for CWL = 9, AL = 0, PL = 0; DODTLon = AL + PL +CWL - 2 = 7; DODTLo = AL + PL + CWL - 2 = 7. NOTE 2 ODT must be held HIGH for at least ODTH8 a er asser on (T1). Synchronous ODT with BC4 NOTE 1 Example for CWL = 9, AL = 10, PL = 0; DODTLon/o = AL + PL+ CWL - 2 = 17; ODTcnw = AL + PL+ CWL - 2 = 17. NOTE 2 ODT must be held HIGH for at least ODTH4 a er asser on (T1). Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 185 ® Long-term Support World Class Quality IS43/46QR16256A ODT During Reads Because the DRAM cannot terminate with RTT and drive with RON at the same me; RTT may nominally not be enabled un l the end of the postamble as shown in the example below. At cycle T25, the device turns on the termina on when it stops driving, which is determined by tHZ. If the DRAM stops driving early (that is, tHZ is early), then tADC (MIN) ming may apply. If the DRAM stops driving late (that is, tHZ is late), then the DRAM complies with tADC (MAX) ming. ODT During Reads T0 T1 T2 T3 T4 T5 T6 T7 T8 T19 T21 T22 T23 T24 T25 T26 T27 T28 diff_CK CMD RD Addr A RL = AL + CL ODT RODTLof f = RL - 2 = CL + AL - 2 DODTLon = WL - 2 tADCmin tADCmin tADCmax tADCmax DRAM_ODT RTT_PARK RTT_NOM DQSdiff DQ QA0 QA1 QA2 QA3 QA4 QA5 QA6 QA7 NOTE 1 Example for CL = 11; PL = 0, AL = CL - 1 = 10; RL = PL +AL + CL = 21; CWL= 9; DODTLon = PL + AL + CWL - 2 = 17; DODTLo = PL + AL + CWL - 2 = 17;1tCK preamble Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 186 IS43/46QR16256A ® Long-term Support World Class Quality Dynamic ODT In certain applica on cases and to further enhance signal integrity on the data bus, it is desirable that the termina on strength of the device can be changed without issuing an MRS command. This requirement is supported by the dynamic ODT feature, described below. Functional Description The dynamic ODT mode is enabled if bit A9 or A10 of MR2 is set to 1. Three RTT values are available: RTT_NOM, RTT_WR, and RTT_PARK. – The value for RTT_NOM is preselected via bits MR1[10:8]. – The value for RTT_WR is preselected via bits MR2[11:9]. – The value for RTT_PARK is preselected via bits MR5[8:6]. During opera on without WRITE commands, the termina on is controlled as follows: – Nominal termina on strength RTT_NOM or RTT_PARK is selected. – RTT_NOM on/o ming is controlled via ODT pin and latencies DODTLon and DODTLo ; and RTT_PARK is on when ODT is LOW. When a WRITE command (WR, WRA, WRS4, WRS8, WRAS4, WRAS8) is registered, and if Dynamic ODT is enabled, the termina on is controlled as follows: – Latency ODTLcnw a er the WRITE command, termina on strength RTT_WR is selected. – Latency ODTLcwn8 (for BL8, xed by MRS or selected OTF) or ODTLcwn4 (for BC4, xed by MRS or selected OTF) a er the WRITE command, termina on strength RTT_WR is deselected. One or two clocks will be added into or subtracted from ODTLcwn8 and ODTLcwn4, depending on Write CRC Mode and/or 2 tCK preamble enablement. The following table shows latencies and ming parameters which are relevant for the on-die termina on control in dynamic ODT mode. The dynamic ODT feature is not supported in DLL-o mode. MRS command must be used to set RTT_WR, MR2[11:9] = 000, to disable dynamic ODT externally. Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 187 ® Long-term Support World Class Quality IS43/46QR16256A Dynamic ODT Latencies and Timing (1 tCK Preamble Mode and CRC Disabled) Abbr. DeĮned from DeĮne to DeĮniƟon for all DDR4 speed bins Unit ODTLcnw Registering external write command Change RTT strength from RTT_PARK/RTT_NOM to RTT_WR ODTLcnw = WL - 2 tCK ODTLcwn4 Registering external write command Change RTT strength from RTT_WR to RTT_PARK/RTT_NOM ODTLcwn4 = 4 + ODTLcnw tCK ODTLcwn8 Registering external write command Change RTT strength from RTT_WR to RTT_PARK/RTT_NOM ODTLcwn8 = 6 + ODTLcnw tCK(avg) tADC ODTLcnw ODTLcwn RTT valid tADC(min) = 0.3 tADC(max) = 0.7 tCK(avg) Name and DescripƟon ODT Latency for changing from RTT_PARK/RTT_NOM to RTT_WR ODT Latency for change from RTT_WR to RTT_PARK/RTT_NOM (BL = 4) ODT Latency for change from RTT_WR to RTT_PARK/RTT_NOM (BL = 8) RTT change skew Dynamic ODT Latencies and Timing with Preamble Mode and CRC Mode Matrix Symbol 1tck Preamble CRC oī 2tck Preamble CRC on CRC oī Unit CRC on ODTLcnw WL - 2 WL - 2 WL - 3 WL - 3 ODTLcwn4 ODTLcnw +4 ODTLcnw +7 ODTLcnw +5 ODTLcnw +8 ODTLcwn8 ODTLcnw +6 ODTLcnw +7 ODTLcnw +7 ODTLcnw +8 tCK Dynamic ODT (1t CK Preamble; CL = 14, CWL = 11, BL = 8, AL = 0, CRC Disabled) diff_CK CMD WR O DT DODTLon = WL - 2 DODTLoff = WL - 2 tADC,max tADC,max RTT tADC,max Rtt_WR Rtt_PARK tADC,max Rtt_PARK tADC,min ODTLcnw Rtt_NOM Rtt_PARK tADC,min tADC,min tADC,min ODTLcwn NOTE 1 ODTLcnw = WL - 2 (1 tCK preamble) or WL - 3 (2 tCK preamble). NOTE 2 If BC4 then ODTLcwn = WL+4 if CRC disabled or WL+5 if CRC enabled; If BL8 then ODTLcwn = WL+6 if CRC disabled or WL+7 if CRC enabled. Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 188 ® Long-term Support World Class Quality IS43/46QR16256A Dynamic ODT Overlapped with RTT_NOM (CL=14, CWL=11, BL=8, AL=0, CRC Disabled) diff_CK CMD WR ODT ODTLcnw ODTLcwn8 tADC,max RTT Rtt_NOM tADC,max Rtt_NOM Rtt_WR tADC,min tADC,max tADC,min Rtt_PARK tADC,min DODTLoff = CWL - 2 NOTE 1 Behavior with WR command issued while ODT is being registered HIGH. Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 189 ® Long-term Support World Class Quality IS43/46QR16256A Asynchronous ODT Mode Asynchronous ODT mode is selected when DRAM runs in DLL o mode. In asynchronous ODT ming mode, the internal ODT command is not delayed by either Addi ve Latency (AL) or the Parity Latency (PL) rela ve to the external ODT signal (RTT_NOM). In asynchronous ODT mode, two ming parameters apply: tAONAS (MIN/MAX), tAOFAS (MIN/MAX). RTT_NOM turn-on me Minimum RTT_NOM turn-on me (tAONAS (MIN) is the point in me when the device termina on circuit leaves RTT_PARK and ODT resistance begins to turn on. Maximum RTT_NOM turn-on me (tAONAS [MAX]) is the point in me when the ODT resistance has reached RTT_NOM. tAONAS (MIN) and tAONAS (MAX) are Minimum RTT_NOM turn-o measured from ODT being sampled HIGH. RTT_NOM turn-o me me ( tAOFAS [MIN]) is the point in me when the device's termina on circuit starts to leave RTT_NOM. Maximum RTT_NOM turn-o me ( tAOFAS [MAX]) is the point in me when the on die termina on has reached RTT_PARK. tAOFAS (MIN) and tAOFAS (MAX) are measured from ODT being sampled LOW. Asynchronous ODT Timings with DLL Off T0 T1 T2 T3 T4 T5 T6 Ti Ti+1 TI+2 Ti+3 Ti+4 Ti+5 Ti+6 Ta Tb Tc diff_CK CKE tIH tIH tIS tIS ODT tAONAS max RTT RTT_PARK TD_ODT_Async RTT_NOM tAONAS min Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 tAOFAS min tAOFAS max 190 ® Long-term Support World Class Quality IS43/46QR16256A ODT buffer disabled mode for Power down DRAM does not provide R _NOM termina on during power down when ODT input bu er deac va on mode is enabled in MR5 bit A5. To account for DRAM internal delay on CKE line to disable the ODT bu er and block the sampled output, the host controller must con nuously drive ODT to either low or high when entering power down. The ODT signal may be oa ng a er tCPDEDmin has expired. In this mode, RTT_NOM termina on corresponding to sampled ODT at the input a er CKE is rst registered low (and tANPD before that) may not be provided. tANPD is equal to (WL-1) and is counted backwards from PDE. ODT timing for power down entry with ODT buffer disable mode diff_CK CK E tDODT off+1 tCP DE Dmi n ODT Floating tA DCmin DRA M_RTT _s ync (DLL enabl ed) RTT _NOM RTT _PA RK DODT Loff DRA M_RTT _as ync (DLL dis abled) tCP DE Dmi n + tA DCmax RTT _NOM RTT _PA RK tA ONA S mi n tCP DE Dmi n + tA OF AS max When exit from power down, along with CKE being registered high, ODT input signal must be re-driven and maintained low un l tXP is met. ODT timing for power down exit with ODT buffer disable mode diff_CK CK E ODT _A (DLL enabl ed) Floating tX P tA DC_max DODT Lon ODT _B (DLL dis abled) RTT _NOM RTT _PARK DRA M_RTT _A tA DC_min Floating tX P DRA M_RTT _B RTT _PARK RTT _NOM tA ONA S mi n tA OFAS max Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 191 ® Long-term Support World Class Quality IS43/46QR16256A ODT Timing Definitions The reference load for ODT mings is di erent than the reference load used for ming measurements. ODT Timing Reference Load VDDQ CK,CK DQ,DM DQS,DQS TDQS,TDQS DUT RTERM=50ȍ VTT = VSSQ VSSQ Timing Reference Point ODT Timing Definitions and Waveforms De ni ons for tADC, tAONAS and tAOFAS are provided in the Table and measurement reference se ngs are provided in the subsequent. The tADC for the Dynamic ODT case and Read Disable ODT cases are represented by tADC of Direct ODT Control case. ODT Timing Definitions Symbol tADC Begin Point DeĮniƟon End Point DeĮniƟon Rising edge of CK, CK de ned by the end point of DODTLoī Extrapolated point at VRTT_NOM Rising edge of CK, CK de ned by the end point of DODTLon Extrapolated point at VSSQ Rising edge of CK - CK de ned by the end point of ODTLcnw Extrapolated point at VRTT_NOM Rising edge of CK - CK de ned by the end point of ODTLcwn4 or ODTLcwn8 Extrapolated point at VSSQ tAONAS Rising edge of CK, CK with ODT being rst registered high Extrapolated point at VSSQ tAOFAS Rising edge of CK, CK with ODT being rst registered low Extrapolated point at VRTT_NOM Reference Settings for ODT Timing Measurements Measured Parameter RTT_PARK RTT_NOM RTT_WR Vsw1 Vsw2 Note Disable RZQ/7 – 0.20V 0.40V 1,2 1,3 tADC – RZQ/7 Hi-Z 0.20V 0.40V tAONAS Disable RZQ/7 – 0.20V 0.40V tAOFAS Disable RZQ/7 – 0.20V 0.40V 1,2 NOTE 1 MR se ng is as follows. - MR1 A10=1, A9=1, A8=1 (RTT_NOM_Se ng) - MR5 A8=0 , A7=0, A6=0 (RTT_PARK Se ng) - MR2 A11=0, A10=1, A9=1 (RTT_WR Se ng) NOTE 2 ODT state change is controlled by ODT pin. NOTE 3 ODT state change is controlled by Write Command. Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 192 ® Long-term Support World Class Quality IS43/46QR16256A Definition of tADC at Direct ODT Control DODTLoff Begin point:Rising edge of DODTLon Begin point:Rising edge of CK-CK defined by the CK-CK defined by the end point of DODTLoff end point of DODTLon CK CK tADC tADC VRTT_NOM End point:Extrapolated point at VRTT_NOM DQ,DM DQS,DQS TDQS,TDQS VRTT_NOM Vsw2 Vsw1 End point:Extrapolated VSSQ VSSQ point at VSSQ Definition of tADC at Dynamic ODT Control Begin point: Rising edge of CK - CK defined by the end point of ODTLcnw Begin point: Rising edge of CK - CK defined by the end point of ODTLcwn4 or ODTLcwn8 CK VDD/2 CK tADC tADC VRTT_NOM End point:Extrapolated point at VRTT_NOM DQ,DM DQS,DQS TDQS,TDQS Vsw2 Vsw1 VSSQ Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 VRTT_NOM VSSQ End point:Extrapolated point at VSSQ 193 ® Long-term Support World Class Quality IS43/46QR16256A Definition of tAOFAS and tAONAS Rising edge of CK-CK with ODT being first registered low Rising edge of CK-CK with ODT being first registered high CK CK tAOFAS VRTT_NOM tAONAS End point:Extrapolated point at VRTT_NOM Vsw2 Vsw1 DQ,DM DQS,DQS TDQS,TDQS VSSQ Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 VRTT_NOM VSSQ End point: Extrapolated point at VSSQ 194 ® Long-term Support World Class Quality IS43/46QR16256A Absolute Maximum DC Ratings Absolute Ratings Stresses greater than those listed may cause permanent damage to the device. This is a stress ra ng only, and func onal opera on of the device at these or any other condi ons outside those indicated in the opera onal sec ons of this speci ca on is not implied. Exposure to absolute maximum ra ng condi ons for extended periods may adversely a ect reliability. Symbol VDD VDDQ VPP VIN, VOUT TSTG Parameter Min Max Units NOTE Voltage on VDD pin rela ve to Vss -0.3 1.5 V 1,3 Voltage on VDDQ pin rela ve to Vss -0.3 1.5 V 1,3 Voltage on VPP pin rela ve to Vss -0.3 3.0 V 4 Voltage on any pin except VREFCA rela ve to Vss -0.3 1.5 V 1,3,5 Storage Temperature -55 100 °C 1,2 NOTE 1 Stresses greater than those listed under “Absolute Maximum Ra ngs” may cause permanent damage to the device. This is a stress ra ng only and func onal opera on of the device at these or any other condi ons above those indicated in the opera onal sec ons of this speci ca on is not implied. Exposure to absolute maximum ra ng condi ons for extended periods may a ect reliability NOTE 2 Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement condi ons, please refer to JESD51- 2 standard. NOTE 3 VDD and VDDQ must be within 300 mV of each other at all mes;and VREFCA must be not greater than 0.6 x VDDQ, When VDD and VDDQ are less than 500 mV; VREFCA may be equal to or less than 300 mV NOTE 4 VPP must be equal or greater than VDD/VDDQ at all mes. NOTE 5 Refer to overshoot area above 1.5 V. Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 195 ® Long-term Support World Class Quality IS43/46QR16256A AC and DC Operating Conditions Supply Operating Conditions Recommended Supply Operating Conditions Symbol Parameter VDD Supply Voltage VDDQ Supply Voltage for Output VPP Min. RaƟng Typ. Max. 1.14 1.2 1.14 2.375 Unit NOTE 1.26 V 1,2,3 1.2 1.26 V 1,2,3 2.5 2.75 V 3 NOTE 1 Under all condi ons VDDQ must be less than or equal to VDD. NOTE 2 VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ ed together. NOTE 3 The DC bandwidth is limited to 20MHz Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 196 ® Long-term Support World Class Quality IS43/46QR16256A AC and DC Single-Ended Input Measurement Levels (RESET) RESET Input Levels (CMOS) Symbol Parameter Min Max Unit NOTE VIH(AC)_RESET AC Input High Voltage 0.8 x VDD VDD V 6 VIH(DC)_RESET DC Input High Voltage 0.7 x VDD VDD V 2 VIL(DC)_RESET DC Input Low Voltage VSS 0.3 x VDD V 1 VIL(AC)_RESET AC Input Low Voltage VSS 0.2 x VDD V 7 TR_RESET Rising me – 1.0 s 4 tPW_RESET RESET pulse width 1.0 – s 3,5 NOTE 1 A er RESET is registered LOW, RESET level shall be maintained below VIL(DC)_RESET during tPW_RESET, otherwise, the DRAM may not be reset. NOTE 2 Once RESET is registered HIGH, RESET level must be maintained above VIH(DC)_RESET, otherwise, opera on will be uncertain un l it is reset by asser ng RESET signal LOW. NOTE 3 RESET is destruc ve to data contents NOTE 4 No slope reversal(ringback) requirement during its level transi on from Low to High. NOTE 5 This de ni on is applied only “Reset Procedure at Power Stable”. NOTE 6 Overshoot might occur. It should be limited by the Absolute Maximum DC Ra ngs. NOTE 7 Undershoot might occur. It should be limited by Absolute Maximum DC Ra ngs. CT Type-D Input Slew Rate Definition tPW_RESET tR_RESET Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 197 ® Long-term Support World Class Quality IS43/46QR16256A Command/Address Input Levels Command and Address Input Levels: DDR4-2133 through DDR4-2400 DDR4-2133/2400 Min Max Symbol Parameter VIH.CA(DC75) DC input logic high VREFCA + 0.075 VDD V VIL.CA(DC75) DC input logic low VSS VREFCA - 0.075 V VIH.CA(AC100) AC input logic high VREFCA + 0.1 NOTE 2 V 1 AC input logic low NOTE 2 VREFCA - 0.1 V 1 Reference Voltage for ADD, CMD inputs 0.49 x VDD 0.51 x VDD V 2,3 VIL.CA(AC100) VREFCA(DC) Unit NOTE NOTE 1 Refer to “Overshoot and Undershoot Speci ca ons”. NOTE 2 The ac peak noise on VREF may not allow VREF to deviate from VREFCA(DC) by more than ±1% VDD (for reference: approx. ± 12 mV). NOTE 3 For reference : approx. VDD/2 ± 12mV. Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 198 IS43/46QR16256A ® Long-term Support World Class Quality AC and DC Input Measurement Levels: VREF Tolerances VREFCA is to be supplied to the DRAM and equal to V DD/2. The VREFCA is a reference supply input and therefore does not draw biasing current. The DC-tolerance limits and AC-noise limits for the reference voltages VREFCA are illustrated in gure below. The gure shows a valid reference voltage VRef(t) as a func on of me (VRef stands for V REFCA). VRef (DC) is the linear average of VRef(t) over a very long period of me (e.g., 1 sec). This average has to meet the min/max requirements. Furthermore VRef(t) may temporarily deviate from VRef(DC) by no more than +/- 1% VDD for the AC-noise limit. VREFDQ Voltage Range The voltage levels for setup and hold me measurements are dependent on VRef. “VRef ” shall be understood as VRef(DC), as de ned in above gure. This clari es that DC-varia ons of VRef a ect the absolute voltage a signal has to reach to achieve a valid high or low level and therefore the me to which setup and hold is measured. System ming and voltage budgets need to account for VRef(DC) devia ons from the op mum posi on within the data-eye of the input signals. This also clari es that the DRAM setup/hold speci ca on and dera ng values need to include me and voltage associated with VRef AC-noise. Timing and voltage e ects due to AC-noise on VRef up to the speci ed limit (+/-1% of VDD) are included in DRAM mings and their associated dera ngs. Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 199 ® Long-term Support World Class Quality IS43/46QR16256A Data Receiver Input Requirements The Write Timing sec on "Data Strobe to Data Rela onship" details the Data receiver Rx mask opera on to which the following parameters are applicable for. The gure below de nes the measurement points for the Rx mask input slew rates, applicable on a per input basis. DQ TdIPW and SRIN_dIVW definitions. NOTE 1 SRIN_dIVW=VdIVW_Total/(tr or ), signal must be monotonic within tr and range. DQ Input Receiver Specifications Symbol Parameter DDR4-2133 DDR4-2400 Unit NOTE mV 1,2,4,6 130 mV 1,5,13 – 0.2 12 UI 1,2,4,6 0.2 – 0.2 UI 1,5, 13 – 160 – mV 7 Min. Max. – 136 – 136 TdIVW_total Rx ming window total – 0.2 TdIVW_dj Rx determinis c ming – VIHL_AC DQ AC input swing pk-pk 186 VdIVW_total Rx Mask voltage - p-p total VdIVW_dV Rx Mask voltage determinis c 12 12 Min. Max. – 130 – 12 TdIPW DQ input pulse width 0.58 – 0.58 – UI 8 tDQS2DQS tDQ2DQ DQS-to-DQ Rx Mask O set -0.17 0.17 -0.17 0.17 UI 9 DQ-to-DQ Rx Mask O set – 0.1 – 0.1 UI 10 Input Slew Rate over VdIVW_total 1 9 1.25 9 V/ns 11 SRIN_dIVW NOTE 1 Data Rx mask voltage and ming total input valid window where VdIVW is centered around Vcent_DQ(pin avg). The data Rx mask is applied per bit and should include voltage and temperature dri terms. The design speci ca on is BER 4.0 4.0 3.0 2.0 1.8 1.6 1.4 1.2 1.0 < 1.0 120 115 110 105 100 95 90 85 80 80 NOTE 1 Below VIL(AC) Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 206 ® Long-term Support World Class Quality IS43/46QR16256A Single-ended requirements for CK differential signals Each individual component of a di eren al signal (CK, CK) has also to comply with certain requirements for single-ended signals. CK and CK have to reach approximately VSEHmin / VSELmax , approximately equal to the ac-levels V IH(AC) and VIL(AC) for ADD/CMD signals in every half-cycle. The applicable ac-levels for ADD/CMD might be di erent per speed-bin etc. e.g., if a value other than 100mV is used for ADD/CMD VIH(AC) and VIL(AC) signals, then these ac-levels apply also for the single-ended signals CK and CK. While ADD/CMD signal requirements are with respect to VREFCA, the single-ended components of di eren al signals have a requirement with respect to VDD / 2; this is nominally the same. The transi on of single-ended signals through the ac-levels is used to measure setup me. For single-ended components of di eren al signals the requirement to reach VSELmax, VSEHmin has no bearing on ming, but adds a restric on on the common mode characteris cs of these signals. Single-ended requirement for CK VDD or VDDQ VSEHmin VSEH VDD/2 or VDDQ/2 CK VSELmax VSEL VSS or VSSQ time Single-Ended Requirements for CK Symbol DDR4-2133/2400 Min Max Parameter Unit NOTE VSEH Single-ended high-level for CK , CK (VDD/2)+0.100 NOTE 3 V 1,2 VSEL Single-ended low-level for CK , CK NOTE 3 (VDD/2)-0.100 V 1,2 NOTE 1 For CK - CK use VIH(AC) and VIL(AC) of ADD/CMD and VREFCA. NOTE 2 ADDR/CMD VIH(AC) and VIL(AC) based on VREFCA. NOTE 3 These values are not de ned; however, the di eren al signals (CK, CK) need to be within the respec ve limits, VIH(DC) max and VIL(DC) min for single-ended signals as well as the limita ons for overshoot and undershoot. Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 207 ® Long-term Support World Class Quality IS43/46QR16256A Slew Rate Definitions for CK Differential Input Signals CK Differential Input Slew Rate Definition DescripƟon Measured from to DeĮned by Di eren al input slew rate for rising edge(CK - CK) VIL,diī,max VIH,diī,min [ VIH,di ,min – VIL,di ,max ] / TRdi Di eren al input slew rate for falling edge(CK - CK) VIH,diī,min VIL,diī,max [ VIH,di ,min – VIL,di ,max ] / TFdi NOTE 1 The di eren al signal CK - CK must be monotonic between these thresholds. Differential Input Slew Rate Definition for CK, CK Differential Input Voltage(i,e, CK - CK ) Delta TRdiff VIHdiff,min 0 VILdiff,max Delta TFdiff Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 208 ® Long-term Support World Class Quality IS43/46QR16256A CK Differential Input Cross Point Voltage To guarantee ght setup and hold mes as well as output skew parameters with respect to clock and strobe, each cross point voltage of di eren al input signal CK, CK must meet the requirements shown below. The di eren al input cross point voltage VIX(CK) is measured from the actual cross point of true and complement signals to the midlevel between VDD and VSS. VIX(CK) Definition VDD CK Vix VDD/2 Vix CK VSEH VSEL VSS Cross Point Voltage For CK Differential Input Signals Symbol – Area of VSEH, VSEL VlX(CK) DDR4-2133 Parameter Di eren al Input Cross Point Voltage rela ve to VDD/2 for CK, CK Min Max VSEL” VDD/2 - 145 mV VDD/2 - 145 mV ” VSEL” VDD/2 - 100 mV VDD/2 + 100 mV ” VSEH” VDD/2 + 145 mV VDD/2 + 145 mV ” VSEH -120 mV - ( VDD/2 - VSEL ) + 25 mV ( VSEH - VDD/2 ) - 25 mV 120 mV NOTE 1 Extended range for VIX(CK) is only allowed if single-ended clock input signals CK and CK are monotonic with a single-ended swing VSEL/VSEH of at least VDD/2 ±250mV, and when the di eren al slew rate of CK - CK is larger than 4V/ns. NOTE 2 The rela on between Vix(CK) Min/Max and VSEL/VSEH should sa sfy following: (VDD/2) + VIX(CK) Min) - VSEL 25mV VSEH - ((VDD/2) + IX(CK) Max) 25mV Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 209 ® Long-term Support World Class Quality IS43/46QR16256A Slew Rate Definitions for DQS Differential Input Signals Measured from to DescripƟon DeĮned by Di eren al input slew rate for rising edge(DQS - DQS) VILDiī_DQS VIHDiī_DQS |VILDi _DQS - VIHDi _DQS | Di eren al input slew rate for falling edge(DQS - DQS) VIHDiī_DQS VILDiī_DQS |VILDi _DQS - VIHDi _DQS | / TRdi / TFdi NOTE 1 The di eren al signal DQS - DQS must be monotonic between these thresholds. Differential Input Slew Rate and Input Level Definition for DQS - DQS Differential Input Slew Rate and Input Levels for DQS - DQS Symbol Parameter DDR4-2133 Min Max DDR4-2400 Min Max Unit VIHDiī_DQS Di ern al Input High 136 – 130 – mV VILDiī_DQS Di ern al Input Low – –136 – -130 mV VIHDiīPeak VIH.DIFF.Peak Voltage 186 VDDQ 160 VDDQ mV VILDiīPeak VIL.DIFF.Peak Voltage VSSQ –186 VSSQ -160 mV 3 18 3 18 V/ns SRIdiī Di eren al Intput Slew Rate Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 210 ® Long-term Support World Class Quality IS43/46QR16256A DQS Differential Input Cross Point Voltage To guarantee ght setup and hold mes as well as output skew parameters with respect to clock and strobe, each cross point voltage of di eren al input signal DQS, DQS must meet the requirements shown below. The di eren al input cross point voltage VIX(DQS) is measured from the actual cross point of true and complement signals to the midlevel between VDD and VSS. VIX(DQS) Definition Cross Point Voltage For Differential Input Signals DQS Symbol Parameter Vix_DQS_raƟo DQS Di eren al input crosspoint voltage ra o DDR4-2133/2400 Min. Max. – 25 Unit NOTE % 1,2,3 NOTE 1 The base level of Vix_DQS_FR/RF is VREFDQ that is the internal se ng value that was determined by VREF Training. NOTE 2 MIN(f(t)) = VIL_DIFF_Peak. NOTE 3 MAX(f(t))= VIH_DIFF_Peak. NOTE 4 Vix_DQS_FR = MIN(f(t)) x VIX_DQS_ra o. NOTE 5 Vix_DQS_RF = MAX(f(t)) x VIX_DQS_ra o. Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 211 ® Long-term Support World Class Quality IS43/46QR16256A Overshoot and Undershoot Specifications Address, Command, and Control Overshoot and Undershoot Specifications SpeciĮcaƟon DDR4-2133 DDR4-2400 Parameter Unit Address and control pins ( A0-A13,A17,BG[1:0],BA[1:0],ACT ,RAS/A16,CAS /A15,WE/A14,CS,CKE,ODT) Maximum peak amplitude above VDD Absolute Max allowed for overshoot area Delta value between VDD Absolute Max and VDD Max allowed for overshoot area 0.06 0.06 V 0.24 0.24 V Maximum peak amplitude allowed for undershoot area 0.3 0.3 V/ns Maximum overshoot area per 1tCK Above Absolute Max 0.0062 0.0055 V/ns Maximum overshoot area per 1tCK Between Absolute Max and VDD Max 0.1914 0.1699 V/ns Maximum undershoot area per 1tCK Below VSS 0.1984 0.1762 V/ns ADDR, CMD, CNTL Overshoot and Undershoot Definition Overshoot Area above VDD Absolute Max VDD Absolute Max Volts VDD (V) Overshoot_ Area Between VDD Absolute Max and VDD Max 1 tCK VSS Undershoot_ Area below VSS Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 212 ® Long-term Support World Class Quality IS43/46QR16256A Clock Overshoot and Undershoot Specifications SpeciĮcaƟon DDR4-2133 DDR4-2400 Parameter Unit Clock (CK, CK) Maximum peak amplitude above VDD Absolute Max allowed for overshoot area Delta value between VDD Absolute Max and VDD Max allowed for overshoot area 0.06 0.06 V 0.24 0.24 V Maximum peak amplitude allowed for undershoot area 0.3 0.3 V/ns Maximum overshoot area per 1UI Above Absolute Max 0.0028 0.0025 V/ns Maximum overshoot area per 1UI Between Absolute Max and VDD Max 0.0844 0.0750 V/ns Maximum undershoot area per 1UI Below VSS 0.0858 0.0762 V/ns CK Overshoot and Undershoot Definition Overshoot_Area above VDD Absolute Max VDD Absolute Max Volts (V) Overshoot_Area Between VDD Absolute Max and VDD Max VDD 1UI VSS Undershoot_Area below VSS Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 213 ® Long-term Support World Class Quality IS43/46QR16256A Data, Strobe, and Mask Overshoot and Undershoot Specifications Parameter DDR4-2133 DDR4-2400 Unit Data, Strobe and Mask (DQ, DQS, DQS, DM, DBI, TDQS, TDQS) Maximum peak amplitude above Max absolute level of Vin,Vout 0.16 0.16 V Overshoot area Between Max Absolute level of Vin,Vout and VDDQ Max 0.24 0.24 V Undershoot area Between Min absolute level of Vin,Vout and VSSQ 0.30 0.30 V Maximum peak amplitude below Min absolute level of Vin,Vout 0.10 0.10 V 0.0113 0.0100 V/ns 0.0788 0.0700 V/ns 0.0788 0.0700 V/ns 0.0113 0.0100 V/ns Maximum overshoot area per 1UI Above Max absolute level of Vin,Vout Maximum overshoot area per 1UI Between Max absolute level of Vin,Vout and VDDQ Max Maximum undershoot area per 1UI Between Min absolute level of Vin,Vout and VSSQ Maximum undershoot area per 1UI Below Min absolute level of Vin,Vout Data, Strobe, and Mask Overshoot and Undershoot Definition Overshoot area above Max absolute level of Vin,Vout Max absolute level of Vin,Vout Overshoot area Between Max absolute level of Vin,Vout and VDDQ Max VDDQ Volts (V) 1UI VSSQ Min absolute level of Vin,Vout Undershoot area Between Min absolute level of Vin,Vout and VSSQ Undershoot area below Min absolute level of Vin,Vout Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 214 ® Long-term Support World Class Quality IS43/46QR16256A AC and DC Output Measuremnt Levels Output Driver DC Electrical Characteristics The DDR4 driver supports two Ron values. These Ron values are referred as strong mode (low Ron - 34 ) and weak mode (high Ron - 48 ). A func onal representa on of the output bu er is shown in the gure below. Chip In Drive Mode Output Drive VDDQ IPu To other circuity like RCV, ... RONPu DQ RONPd Iout Vout I Pd VSSQ The output driver impedance, RON, is determined by the value of the external reference resistor RZQ as follows: RON(34) = RZQ/7, or RON(48) = RZQ/5 . This provides either a nominal 34.3 ±10% or 48 ±10% with nominal RZQ = 240 RONPu = RONPd = VDDQ - Vout | Iout | Vout | Iout | under the condi on that RON Pd is o under the condi on that RON Pu is o Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 215 ® Long-term Support World Class Quality IS43/46QR16256A ALERT Output Drive Characteristic Output driver impedance RON is de ned as follows: Alert Driver DRAM Alert RONPd Iout I Pd Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 Vout VSSQ 216 ® Long-term Support World Class Quality IS43/46QR16256A Output Driver Characteristic of Connectivity Test (CT) Mode Following Output driver impedance RON will be applied Test Output Pin during Connec vity Test (CT) Mode. The individual pull-up and pull-down resistors (RONPu_CT and RONPd_CT) are de ned as follows: RONPu_CT = VDDQ -VOUT VOUT RONPd_C = l Iout l l Iout l Chip In Drive Mode Output Driver VDDQ IPu_CT To other circuity like RCV,... RON Pu_CT Iout DQ RON Pd_CT Vout IPd_CT VSSQ Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 217 ® Long-term Support World Class Quality IS43/46QR16256A Single-Ended AC & DC Output Levels Symbol Parameter DDR4-2133/2400 VOH(DC) DC output high measurement level VOM(DC) DC output mid measurement level VOL(DC) DC output low measurement level VOH(AC) AC output high measurement level VOL(AC) AC output low measurement level For IV curve linearity For output SR Units 1.1 x VDDQ V 0.8 x VDDQ V NOTE 0.5 x VDDQ V (0.7 + 0.15) x VDDQ V 1 (0.7 - 0.15) x VDDQ V 1 NOTE 1 The swing of ± 0.15 × VDDQ is based on approximately 50% of the sta c single-ended output peak-to-peak swing with a driver impedance of RZQ/7 and an e ec ve test load of 50 to VTT = VDDQ. Using the same reference load used for ming measurements, output slew rate for falling and rising edges is de ned and measured between VOL(AC) and VOH(AC) for single ended signals. Single-Ended Output Slew Rate Definition Measured from to DescripƟon DeĮned by Single ended output slew rate for rising edge VOL(AC) VOH(AC) [VOH(AC)-VOL(AC)] / TRse Single ended output slew rate for falling edge VOH(AC) VOL(AC) [VOH(AC)-VOL(AC)] / TFse VOH(AC) VTT VOL(AC) delta TFse delta TRse Single-Ended Output Slew Rate Symbol Parameter SRQse Single ended output slew rate DDR4-2133 DDR4-2400 Min Max Min Max 4 9 4 9 Unit V/ns For RON = RZQ/7 NOTE 1 SR = slew rate; Q = query output; se = single-ended signals NOTE 2 In two cases a maximum slew rate of 12V/ns applies for a single DQ signal within a byte lane. Case 1 is de ned for a single DQ signal within a byte lane that is switching into a certain direc on (either from high-to-low or low-to-high) while all remaining DQ signals in the same byte lane are sta c (they stay at either high or low). Case 2 is de ned for a single DQ signal within a byte lane that is switching into a certain direc on (either from high to low or low to high) while all remaining DQ signals in the same byte lane are switching into the opposite direc on (from low to high or high to low respec vely). For the remaining DQ signal switching into the opposite direc on, the regular maximum limit of 9 V/ns applies. Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 218 ® Long-term Support World Class Quality IS43/46QR16256A Differential Outputs Symbol Parameter DDR4-2133/2400 Units VOHdiī(AC) AC di eren al output high measurement level (for output SR) +0.3 x VDDQ V VOLdiī(AC) -0.3 x VDDQ V AC di eren al output low measurement level (for output SR) NOTE 1 The swing of ± 0.3 × VDDQ is based on approximately 50% of the sta c single-ended output peak-to-peak swing with a driver impedance of RZQ/7 and an e ec ve test load of 50 to VTT = VDDQ at each di eren al output. NOTE 2 Using the same reference load used for ming measurements, output slew rate for falling and rising edges is de ned and measured between VOL,di (AC) and VOH,di (AC) for di eren al signals. Differential Output Slew Rate Definition Measured from to DescripƟon Di eren al output slew rate for rising edge VOLdiī(AC) VOHdiī(AC) Di eren al output slew rate for falling edge VOHdiī(AC) VOLdiī(AC) DeĮned by [VOH,di (AC)-VOL,di (AC)] / TRdi [VOH,di (AC)-VOL,di (AC)] / TFdi V OHdiff (AC) VTT VOLdiff (AC) delta TRdiff delta TFdiff Differential Output Slew Rate For RON = RZQ/7 Symbol Parameter SRQdiī Di eren al output slew rate DDR4-2133 Min Max 8 18 DDR4-2400 Min Max 8 18 Unit V/ns NOTE 1 SR = slew rate; Q = query output; se = single-ended signals Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 219 ® Long-term Support World Class Quality IS43/46QR16256A Connectivity Test Mode Output Levels Symbol Parameter DDR4-2133/2400 VOH(DC) DC output high measurement level VOM(DC) DC output mid measurement level VOL(DC) DC output low measurement level VOB(DC) DC output below measurement level VOH(AC) AC output high measurement level For output AC output below measurement level SR VOL(AC) Units NOTE 1.1 x VDDQ V 0.8 x VDDQ V 0.5 x VDDQ V 0.2 x VDDQ V VTT + (0.1 x VDDQ) V 1 VTT - (0.1 x VDDQ) V 1 For IV curve linearity NOTE 1 Driver impedance of RZQ/7 and an e ec ve test load of 50 to VTT = VDDQ. Test Load for Connectivity Test Mode Timing VDDQ CT_Inputs DUT DQ, DQS, DQS, DM, TDQS, TDQS 0.5 * VDDQ RTERM = 50 ȍ VSSQ Timing reference point DDR4-2133/ 2400 Min Symbol Parameter TF_output_CT Output signal Falling me – 10 ns/V TR_output_CT Output signal Rising me – 10 ns/V Integrated Silicon Solution, Inc. — www.issi.com Rev. A 05/05/2017 Max Unit 220 ® Long-term Support World Class Quality IS43/46QR16256A Speed Bin DDR4-2133 Speed Bins and Operating Conditions Speed Bin DDR4-2133P CL-nRCD-nRP 15-15-15 Parameter Unit Notes Symbol Min Max tAA 14.0614 18.00 ns 12 tAA_DBI tAA(min) + 3nCK tAA(max) +3nCK ns 12 tRCD 14.06 – ns 12 PRE command period tRP 14.06 – ns 12 ACT to PRE command period tRAS 33 9 x tREFI ns 12 ACT to ACT or REF command period tRC 47.06 – ns 12 1.6 ns 1,2,3,4,11,14 Internal read command to rst data Internal read command to rst data with read DBI enabled ACT to internal read or write delay me CWL = 9 CWL = 9,11 CWL = 10,12 CWL = 11,14 Normal Read DBI CL = 9 CL = 11 (Op onal)5 tCK(AVG) CL = 10 CL = 12 tCK(AVG) CL = 11 CL = 13 tCK(AVG) CL = 12 CL = 14 tCK(AVG) CL = 13 CL = 15 tCK(AVG) 1.5 (Op onal)5,12 Reserved 1.25