IS43TR81024BL-125KBLI

IS43/46TR16512B, IS43/46TR16512BL, IS43/46TR81024B, IS43/46TR81024BL 1Gx8, 512Mx16 8Gb DDR3 SDRAM JUNE 2021 FEATURES  Standard Voltage: VDD and VDDQ = 1.5V ± 0.075V  Low Voltage (L): VDD and VDDQ = 1.35V + 0.1V, -0.067V - Backward compatible to 1.5V  High speed data transfer rates with system frequency up to 933 MHz  8 internal banks for concurrent operation  8n-Bit pre-fetch architecture  Programmable CAS Latency  Programmable Additive Latency: 0, CL-1,CL-2  Programmable CAS WRITE latency (CWL) based on tCK  Programmable Burst Length: 4 and 8  Programmable Burst Sequence: Sequential or Interleave  BL switch on the fly  Auto Self Refresh(ASR)  Self Refresh Temperature(SRT) OPTIONS  Configuration: 1Gx8 512Mx16  Package: 96-ball BGA (10mm x 14mm) for x16 78-ball BGA (10mm x 14mm) for x8  Refresh Interval: 7.8 µs (8192 cycles/64 ms) Tc= -40°C to 85°C 3.9 µs (8192 cycles/32 ms) Tc= 85°C to 95°C 1.95 µs (8192 cycles/16 ms) Tc= 95°C to 105°C 0.97 µs (8192 cycles/8 ms) Tc= 105°C to 115°C          Partial Array Self Refresh Asynchronous RESET pin TDQS (Termination Data Strobe) supported (x8 only) OCD (Off-Chip Driver Impedance Adjustment) Dynamic ODT (On-Die Termination) Driver strength : RZQ/7, RZQ/6 (RZQ = 240 Ω) Write Leveling Up to 200 MHz in DLL off mode Operating temperature: Commercial (TC = 0°C to +95°C) Industrial (TC = -40°C to +95°C) Automotive, A1 (TC = -40°C to +95°C) Automotive, A2 (TC = -40°C to +105°C) Automotive, A25 (TC = -40°C to +115°C) ADDRESS TABLE Parameter Row Addressing Column Addressing Bank Addressing Page size Auto Precharge Addressing BL switch on the fly 1Gx8 A0-A15 A0-A9, A11 BA0-2 2KB 512Mx16 A0-A15 A0-A9 BA0-2 2KB A10/AP A10/AP A12/BC# A12/BC# SPEED BIN Speed Option 125K 107M 093N JEDEC Speed Grade DDR3-1600K DDR3-1866M DDR3-2133N CL-nRCD-nRP tRCD,tRP(min) 11-11-11 13.75 13-13-13 13.91 14-14-14 13.09 Units tCK ns Note: Faster speed options are backward compatible to slower speed options. Copyright © 2021 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc. – www.issi.com – Rev. B1 06/25/2021 1 IS43/46TR16512B, IS43/46TR16512BL, IS43/46TR81024B, IS43/46TR81024BL 1. DDR3 PACKAGE BALLOUT 1.1 DDR3 SDRAM package ballout 78-ball BGA – x8 A B C D E F G H J K L M N 1 VSS VSS VDDQ VSSQ VREFDQ NC1 ODT NC VSS VDD VSS VDD VSS 2 VDD VSSQ DQ2 DQ6 VDDQ VSS VDD CS# BA0 A3 A5 A7 RESET# 3 NC DQ0 DQS DQS# DQ4 RAS# CAS# WE# BA2 A0 A2 A9 A13 4 5 6 7 NU/TDQS# DM/TDQS DQ1 VDD DQ7 CK CK# A10/AP A15 A12/BC# A1 A11 A14 8 VSS VSSQ DQ3 VSS DQ5 VSS VDD ZQ VREFCA BA1 A4 A6 A8 9 VDD VDDQ VSSQ VSSQ VDDQ NC CKE NC VSS VDD VSS VDD VSS Note: NC balls have no internal connection. Integrated Silicon Solution, Inc. – www.issi.com – Rev. B1 06/25/2021 2 IS43/46TR16512B, IS43/46TR16512BL, IS43/46TR81024B, IS43/46TR81024BL 1.2 DDR3 SDRAM package ballout 96-ball BGA – x16 A B C D E F G H J K L M N P R T 1 VDDQ VSSQ VDDQ VSSQ VSS VDDQ VSSQ VREFDQ NC ODT NC VSS VDD VSS VDD VSS 2 DQU5 VDD DQU3 VDDQ VSSQ DQL2 DQL6 VDDQ VSS VDD CS# BA0 A3 A5 A7 RESET# 3 DQU7 VSS DQU1 DMU DQL0 DQSL DQSL# DQL4 RAS# CAS# WE# BA2 A0 A2 A9 A13 4 5 6 7 DQU4 DQSU# DQSU DQU0 DML DQL1 VDD DQL7 CK CK# A10/AP A15 A12/BC# A1 A11 A14 8 VDDQ DQU6 DQU2 VSSQ VSSQ DQL3 VSS DQL5 VSS VDD ZQ VREFCA BA1 A4 A6 A8 9 VSS VSSQ VDDQ VDD VDDQ VSSQ VSSQ VDDQ NC CKE NC VSS VDD VSS VDD VSS Note: NC balls have no internal connection. Integrated Silicon Solution, Inc. – www.issi.com – Rev. B1 06/25/2021 3 IS43/46TR16512B, IS43/46TR16512BL, IS43/46TR81024B, IS43/46TR81024BL 1.3 Pinout Description - JEDEC Standard Symbol Type Function CK, CK# Input CKE Input CS# Input ODT Input RAS#. CAS#. WE# DM, (DMU), (DML) Input Clock: CK and CK# are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK#. Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and device input buffers and output drivers. Taking CKE Low provides Precharge Power-Down and Self-Refresh operation (all banks idle), or Active Power-Down (row Active in any bank). CKE is asynchronous for Self-Refresh exit. After VREFCA and VREFDQ have become stable during the power on and initialization sequence, they must be maintained during all operations (including Self-Refresh). CKE must be maintained high throughout read and write accesses. Input buffers, excluding CK, CK#, ODT and CKE, are disabled during power-down. Input buffers, excluding CKE, are disabled during Self-Refresh. Chip Select: All commands are masked when CS# is registered HIGH. CS# provides for external Rank selection on systems with multiple Ranks. CS# is considered part of the command code. On Die Termination: ODT (registered HIGH) enables termination resistance internal to the DDR3 SDRAM. When enabled, ODT is only applied to each DQ, DQSU, DQSU#, DQSL, DQSL#, DMU, and DML signal. The ODT pin will be ignored if MR1 and MR2 are programmed to disable RTT. Command Inputs: RAS#, CAS# and WE# (along with CS#) define the command being entered. BA0 - BA2 Input A0 - A15 Input A10 / AP Input A12 / BC# Input RESET# Input DQ( DQL, DQU) Input / Output Input / Output DQS, DQS#, DQSU, DQSU#, DQSL, DQSL# TDQS, TDQS# Input Output Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH coincident with that input data during a Write access. DM is sampled on both edges of DQS. For x8 device, the function of DM or TDQS/TDQS# is enabled by Mode Register A11 setting in MR1. Bank Address Inputs: BA0 - BA2 define to which bank an Active, Read, Write, or Precharge command is being applied. Bank address also determines which mode register is to be accessed during a MRS cycle. Address Inputs: Provide the row address for Active commands and the column address for Read/ Write commands to select one location out of the memory array in the respective bank. (A10/AP and A12/BC# have additional functions; see below). The address inputs also provide the op-code during Mode Register Set commands. Auto-precharge: A10 is sampled during Read/Write commands to determine whether Autoprecharge should be performed to the accessed bank after the Read/Write operation. (HIGH: Autoprecharge; LOW: no Autoprecharge). A10 is sampled during a Precharge command to determine whether the Precharge applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by bank addresses. Burst Chop: A12 / BC# is sampled during Read and Write commands to determine if burst chop (on-the-fly) will be performed. (HIGH, no burst chop; LOW: burst chopped). See command truth table for details. Active Low Asynchronous Reset: Reset is active when RESET# is LOW, and inactive when RESET# is HIGH. RESET# must be HIGH during normal operation. RESET# is a CMOS railto-rail signal with DC high and low at 80% and 20% of VDD, i.e., 1.20V for DC high and 0.30V for DC low. Data Input/ Output: Bi-directional data bus. Data Strobe: output with read data, input with write data. Edge-aligned with read data, centered in write data. For the x16, DQSL corresponds to the data on DQL0-DQL7; DQSU corresponds to the data on DQU0-DQU7. The data strobes DQS, DQSL, and DQSU are paired with differential signals DQS#, DQSL#, and DQSU#, respectively, to provide differential pair signaling to the system during reads and writes. DDR3 SDRAM supports differential data strobe only and does not support single-ended. Termination Data Strobe: TDQS/TDQS# is applicable for x8 DRAMs only. When enabled via Mode Register A11 = 1 in MR1, the DRAM will enable the same termination resistance function on TDQS/TDQS# that is applied to DQS/DQS#. When disabled via mode register A11 = 0 in MR1, DM/TDQS will provide the data mask function and TDQS# is not used. x16 DRAMs must disable the TDQS function via mode register A11 = 0 in MR1. Integrated Silicon Solution, Inc. – www.issi.com – Rev. B1 06/25/2021 4 IS43/46TR16512B, IS43/46TR16512BL, IS43/46TR81024B, IS43/46TR81024BL NC No Connect: No internal electrical connection is present. VDDQ Supply VSSQ Supply DQ Power Supply: 1.5 V +/- 0.075 V for standard voltage or 1.35V +0.1V, -0.067V for low voltage DQ Ground VDD Supply Power Supply: 1.5 V +/- 0.075 V for standard voltage or 1.35V +0.1V, -0.067V for low voltage VSS Supply Ground VREFDQ Supply Reference voltage for DQ VREFCA Supply Reference voltage for CA ZQ Supply Reference Pin for ZQ Note: Input only pins (BA0-BA2, A0-A15, RAS#, CAS#, WE#, CS#, CKE, ODT, and RESET#) do not supply termination. Integrated Silicon Solution, Inc. – www.issi.com – Rev. B1 06/25/2021 5 IS43/46TR16512B, IS43/46TR16512BL, IS43/46TR81024B, IS43/46TR81024BL 2. FUNCTION DESCRIPTION 2.1 Simplified State Diagram Power applied Power On Reset Procedure MRS,MPR, Write Leveling Initialization Self Refresh SRE ZQCL From Any state RESET ZQCL ZQCS ZQ Calibration SRX REF Idle Refreshing PDE ACT PDX Active Power Down Precharge Power Down Activating PDX PDE Write Write Bank Active Write A Writing Write Read Read A Read Write A Read Reading Read A Write A Read A PRE,PREA PRE,PREA PRE,PREA Writing Reading Precharging Automatic Sequence Command Sequence Abbreviation Function Abbreviation Function Abbreviation Function ACT Active Read RD, RDS4, RDS8 PDE Enter Power-down PRE Precharge Read A RDA, RDAS4, RDAS8 PDX Exit Power-down PREA Precharge All Write WR, WRS4, WRS8 SRE Self-Refresh entry MRS Mode Register Set Write A WRA, WRAS4, WRAS8 SRX REF Refresh Start RESET Procedure MPR Self-Refresh exit Multi-Purpose Register ZQCL ZQ Calibration Long RESET ZQCS Integrated Silicon Solution, Inc. – www.issi.com – Rev. B1 06/25/2021 ZQ Calibration Short 6 IS43/46TR16512B, IS43/46TR16512BL, IS43/46TR81024B, IS43/46TR81024BL 2.2 RESET and Initialization Procedure 2.2.1 Power-up Initialization Sequence The following sequence is required for POWER UP and Initialization. 1. Apply power (RESET# is recommended to be maintained below 0.2 x VDD; all other inputs may be undefined). RESET# needs to be maintained for minimum 200 us with stable power. CKE is pulled “Low” anytime before RESET# being de-asserted (min. time 10 ns). The power voltage ramp time between 300mV to VDD(min) must be no greater than 200 ms; and during the ramp, VDD > VDDQ and (VDD - VDDQ) < 0.3 volts.    VDD and VDDQ are driven from a single power converter output, AND The voltage levels on all pins other than VDD, VDDQ, VSS, VSSQ must be less than or equal to VDDQ and VDD on one side and must be larger than or equal to VSSQ and VSS on the other side. In addition, VTT is limited to 0.95 V max once power ramp is finished, AND Vref tracks VDDQ/2. OR    Apply VDD without any slope reversal before or at the same time as VDDQ. Apply VDDQ without any slope reversal before or at the same time as VTT & Vref. The voltage levels on all pins other than VDD, VDDQ, VSS, VSSQ must be less than or equal to VDDQ and VDD on one side and must be larger than or equal to VSSQ and VSS on the other side. 2. After RESET# is de-asserted, wait for another 500 us until CKE becomes active. During this time, the DRAM will start internal state initialization; this will be done independently of external clocks. 3. Clocks (CK, CK#) need to be started and stabilized for at least 10 ns or 5 tCK (which is larger) before CKE goes active. Since CKE is a synchronous signal, the corresponding set up time to clock (tIS) must be met. Also, a NOP or Deselect command must be registered (with tIS set up time to clock) before CKE goes active. Once the CKE is registered “High” after Reset, CKE needs to be continuously registered “High” until the initialization sequence is finished, including expiration of tDLLK and tZQinit. 4. The DDR3 SDRAM keeps its on-die termination in high-impedance state as long as RESET# is asserted. Further, the SDRAM keeps its on-die termination in high impedance state after RESET# deassertion until CKE is registered HIGH. The ODT input signal may be in undefined state until tIS before CKE is registered HIGH. When CKE is registered HIGH, the ODT input signal may be statically held at either LOW or HIGH. If RTT_NOM is to be enabled in MR1, the ODT input signal must be statically held LOW. In all cases, the ODT input signal remains static until the power up initialization sequence is finished, including the expiration of tDLLK and tZQinit. 5. After CKE is being registered high, wait minimum of Reset CKE Exit time, tXPR, before issuing the first MRS command to load mode register. (tXPR=max (tXS ; 5 x tCK) 6. Issue MRS Command to load MR2 with all application settings. (To issue MRS command for MR2, provide “Low” to BA0 and BA2, “High” to BA1.) 7. Issue MRS Command to load MR3 with all application settings. (To issue MRS command for MR3, provide “Low” to BA2, “High” to BA0 and BA1.) 8. Issue MRS Command to load MR1 with all application settings and DLL enabled. (To issue "DLL Enable" command, provide "Low" to A0, "High" to BA0 and "Low" to BA1 – BA2). 9. Issue MRS Command to load MR0 with all application settings and “DLL reset”. (To issue DLL reset command, provide "High" to A8 and "Low" to BA0-2). Integrated Silicon Solution, Inc. – www.issi.com – Rev. B1 06/25/2021 7 IS43/46TR16512B, IS43/46TR16512BL, IS43/46TR81024B, IS43/46TR81024BL 10. Issue ZQCL command to starting ZQ calibration. 11. Wait for both tDLLK and tZQinit completed. 12. The DDR3 SDRAM is now ready for normal operation. Ta CK,CK# Tb (( () () )) Tc Td (( () () )) Te Tf Tg Th Ti Tj Tk (( () () )) (( () () )) (( () () )) (( () () )) (( () () )) (( () () )) (( () () )) tCKSRX VDD,VDDQ RESET# (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) T=200µS T=500µS (( (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( () () )) (( () () )) (( () () )) (( () () )) (( () () )) (( () () )) (( () () )) Valid (( () () )) Valid (( () () )) Valid (( )) )) tIS Tmin=10nS CKE (( () () )) tDLLK tMRD tXPR tMRD tMRD tMOD tZQinit tIS CMMAND (( () () )) (( () () )) BA (( () () )) (( () () )) ODT (( () () )) (( () () )) RTT (( )) (( )) 1) (( () () )) MRD (( () () )) MRD (( () () )) MRD (( () () )) MRD (( () () )) (( () () )) MR2 (( () () )) MR3 (( () () )) MR1 (( () () )) MR0 (( () () )) ZQCL (( () () )) 1) (( () () )) tIS tIS (( () () Static )) (( )) LOW in case RTT_Nom is enabled at time Tg, otherwise static (( )) Note1. From time point “Td” until “Tk” NOP or DES commands must be applied between MRS and ZQCL commands. (( )) (( )) (( () () HIGH )) (( )) (( )) Time Break Figure2.1.1 Reset and Initialization Sequence at Power-on Ramping Integrated Silicon Solution, Inc. – www.issi.com – Rev. B1 06/25/2021 (( )) or LOW (( () () )) Valid (( )) DON’T CARE 8 IS43/46TR16512B, IS43/46TR16512BL, IS43/46TR81024B, IS43/46TR81024BL 2.2.2 Reset Initialization with Stable Power The following sequence is required for RESET at no power interruption initialization. 1. Asserted RESET below 0.2 * VDD anytime when reset is needed (all other inputs may be undefined). RESET needs to be maintained for minimum 100 ns. CKE is pulled “LOW” before RESET being de-asserted (min. time 10 ns). 2. Follow Power-up Initialization Sequence steps 2 to 11. 3. The Reset sequence is now completed; DDR3 SDRAM is ready for normal operation. Ta CK,CK# Tb (( () () )) Tc Td (( () () )) Te Tf Tg Th Ti Tj Tk (( () () )) (( () () )) (( () () )) (( () () )) (( () () )) (( () () )) (( () () )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( () () )) (( () () )) (( () () )) (( () () )) (( () () )) (( () () )) (( () () )) Valid (( () () )) Valid (( () () )) Valid tCKSRX VDD,VDDQ RESET# (( )) (( )) T=100nS T=500µS (( (( )) )) tIS Tmin=10nS CKE (( () () )) tDLLK tMRD tXPR tMRD tMRD tMOD tZQinit tIS CMMAND (( () () )) (( () () )) BA (( () () )) (( () () )) ODT (( () () )) (( () () )) RTT (( )) (( )) 1) (( () () )) MRD (( () () )) MRD (( () () )) MRD (( () () )) MRD (( () () )) (( () () )) MR2 (( () () )) MR3 (( () () )) MR1 (( () () )) MR0 (( () () )) ZQCL (( () () )) 1) (( () () )) tIS tIS (( () () Static )) (( )) LOW in case RTT_Nom is enabled at time Tg, otherwise static (( )) Note1. From time point “Td” until “Tk” NOP or DES commands must be applied between MRS and ZQCL commands. (( )) (( )) (( () () HIGH )) (( )) (( )) Time Break Figure2.1.2 Reset Procedure at Power Stable Condition (( )) or LOW (( () () )) Valid (( )) DON’T CARE 2.3 Register Definition 2.3.1 Programming the Mode Registers For application flexibility, various functions, features, and modes are programmable in four Mode Registers, provided by the DDR3 SDRAM, as user defined variables and they must be programmed via a Mode Register Set (MRS) command. As the default values of the Mode Registers (MR#) are not defined, contents of Mode Registers must be fully initialized and/or re-initialized, i.e. written, after power up and/or reset for proper operation. Also the contents of the Mode Registers can be altered by re-executing the MRS command during normal operation. When programming the mode registers, even if the user chooses to modify only a sub-set of the MRS fields, all address fields within the accessed mode register must be redefined when the MRS command is issued. MRS command and DLL Reset do not affect array contents, which means these commands can be executed any time after power-up without affecting the array contents The mode register set command cycle time, tMRD is required to complete the write operation to the mode register and is the minimum time required between two MRS commands shown as below. Integrated Silicon Solution, Inc. – www.issi.com – Rev. B1 06/25/2021 9 IS43/46TR16512B, IS43/46TR16512BL, IS43/46TR81024B, IS43/46TR81024BL CK# CK Command Valid Valid Valid MRS NOP/ DEC NOP/ DEC MRS NOP/ DEC NOP/ DEC Valid Valid Address Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid CKE Old Settings Settings New Settings tMRD tMRD RTT_Nom ENABLED prior and/or after MRS command ODT ODT Valid Valid ODTLoff + 1 Valid RTT_Nom DISABLED prior and after MRS command Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid (( )) Valid DON’T CARE Time Break Figure2.3.1a tMRD Timing The MRS command to Non-MRS command delay, tMOD, is require for the DRAM to update the features except DLL reset, and is the minimum time required from an MRS command to a non-MRS command excluding NOP and DES shown as the following figure. CK# CK Command Valid Valid Valid MRS NOP/ DEC NOP/ DEC NOP/ DEC NOP/ DEC NOP/ DEC Valid Valid Address Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid CKE Old Settings Settings New Settings tMOD RTT_Nom ENABLED prior and/or after MRS command ODT Valid Valid ODTLoff + 1 Valid RTT_Nom DISABLED prior and after MRS command ODT Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid (( )) Time Break Valid DON’T CARE Figure 2.3.1b tMOD Timing The mode register contents can be changed using the same command and timing requirements during normal operation as long as the DRAM is in idle state, i.e., all banks are in the precharged state with tRP satisfied, all data bursts are completed and CKE is high prior to writing into the mode register. If the RTT_NOM Feature is enabled in the Mode Register prior and/or after an MRS Command, the ODT Signal must continuously be registered LOW ensuring RTT is in an off State prior to the MRS command. The ODT Signal maybe registered high after tMOD has expired. If the RTT_NOM Feature is disabled in the Mode Register prior and after an MRS command, the ODT Signal can be registered either LOW or HIGH before, during and after the MRS command. The mode registers are divided into various fields depending on the functionality and/or modes. Integrated Silicon Solution, Inc. – www.issi.com – Rev. B1 06/25/2021 10 IS43/46TR16512B, IS43/46TR16512BL, IS43/46TR81024B, IS43/46TR81024BL 2.3.2 Mode Register MR0 The mode register MR0 stores the data for controlling various operating modes of DDR3 SDRAM. It controls burst length, read burst type, CAS latency, test mode, DLL reset, WR and DLL control for precharge Power-Down, which include vendor specific options to make DDR3 SDRAM useful for various applications. The mode register is written by asserting low on CS#, RAS#, CAS#, WE#, BA0, BA1, and BA2, while controlling the states of address pins according to the following figure. BA2 BA1 BA0 0 0 0 A8 0 1 A12 0 1 BA1 BA0 0 0 0 1 1 0 1 1 A15-A13 0* 1 A12 PPD A11 DLL Reset No Yes DLL Control for Precharge PD Slow exit (DLL off) Fast exit (DLL on) MR Select MR0 MR1 MR2 MR3 A7 0 1 A10 WR A9 mode Nomal Test A8 DLL A7 TM A6 A5 A4 CAS Latency A3 0 1 Read Burst Type Nibble Sequential Interleave Write recovery for autoprecharge A11 A10 A9 WR(cycles) 0 0 0 16 *2 0 0 1 5 *2 0 1 0 6 *2 0 1 1 7 *2 1 0 0 8 *2 1 0 1 10 *2 1 1 0 12 *2 1 1 1 14 *2 A3 RBT A2 CL A1 A0 A1 0 0 1 1 A0 0 1 0 1 BL 8 (Fixed) BC4 or 8 (on the fly) BC4 (Fixed) Reserved BL Address Field Mode Register 0 A6 0 0 0 0 1 1 1 1 A5 0 0 1 1 0 0 1 1 A4 0 1 0 1 0 1 0 1 A2 0 0 0 0 0 0 0 0 CAS Latency Reserved 5 6 7 8 9 10 11 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 1 1 1 1 1 1 12 13 14 Reserved Reserved Reserved 1 1 0 1 Reserved 1 1 1 1 Reserved 1. A15,A14 and A13 must be programmed to 0 during MRS. 2. WR (write recovery for autoprecharge)min in clock cycles is calculated by dividing tWR(in ns) by tCK(in ns) and rounding up to the next integer: WRmin[cycles] = Roundup(tWR[ns] / tCK[ns]). The WR value in the mode register must be programmed to be equal or larger than WRmin. The programmed WR value is used with tRP to determine tDAL. 3. The table only shows the encodings for a given Cas Latency. For actual supported Cas Latency, please refer to speedbin tables for each frequency 4. The table only shows the encodings for Write Recovery. For actual Write recovery timing, please refer to AC timing table. Figure 2.3.2 — MR0 Definition 2.3.2.1 Burst Length, Type and Order Accesses within a given burst may be programmed to sequential or interleaved order. The burst type is selected via bit A3 as shown in Figure 2.3.2. The ordering of accesses within a burst is determined by the burst length, burst type, and the starting column address as shown in Table below. The burst length is defined by bits A0-A1. Burst length options include fixed BC4, fixed BL8, and ‘on the fly’ which allows BC4 or BL8 to be selected coincident with the registration of a Read or Write command via A12/BC#. Integrated Silicon Solution, Inc. – www.issi.com – Rev. B1 06/25/2021 11 IS43/46TR16512B, IS43/46TR16512BL, IS43/46TR81024B, IS43/46TR81024BL Burst Length 4 Chop READ/ WRITE READ WRITE 8 READ WRITE Starting Column ADDRESS (A2,A1,A0) 0 1 10 11 100 101 110 111 0,V,V 1,V,V 0 1 10 11 100 101 110 111 V,V,V burst type = Sequential (decimal) A3 = 0 burst type = Interleaved (decimal) A3 = 1 Notes 0,1,2,3,T,T,T,T 1,2,3,0,T,T,T,T 2,3,0,1,T,T,T,T 3,0,1,2,T,T,T,T 4,5,6,7,T,T,T,T 5,6,7,4,T,T,T,T 6,7,4,5,T,T,T,T 7,4,5,6,T,T,T,T 0,1,2,3,X,X,X,X 4,5,6,7,X,X,X,X 0,1,2,3,4,5,6,7 1,2,3,0,5,6,7,4 2,3,0,1,6,7,4,5 3,0,1,2,7,4,5,6 4,5,6,7,0,1,2,3 5,6,7,4,1,2,3,0 6,7,4,5,2,3,0,1 7,4,5,6,3,0,1,2 0,1,2,3,4,5,6,7 0,1,2,3,T,T,T,T 1,0,3,2,T,T,T,T 2,3,0,1,T,T,T,T 3,2,1,0,T,T,T,T 4,5,6,7,T,T,T,T 5,4,7,6,T,T,T,T 6,7,4,5,T,T,T,T 7,6,5,4,T,T,T,T 0,1,2,3,X,X,X,X 4,5,6,7,X,X,X,X 0,1,2,3,4,5,6,7 1,0,3,2,5,4,7,6 2,3,0,1,6,7,4,5 3,2,1,0,7,6,5,4 4,5,6,7,0,1,2,3 5,4,7,6,1,0,3,2 6,7,4,5,2,3,0,1 7,6,5,4,3,2,1,0 0,1,2,3,4,5,6,7 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 4, 5 1, 2, 4, 5 2 2 2 2 2 2 2 2 2, 4 Notes: 1. In case of burst length being fixed to 4 by MR0 setting, the internal write operation starts two clock cycles earlier than for the BL8 mode. This means that the starting point for tWR and tWTR will be pulled in by two clocks. In case of burst length being selected on-the-fly via A12/BC#, the internal write operation starts at the same point in time like a burst of 8 write operation. This means that during on-the-fly control, the starting point for tWR and tWTR will not be pulled in by two clocks. 2. 0...7 bit number is value of CA[2:0] that causes this bit to be the first read during a burst. 3. T: Output driver for data and strobes are in high impedance. 4. V: a valid logic level (0 or 1), but respective buffer input ignores level on input pins. 5. X: Don’t Care. 2.3.2.2 CAS Latency The CAS Latency is defined by MR0 (bits A9-A11) as shown in Figure 2.3.2. CAS Latency is the delay, in clock cycles, between the internal Read command and the availability of the first bit of output data. DDR3 SDRAM does not support any half-clock latencies. The overall Read Latency (RL) is defined as Additive Latency (AL) + CAS Latency (CL); RL = AL + CL. For more information on the supported CL and AL settings based on the operating clock frequency, refer to “Standard Speed Bins”. 2.3.2.3 Test Mode The normal operating mode is selected by MR0 (bit A7 = 0) and all other bits set to the desired values shown in Figure 2.3.2. Programming bit A7 to a ‘1’ places the DDR3 SDRAM into a test mode that is only used by the DRAM Manufacturer and should NOT be used. No operations or functionality is specified if A7 = 1. 2.3.2.4 DLL Reset The DLL Reset bit is self-clearing, meaning that it returns back to the value of ‘0’ after the DLL reset function has been issued. Once the DLL is enabled, a subsequent DLL Reset should be applied. Any time that the DLL reset function is used, tDLLK must be met before any functions that require the DLL can be used (i.e., Read commands or ODT synchronous operations). 2.3.2.5 Write Recovery The programmed WR value MR0 (bits A9, A10, and A11) is used for the auto precharge feature along with tRP to determine tDAL. WR (write recovery for auto-precharge) min in clock cycles is calculated by dividing tWR (in ns) by tCK (in ns) and rounding up to the next integer: WRmin[cycles] = Roundup(tWR[ns]/tCK[ns]). The WR must be programmed to be equal to or larger than tWR(min). Integrated Silicon Solution, Inc. – www.issi.com – Rev. B1 06/25/2021 12 IS43/46TR16512B, IS43/46TR16512BL, IS43/46TR81024B, IS43/46TR81024BL 2.3.2.6 Precharge PD DLL MR0 (bit A12) is used to select the DLL usage during precharge power-down mode. When MR0 (A12 = 0), or ‘slow-exit’, the DLL is frozen after entering precharge power-down (for potential power savings) and upon exit requires tXPDLL to be met prior to the next valid command. When MR0 (A12 = 1), or ‘fast-exit’, the DLL is maintained after entering precharge power-down and upon exiting power-down requires tXP to be met prior to the next valid command. 2.3.3 Mode Register MR1 The Mode Register MR1 stores the data for enabling or disabling the DLL, output driver strength, Rtt_Nom impedance, additive latency, Write leveling enable, TDQS enable and Qoff. The Mode Register 1 is written by asserting low on CS#, RAS#, CAS#, WE#, high on BA0 and low on BA1 and BA2, while controlling the states of address pins according to Figure 2.3.3. BA2 BA1 BA0 0 0 1 A11 0 1 A15-A13 0* 1 TDQS enable Disabled Enabled A4 0 0 1 1 A12 0 1 A12 A11 A10 Qoff TDQS 0* 1 A9 Rtt A7 0 1 Write leveling enable Disabled Enabled A3 0 1 0 1 Additive Latency 0 (AL disabled) CL-1 CL-2 Reserved A8 0* 1 A6 Rtt A5 D.I.C A9 0 0 0 0 1 1 1 1 A6 0 0 1 1 0 0 1 1 A2 0 1 0 1 0 1 0 1 A4 A3 AL A2 Rtt Rtt_Nom *3 ODT disabled RZQ/4 RZQ/2 RZQ/6 RZQ/12 *4 RZQ/8 *4 Reserved Reserved A1 A0 Address Field D.I.C DLL Mode Register 1 A0 0 1 DLL Enable Enable Disable Note: RZQ = 240  *3:In Write leveling Mode (MR1[bit7] = 1) with MR1[bit12]=1, all RTT_Nom settings are allowed; in Write Leveling Mode (MR1[bit7] = 1) with MR1[bit12]=0, only RTT_Nom settings of RZQ/2, RZQ/4 and RZQ/6 are allowed. *4:If RTT_Nom is used during Writes, only the values RZQ/2, RZQ/4 and RZQ/6 are allowed. Qoff *2 Output buffer enabled Output buffer disabled *2 *2: Outputs disabled - DQs, DQSs, DQS#s. BA1 BA0 0 0 0 1 1 0 1 1 A7 Level MR Select MR0 MR1 MR2 MR3 A5 0 0 1 A1 0 1 0 Output Driver Impedance Control RZQ/6 RZQ/7 Reserved 1 1 Reserved * 1 : A8, A10, A13, A14, and A15 must be programmed to 0 during MRS. * TDQS must be disabled for x16 option. Figure 2.3.3 MR1 Definition 2.3.3.1 DLL Enable/Disable The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and upon returning to normal operation after having the DLL disabled. During normal operation (DLL-on) with MR1 (A0 = 0), the DLL is automatically disabled when entering Self-Refresh operation and is automatically re-enabled upon exit of Self-Refresh operation. Any time the DLL is enabled and subsequently reset, tDLLK clock cycles must occur before a Read or synchronous ODT command can be issued to allow time for the internal clock to be synchronized with the external clock. Failing to wait for synchronization to occur may result in a violation of the tDQSCK, tAON or tAOF parameters. During tDLLK, CKE must continuously be registered high. DDR3 SDRAM does not require DLL for any Write operation, except Integrated Silicon Solution, Inc. – www.issi.com – Rev. B1 06/25/2021 13 IS43/46TR16512B, IS43/46TR16512BL, IS43/46TR81024B, IS43/46TR81024BL when RTT_WR is enabled and the DLL is required for proper ODT operation. For more detailed information on DLL Disable operation refer to “DLL-off Mode”. The direct ODT feature is not supported during DLL-off mode. The on-die termination resistors must be disabled by continuously registering the ODT pin low and/or by programming the RTT_Nom bits MR1{A9,A6,A2} to {0,0,0} via a mode register set command during DLL-off mode. The dynamic ODT feature is not supported at DLL-off mode. User must use MRS command to set Rtt_WR, MR2 {A10, A9} = {0,0}, to disable Dynamic ODT externally. 2.3.3.2 Output Driver Impedance Control The output driver impedance of the DDR3 SDRAM device is selected by MR1 (bits A1 and A5) as shown in Figure 2.3.3. 2.3.3.3 ODT Rtt Values DDR3 SDRAM is capable of providing two different termination values (Rtt_Nom and Rtt_WR). The nominal termination value Rtt_Nom is programmed in MR1. A separate value (Rtt_WR) may be programmed in MR2 to enable a unique RTT value when ODT is enabled during writes. The Rtt_WR value can be applied during writes even when Rtt_Nom is disabled. 2.3.3.4 Additive Latency (AL) Additive Latency (AL) operation is supported to make command and data bus efficient for sustainable bandwidths in DDR3 SDRAM. In this operation, the DDR3 SDRAM allows a read or write command (either with or without autoprecharge) to be issued immediately after the active command. The command is held for the time of the Additive Latency (AL) before it is issued inside the device. The Read Latency (RL) is controlled by the sum of the AL and CAS Latency (CL) register settings. Write Latency (WL) is controlled by the sum of the AL and CAS Write Latency (CWL) register settings. A summary of the AL register options are shown in Table below. A4 0 0 1 1 A3 0 1 0 1 Additive Latency (AL) Settings 0 (AL Disabled) CL - 1 CL - 2 Reserved NOTE: AL has a value of CL - 1 or CL - 2 as per the CL values programmed in the MR0 register. 2.3.3.5 Write leveling For better signal integrity, DDR3 memory module adopted fly-by topology for the commands, addresses, control signals, and clocks. The fly-by topology has the benefit of reducing the number of stubs and their length, but it also causes flight time skew between clock and strobe at every DRAM on the DIMM. This makes it difficult for the Controller to maintain tDQSS, tDSS, and tDSH specification. Therefore, the DDR3 SDRAM supports a ‘write leveling’ feature to allow the controller to compensate for skew. 2.3.3.6 Output Disable The DDR3 SDRAM outputs may be enabled/disabled by MR1 (bit A12) as shown in Figure 2.3.3. When this feature is enabled (A12 = 1), all output pins (DQs, DQS, DQS#, etc.) are disconnected from the device, thus removing any loading of the output drivers. This feature may be useful when measuring module power, for example. For normal operation, A12 should be set to ‘0’. 2.3.3.7 TDQS, TDQS# TDQS (Termination Data Strobe) is a feature of X8 DDR3 SDRAM that provides additional termination resistance outputs that may be useful in some system configurations. The TDQS function is available in X8 DDR3 SDRAM only and must be disabled via the mode register A11=0 in MR1 for X16 configuration. Integrated Silicon Solution, Inc. – www.issi.com – Rev. B1 06/25/2021 14 IS43/46TR16512B, IS43/46TR16512BL, IS43/46TR81024B, IS43/46TR81024BL 2.3.4 Mode Register MR2 The Mode Register MR2 stores the data for controlling refresh related features, Rtt_WR impedance, and CAS write latency. The Mode Register 2 is written by asserting low on CS#, RAS#, CAS#, WE#, high on BA1 and low on BA0 and BA2, while controlling the states of address pins according to the below. BA2 0 BA1 1 A7 0 1 BA0 0 A15-A13 A12 A11 0* 1 A10 A9 Rtt_WR Self-Refresh Temperature (SRT) Range Normal operating temperature range Extended operating temperature range A6 0 1 Auto Self-Refresh (ASR) Manual SR Reference (SRT) ASR enable A10 0 0 A9 0 1 1 0 1 1 BA1 BA0 0 0 0 1 1 0 1 1 Rtt_WR *2 Dynamic ODT off (Write does not affect Rtt value) RZQ/4 A8 0* 1 A7 SRT A6 ASR A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 A5 A4 CWL A3 A2 A1 A0 PASR Address Field Mode Register 2 Partial Array Self-Refresh Full Array HalfArray (BA[2:0]=000,001,010, &011) Quarter Array (BA[2:0]=000, & 001) 1/8th Array (BA[2:0] = 000) 3/4 Array (BA[2:0] = 010,011,100,101,110, & 111) HalfArray (BA[2:0] = 100, 101, 110, &111) Quarter Array (BA[2:0]=110, &111) 1/8th Array (BA[2:0]=111) A5 0 0 A4 0 0 A3 0 1 CAS write Latency (CWL) 5 (tCK(avg)  2.5 ns) 6 (2.5 ns > tCK(avg)  1.875 ns) RZQ/2 0 1 0 7 (1.875 ns > tCK(avg)  1.5 ns) Reserved 0 1 1 8 (1.5 ns > tCK(avg)  1.25 ns) 1 0 0 9 (1.25 ns > tCK(avg)  1.07ns) 1 1 1 0 1 1 1 0 1 10 (1.07 ns > tCK(avg)  0.935 ns) Reserved Reserved MR Select MR0 MR1 MR2 MR3 * 1 : A5, A8, A11 ~ A15 must be programmed to 0 during MRS. * 2 : The Rtt_WR value can be applied during writes even when Rtt_Nom is disabled. During write leveling, Dynamic ODT is not available. Figure 2.3.4 MR2 Definition 2.3.4.1 Partial Array Self-Refresh (PASR) If PASR (Partial Array Self-Refresh) is enabled, data located in areas of the array beyond the specified address range shown in Figure 2.3.4 will be lost if Self-Refresh is entered. Data integrity will be maintained if tREFI conditions are met and no Self-Refresh command is issued. 2.3.4.2 CAS Write Latency (CWL) The CAS Write Latency is defined by MR2 (bits A3-A5), as shown in Figure 2.3.4. CAS Write Latency is the delay, in clock cycles, between the internal Write command and the availability of the first bit of input data. DDR3 SDRAM does not support any half-clock latencies. The overall Write Latency (WL) is defined as Additive Latency (AL) + CAS Write Latency (CWL); WL = AL + CWL. For more information on the supported CWL and AL settings based on the operating clock frequency, refer to “Standard Speed Bins”. 2.3.4.3 Auto Self-Refresh (ASR) and Self-Refresh Temperature (SRT) For more details refer to “Extended Temperature Usage”. DDR3 SDRAMs support Self-Refresh operation at all supported temperatures. Applications requiring Self-Refresh operation in the Extended Temperature Range must use the ASR function or program the SRT bit appropriately. Integrated Silicon Solution, Inc. – www.issi.com – Rev. B1 06/25/2021 15 IS43/46TR16512B, IS43/46TR16512BL, IS43/46TR81024B, IS43/46TR81024BL 2.3.4.4 Dynamic ODT (Rtt_WR) DDR3 SDRAM introduces a new feature “Dynamic ODT”. In certain application cases and to further enhance signal integrity on the data bus, it is desirable that the termination strength of the DDR3 SDRAM can be changed without issuing an MRS command. MR2 Register locations A9 and A10 configure the Dynamic ODT setings. In Write leveling mode, only RTT_Nom is available. For details on Dynamic ODT operation, refer to “Dynamic ODT”. 2.3.5 Mode Register MR3 The Mode Register MR3 controls Multi-purpose registers. The Mode Register 3 is written by asserting low on CS#, RAS#, CAS#, WE#, high on BA1 and BA0, and low on BA2 while controlling the states of address pins according to the below. BA2 BA1 BA0 0 1 1 A15-A13 A12 A11 A9 A8 A7 A6 A5 A4 A3 0* 1 MRP Operation A2 MPR 0 Normal operation *3 1 Dataflow from MPR BA1 BA0 0 0 0 1 1 0 1 1 A10 MPR Address A1 A0 0 0 0 1 1 0 1 1 A2 MPR MPR location Predefined pattern RFU RFU RFU A1 A0 MPR Loc Address Field Mode Register 3 *2 MR Select MR0 MR1 MR2 MR3 * 1 : A3 - A15 must be programmed to 0 during MRS. * 2 : The predefined pattern will be used for read synchronization. * 3 : When MPR control is set for normal operation (MR3 A[2] = 0) then MR3 A[1:0] will be ignored. Figure 2.3.5 MR3 Definition 2.3.5.1 Multi-Purpose Register (MPR) The Multi Purpose Register (MPR) function is used to Read out a predefined system timing calibration bit sequence. To enable the MPR, a Mode Register Set (MRS) command must be issued to MR3 register with bit A2=1. Prior to issuing the MRS command, all banks must be in the idle state (all banks precharged and tRP met). Once the MPR is enabled, any subsequent RD or RDA commands will be redirected to the Multi Purpose Register. When the MPR is enabled, only RD or RDA commands are allowed until a subsequent MRS command is issued with the MPR disabled (MR3 bit A2=0). Power down mode, Self-Refresh and any other non-RD/RDA command is not allowed during MPR enable mode. The RESET function is supported during MPR enable mode. The Multi Purpose Register (MPR) function is used to Read out a predefined system timing calibration bit sequence. The basic concept of the MPR is shown in Figure 2.3.5.1. Integrated Silicon Solution, Inc. – www.issi.com – Rev. B1 06/25/2021 16 IS43/46TR16512B, IS43/46TR16512BL, IS43/46TR81024B, IS43/46TR81024BL Memory Core (all banks precharged) MR3[A2] Multipurpose Register pre-defined data for read DQ, DM, DQS, DQS# Figure 2.3.5.1 MPR Block Diagram To enable the MPR, a MODE Register Set (MRS) command must be issued to MR3 Register with bit A2 = 1. Prior to issuing the MRS command, all banks must be in the idle state (all banks precharged and tRP met). Once the MPR is enabled, any subsequent RD or RDA commands will be redirected to the Multi Purpose Register. The resulting operation, when a RD or RDA command is issued, is defined by MR3 bits A[1:0] when the MPR is enabled. When the MPR is enabled, only RD or RDA commands are allowed until a subsequent MRS command is issued with the MPR disabled (MR3 bit A2 = 0). Note that in MPR mode RDA has the same functionality as a READ command which means the auto precharge part of RDA is ignored. Power-Down mode, Self-Refresh and any other non-RD/RDA command is not allowed during MPR enable mode. The RESET function is supported during MPR enable mode. MPR MR3 Register Definition MR3 A[2] MR3 A[1:0] Function MPR MPR-Loc 0b don’t care (0b or 1b) Normal operation, no MPR transaction. All subsequent Reads will come from DRAM array. All subsequent Write will go to DRAM array. 1b See MPR Definition table Enable MPR mode, subsequent RD/RDA commands defined by MR3 A[1:0]. Integrated Silicon Solution, Inc. – www.issi.com – Rev. B1 06/25/2021 17 IS43/46TR16512B, IS43/46TR16512BL, IS43/46TR81024B, IS43/46TR81024BL MPR Register Address Definition The following Table provides an overview of the available data locations, how they are addressed by MR3 A[1:0] during a MRS to MR3, and how their individual bits are mapped into the burst order bits during a Multi Purpose Register Read. MPR MR3 Register Definition MR3 MR3 Function A[2] A[1:0] 1b 00b Read predefined pattern for system Calibration 1b 01b RFU 1b 10b RFU 1b 11b RFU Burst Length Read Address A[2:0] BL8 000b BC4 000b BC4 100b BL8 BC4 BC4 BL8 BC4 BC4 BL8 BC4 BC4 000b 000b 100b 000b 000b 100b 000b 000b 100b Burst Order and Data Pattern Burst order 0,1,2,3,4,5,6,7 Pre-defined Data Pattern [0,1,0,1,0,1,0,1] Burst order 0,1,2,3 Pre-defined Data Pattern [0,1,0,1] Burst order 4,5,6,7 Pre-defined Data Pattern [0,1,0,1] Burst order 0,1,2,3,4,5,6,7 Burst order 0,1,2,3 Burst order 4,5,6,7 Burst order 0,1,2,3,4,5,6,7 Burst order 0,1,2,3 Burst order 4,5,6,7 Burst order 0,1,2,3,4,5,6,7 Burst order 0,1,2,3 Burst order 4,5,6,7 NOTE: Burst order bit 0 is assigned to LSB and the burst order bit 7 is assigned to MSB of the selected MPR agent MPR Functional Description     One bit wide logical interface via all DQ pins during READ operation. Register Read on x16: o DQL[0] and DQU[0] drive information from MPR. o DQL[7:1] and DQU[7:1] either drive the same information as DQL[0], or they drive 0b. Addressing during for Multi Purpose Register reads for all MPR agents: o BA[2:0]: don’t care o A[1:0]: A[1:0] must be equal to ‘00’b. Data read burst order in nibble is fixed o A[2]: For BL=8, A[2] must be equal to 0b, burst order is fixed to [0,1,2,3,4,5,6,7], *) For Burst Chop 4 cases, the burst order is switched on nibble base A[2]=0b, Burst order: 0,1,2,3 *) A[2]=1b, Burst order: 4,5,6,7 *) o A[9:3]: don’t care o A10/AP: don’t care o A12/BC: Selects burst chop mode on-the-fly, if enabled within MR0. o A11, A13, A14, A15: don’t care Regular interface functionality during register reads: o Support two Burst Ordering which are switched with A2 and A[1:0]=00b. o Support of read burst chop (MRS and on-the-fly via A12/BC) o All other address bits (remaining column address bits including A10, all bank address bits) will be ignored by the DDR3 SDRAM. o Regular read latencies and AC timings apply. o DLL must be locked prior to MPR Reads. NOTE: *) Burst order bit 0 is assigned to LSB and burst order bit 7 is assigned to MSB of the selected MPR agent. NOTE: Good reference for the example of MPR feature is the JEDEC standard No.93-3D, 4.10.4 Protocol example. Relevant Timing Parameters AC timing parameters are important for operating the Multi Purpose Register: tRP, tMRD, tMOD, and tMPRR. For more details refer to “Electrical Characteristics & AC Timing Integrated Silicon Solution, Inc. – www.issi.com – Rev. B1 06/25/2021 18 IS43/46TR16512B, IS43/46TR16512BL, IS43/46TR81024B, IS43/46TR81024BL 2.4 DDR3 SDRAM Command Description and Operation 2.4.1 Command Truth Table [BA=Bank Address, RA=Row Address, CA=Column Address, BC#=Burst Chop, X=Don’t Care, V=Valid] CKE A11, A13 A14 A15 A0A9, A11 Abbrev. Previous Cycle Current Cycle CS# RAS# CAS# WE# Mode Register Set Refresh MRS REF H H H H L L L L L L L H BA V V OP Code V V V Self Refresh Entry SRE H L L L L H V V V V V Self Refresh Exit SRX L H H L X H X H X H X V X V X V X V X V Single Bank Precharge Precharge all Banks Bank Activate Write (Fixed BL8 or BC4) Write (BC4, on the Fly) Write (BL8, on the Fly) Write with Auto Precharge (Fixed BL8 or BC4) Write with Auto Precharge (BC4, on the Fly) Write with Auto Precharge (BL8, on the Fly) Read (Fixed BL8 or BC4) Read (BC4, on the Fly) Read (BL8, on the Fly) Read with Auto Precharge (Fixed BL8 or BC4) Read with Auto Precharge (BC4, on the Fly) Read with Auto Precharge (BL8, on the Fly) No Operation Device Deselected PRE PREA ACT WR WRS4 WRS8 H H H H H H H H H H H H L L L L L L L L L H H H H H H L L L L L H L L L BA V BA BA BA BA V V V V L H V V RFU RFU RFU V L H L L L CA CA CA WRA H H L H L L BA RFU V H CA WRAS4 H H L H L L BA RFU L H CA WRAS8 H H L H L L BA RFU H H CA RD RDS4 RDS8 H H H H H H L L L H H H L L L H H H BA BA BA RFU RFU RFU V L H L L L CA CA CA RDA H H L H L H BA RFU V H CA RDAS4 H H L H L H BA RFU L H CA RDAS8 H H L H L H BA RFU H H CA NOP DES H H H H PDE H L L H L H L H L L H X H X H X H H H X H X H X H H H X H X H X L L V X V X V X X X V X V X V X X X V X V X V X X X V X V X V X H L V X V X V X X X Power Down Entry Power Down Exit PDX L H ZQ Calibration Long ZQ Calibration Short ZQCL ZQCS H H H H A12/ BC# A1 0/A P Function BA0BA2 Note s 7,9,1 2 7,8,9 ,12 Row Address(RA) Notes: 1. All DDR3 SDRAM commands are defined by states of CS#, RAS#, CAS#, WE# and CKE at the rising edge of the clock. The MSB of BA, RA and CA are device density and configuration dependant. 2. RESET# is Low enable command which will be used only for asynchronous reset so must be maintained HIGH during any function. 3. Bank addresses (BA) determine which bank is to be operated upon. For (E)MRS BA selects an (Extended) Mode Register. 4. “V” means “H or L (but a defined logic level)” and “X” means either “defined or undefined (like floating) logic level”. 5. Burst reads or writes cannot be terminated or interrupted and Fixed/on-the-Fly BL will be defined by MRS. 6. The Power Down Mode does not perform any refresh operation. 7. The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh. 8. Self Refresh Exit is asynchronous. 9. VREF(Both VrefDQ and VrefCA) must be maintained during Self Refresh operation. VrefDQ supply may be turned OFF and VREFDQ may take any value between VSS and VDD during Self Refresh operation, provided that VrefDQ is valid and stable prior to CKE going back High and that first Write operation or first Write Leveling Activity may not occur earlier than 512 nCK after exit from Self Refresh. 10. The No Operation command should be used in cases when the DDR3 SDRAM is in an idle or wait state. The purpose of the No Operation command (NOP) is to prevent the DDR3 SDRAM from registering any unwanted commands between operations. A No Operation command will not terminate a pervious operation that is still executing, such as a burst read or write cycle. 11. The Deselect command performs the same function as No Operation command. 12. Refer to the CKE Truth Table for more detail with CKE transition. Integrated Silicon Solution, Inc. – www.issi.com – Rev. B1 06/25/2021 19 10 11 6,12 6,12 IS43/46TR16512B, IS43/46TR16512BL, IS43/46TR81024B, IS43/46TR81024BL 2.4.1. CKE Truth Table CKE Current State2 Power-Down Cycle1 Previous (N-1) L Current Cycle1(N) L L H L L L H Bank(s) Active H L Reading H L Writing H L Precharging H L Refreshing H L All Bank Idle H L H L Self-Refresh Command (N)3 RAS#, CAS#, WE#, CS# X DESELECT or NOP X DESELECT or NOP DESELECT or NOP DESELECT or NOP DESELECT or NOP DESELECT or NOP DESELECT or NOP DESELECT or NOP REFRESH Action (N)3 Notes Maintain Power-Down 14,15 Power-Down Exit 11,14 Maintain Self-Refresh 15,16 Self-Refresh Exit 8,12,16 Active Power-Down Entry 11,13,14 Power-Down Entry 11,13,14,17 Power-Down Entry 11,13,14,17 Power-Down Entry 11,13,14,17 Precharge Power-Down Entry 11 Precharge Power-Down Entry 11,13,14,18 Self-Refresh 9.13.18 Notes: 1. CKE (N) is the logic state of CKE at clock edge N; CKE (N-1) was the state of CKE at the previous clock edge. 2. Current state is defined as the state of the DDR3 SDRAM immediately prior to clock edge N. 3. COMMAND (N) is the command registered at clock edge N, and ACTION (N) is a result of COMMAND (N), ODT is not included here. 4. All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document. 5. The state of ODT does not affect the states described in this table. The ODT function is not available during Self-Refresh. 6. CKE must be registered with the same value on tCKEmin consecutive positive clock edges. CKE must remain at the valid input level the entire time it takes to achieve the tCKEmin clocks of registeration. Thus, after any CKE transition, CKE may not transition from its valid level during the time period of tIS + tCKEmin + tIH. 7. DESELECT and NOP are defined in the Command Truth Table. 8. On Self-Refresh Exit DESELECT or NOP commands must be issued on every clock edge occurring during the tXS period. Read or ODT commands may be issued only after tXSDLL is satisfied. 9. Self-Refresh mode can only be entered from the All Banks Idle state. 10. Must be a legal command as defined in the Command Truth Table. 11. Valid commands for Power-Down Entry and Exit are NOP and DESELECT only. 12. Valid commands for Self-Refresh Exit are NOP and DESELECT only. 13. Self-Refresh cannot be entered during Read or Write operations. 14. The Power-Down does not perform any refresh operations. 15. “X” means “don’t care“ (including floating around VREF) in Self-Refresh and Power-Down. It also applies to Address pins. 16. VREF (Both Vref_DQ and Vref_CA) must be maintained during Self-Refresh operation.VrefDQ supply may be turned OFF and VREFDQ may take any value between VSS and VDD during Self Refresh operation, provided that VrefDQ is valid and stable prior to CKE going back High and that first Write operation or first Write Leveling Activity may not occur earlier than 512 nCK after exit from Self Refresh. 17. If all banks are closed at the conclusion of the read, write or precharge command, then Precharge Power-Down is entered, otherwise Active PowerDown is entered. 18. ‘Idle state’ is defined as all banks are closed (tRP, tDAL, etc. satisfied), no data bursts are in progress, CKE is high, and all timings from previous operations are satisfied (tMRD, tMOD, tRFC, tZQinit, tZQoper, tZQCS, etc.) as well as all Self-Refresh exit and Power-Down Exit parameters are satisfied (tXS, tXP, tXPDLL, etc). 2.4.2 No Operation (NOP) Command The No operation (NOP) command is used to instruct the selected DDR3 SDRAM to perform a NOP ( CS# low and RAS#,CAS#,WE# high). This prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected. Integrated Silicon Solution, Inc. – www.issi.com – Rev. B1 06/25/2021 20 IS43/46TR16512B, IS43/46TR16512BL, IS43/46TR81024B, IS43/46TR81024BL 2.4.3 Deselect(DES) Command The Deselect function (CS# HIGH) prevents new commands from being executed by the DDR3 SDRAM. The DDR3 SDRAM is effectively deselected. Operations already in progress are not affected. 2.4.4 DLL-off Mode DDR3 DLL-off mode is entered by setting MR1 bit A0 to “1”; this will disable the DLL for subsequent operations until A0 bit set back to “0”. The MR1 A0 bit for DLL control can be switched either during initialization or later. The DLL-off Mode operations listed below are an optional feature for DDR3. The maximum clock frequency for DLL-off Mode is specified by the parameter tCKDLL_OFF. There is no minimum frequency limit besides the need to satisfy the refresh interval, tREFI. Due to latency counter and timing restrictions, only one value of CAS Latency (CL) in MR0 and CAS Write Latency (CWL) in MR2 are supported. The DLL-off mode is only required to support setting of both CL=6 and CWL=6. DLL-off mode will affect the Read data Clock to Data Strobe relationship (tDQSCK) but not the data Strobe to Data relationship (tDQSQ, tQH). Special attention is needed to line up Read data to controller time domain. Comparing with DLL-on mode, where tDQSCK starts from the rising clock edge (AL+CL) cycles after the Read command, the DLL-off mode tDQSCK starts (AL+CL-1) cycles after the read command. Another difference is that tDQSCK may not be small compared to tCK (it might even be larger than tCK) and the difference between tDQSCKmin and tDQSCKmax is significantly larger than in DLL-on mode. The timing relations on DLL-off mode READ operation have shown at the following Timing Diagram (CL=6, BL=8) T0 T1 T2 T3 T4 T5 READ NOP NOP NOP NOP NOP T6 T7 T8 T9 T10 NOP NOP NOP NOP NOP CK# CK Command Address DQS,DQS#(DLL_on) RL (DLL_on) = AL+CL =6 (CL=6,AL=0) CL=6 DQ(DLL_on) RL (DLL_off) = AL+(CL-1) = 5 tDQSCK(DLL_off)_min DQS,DQS#(DLL_off) DQ(DLL_off) tDQSCK(DLL_off)_max DQS,DQS#(DLL_off) DQ(DLL_off) Don’t Care Note: The tDQSCK is used here for DQS, DQS, and DQ to have a simplified diagram; the DLL_off shift will affect both timings in the same way and the skew between all DQ, DQS, and DQS# signals will still be tDQSQ. Figure 2.4.4 DLL-off mode READ Timing Operation Integrated Silicon Solution, Inc. – www.issi.com – Rev. B1 06/25/2021 21 IS43/46TR16512B, IS43/46TR16512BL, IS43/46TR81024B, IS43/46TR81024BL 2.4.5 DLL on/off switching procedure DDR3 DLL-off mode is entered by setting MR1 bit A0 to “1”; this will disable the DLL for subsequent operation until A0 bit set back to “0”. 2.4.5.1 DLL “on” to DLL “off” Procedure To switch from DLL “on” to DLL “off” requires te frequency to be changed during Self-Refresh outlined in the following procedure: 1. Starting from Idle state (all banks pre-charged, all timing fulfilled, and DRAMs On-die Termination resistors, RTT, must be in high impedance state before MRS to MR1 to disable the DLL). 2. Set MR1 Bit A0 to “1” to disable the DLL. 3. Wait tMOD. 4. Enter Self Refresh Mode; wait until (tCKSRE) satisfied. 5. Change frequency, in guidance with “Input Clock Frequency Change” section. 6. Wait until a stable clock is available for at least (tCKSRX) at DRAM inputs. 7. Starting with the Self Refresh Exit command, CKE must continuously be registered HIGH until all tMOD timings from any MRS command are satisfied. In addition, if any ODT features were enabled in the mode registers when Self Refresh mode was entered, the ODT signal must continuously be registered LOW until all tMOD timings from any MRS command are satisfied. If both ODT features were disabled in the mode registers when Self Refresh mode was entered, ODT signal can be registered LOW or HIGH. 8. Wait tXS, and then set Mode Registers with appropriate values (especially an update of CL, CWL, and WR may be necessary. A ZQCL command may also be issued after tXS). 9. Wait for tMOD, and then DRAM is ready for next command. 2.4.5.2 DLL “off” to DLL “on” Procedure To switch from DLL “off” to DLL “on” (with required frequency change) during Self-Refresh: 1. Starting from Idle state (All banks pre-charged, all timings fulfilled and DRAMs On-die Termination resistors (RTT) must be in high impedance state before Self-Refresh mode is entered.) 2. Enter Self Refresh Mode, wait until tCKSRE satisfied. 3. Change frequency, in guidance with "Input clock frequency change". 4. Wait until a stable clock is available for at least (tCKSRX) at DRAM inputs. 5. Starting with the Self Refresh Exit command, CKE must continuously be registered HIGH until tDLLK timing from subsequent DLL Reset command is satisfied. In addition, if any ODT features were enabled in the mode registers when Self Refresh mode was entered, the ODT signal must continuously be registered LOW until tDLLK timings from subsequent DLL Reset command is satisfied. If both ODT features are disabled in the mode registers when Self Refresh mode was entered, ODT signal can be registered LOW or HIGH. 6. Wait tXS, then set MR1 bit A0 to “0” to enable the DLL. 7. Wait tMRD, then set MR0 bit A8 to “1” to start DLL Reset. 8. Wait tMRD, then set Mode Registers with appropriate values (especially an update of CL, CWL and WR may be necessary. After tMOD satisfied from any proceeding MRS command, a ZQCL command may also be issued during or after tDLLK.) 9. Wait for tMOD, then DRAM is ready for next command (Remember to wait tDLLK after DLL Reset before applying command requiring a locked DLL!). In addition, wait also for tZQoper in case a ZQCL command was issued. Integrated Silicon Solution, Inc. – www.issi.com – Rev. B1 06/25/2021 22 IS43/46TR16512B, IS43/46TR16512BL, IS43/46TR81024B, IS43/46TR81024BL 2.4.6. Input clock frequency change Once the DDR3 SDRAM is initialized, the DDR3 SDRAM requires the clock to be “stable” during almost all states of normal operation. This means that, once the clock frequency has been set and is to be in the “stable state”, the clock period is not allowed to deviate except for what is allowed for by the clock jitter and SSC (spread spectrum clocking) specifications. The input clock frequency can be changed from one stable clock rate to another stable clock rate under two conditions: (1) Self-Refresh mode and (2) Precharge Power-down mode. Outside of these two modes, it is illegal to change the clock frequency. For the first condition, once the DDR3 SDRAM has been successfully placed in to Self-Refresh mode and tCKSRE has been satisfied, the state of the clock becomes a don’t care. Once a don’t care, changing the clock frequency is permissible, provided the new clock frequency is stable prior to tCKSRX. When entering and exiting Self-Refresh mode for the sole purpose of changing the clock frequency, the Self-Refresh entry and exit specifications must still be met. The DDR3 SDRAM input clock frequency is allowed to change only within the minimum and maximum operating frequency specified for the particular speed grade. Any frequency change below the minimum operating frequency would require the use of DLL_on- mode -> DLL_off -mode transition sequence, refer to “DLL on/off switching procedure”. The second condition is when the DDR3 SDRAM is in Precharge Power-down mode (either fast exit mode or slow exit mode). If the RTT_NOM feature was enabled in the mode register prior to entering Precharge power down mode, the ODT signal must continuously be registered LOW ensuring RTT is in an off state. If the RTT_NOM feature was disabled in the mode register prior to entering Precharge power down mode, RTT will remain in the off state. The ODT signal can be registered either LOW or HIGH in this case. A minimum of tCKSRE must occur after CKE goes LOW before the clock frequency may change. The DDR3 SDRAM input clock frequency is allowed to change only within the minimum and maximum operating frequency specified for the particular speed grade. During the input clock frequency change, ODT and CKE must be held at stable LOW levels. Once the input clock frequency is changed, stable new clocks must be provided to the DRAM tCKSRX before Precharge Power-down may be exited; after Precharge Power-down is exited and tXP has expired, the DLL must be RESET via MRS. Depending on the new clock frequency, additional MRS commands may need to be issued to appropriately set the WR, CL, and CWL with CKE continuously registered high. During DLL relock period, ODT must remain LOW and CKE must remain HIGH. After the DLL lock time, the DRAM is ready to operate with new clock frequency. 2.4.7 Write leveling For better signal integrity, the DDR3 memory module adopted fly-by topology for the commands, addresses, control signals, and clocks. The fly-by topology has benefits from reducing number of stubs and their length, but it also causes flight time skew between clock and strobe at every DRAM on the DIMM. This makes it difficult for the Controller to maintain tDQSS, tDSS, and tDSH specification. Therefore, the DDR3 SDRAM supports a ‘write leveling’ feature to allow the controller to compensate for skew. The memory controller can use the ‘write leveling’ feature and feedback from the DDR3 SDRAM to adjust the DQS DQS# to CK - CK# relationship. The memory controller involved in the leveling must have adjustable delay setting on DQS - DQS# to align the rising edge of DQS - DQS# with that of the clock at the DRAM pin. The DRAM asynchronously feeds back CK - CK#, sampled with the rising edge of DQS - DQS#, through the DQ bus. The controller repeatedly delays DQS - DQS# until a transition from 0 to 1 is detected. The DQS - DQS# delay established though this exercise would ensure tDQSS specification. Besides tDQSS, tDSS and tDSH specification also needs to be fulfilled. One way to achieve this is to combine the actual tDQSS in the application with an appropriate duty cycle and jitter on the DQS - DQS# signals. Depending on the actual tDQSS in the application, the actual values for tDQSL and tDQSH may have to be better than the absolute limits provided in the chapter "AC Timing Parameters" in order to satisfy tDSS and tDSH specification. A conceptual timing of this scheme is shown in Figure 2.4.7. Integrated Silicon Solution, Inc. – www.issi.com – Rev. B1 06/25/2021 23 IS43/46TR16512B, IS43/46TR16512BL, IS43/46TR81024B, IS43/46TR81024BL T0 Source T1 T2 T3 T4 T5 T6 T7 CK# CK diff_DQS Tn Destination T0 T1 T2 T3 T4 T5 T6 CK# CK diff_DQS DQ 0 or 1 0 0 0 Push DQS to capture 0-1 transition diff_DQS DQ 0 or 1 1 1 1 Figure 2.4.7 Write Leveling Concept DQS - DQS# driven by the controller during leveling mode must be terminated by the DRAM based on ranks populated. Similarly, the DQ bus driven by the DRAM must also be terminated at the controller. One or more data bits carry the leveling feedback to the controller across the DRAM configurations X8 and X16. On a X16 device, both byte lanes should be leveled independently. Therefore, a separate feedback mechanism should be available for each byte lane. The upper data bits should provide the feedback of the upper diff_DQS(diff_UDQS) to clock relationship whereas the lower data bits would indicate the lower diff_DQS(diff_LDQS) to clock relationship. 2.4.7.1 DRAM setting for write leveling & DRAM termination function in that mode DRAM enters into Write leveling mode if A7 in MR1 set ’High’ and after finishing leveling, DRAM exits from write leveling mode if A7 in MR1 set ’Low’. Note that in write leveling mode, only DQS/DQS# terminations are activated and deactivated via ODT pin, unlike normal operation. MR setting involved in the leveling procedure Function MR1 Enable Disable Write leveling enable Output buffer mode (Qoff) A7 A12 1 0 0 1 DRAM termination function in the leveling mode ODT pin @DRAM De-asserted Asserted DQS/DQS# termination Off On DQs termination Off Off NOTE: In Write Leveling Mode with its output buffer disabled (MR1[bit7] = 1 with MR1[bit12] = 1) all RTT_Nom settings are allowed; in Write Leveling Mode with its output buffer enabled (MR1[bit7] = 1 with MR1[bit12] = 0) only RTT_Nom settings of RZQ/2, RZQ/4 and RZQ/6 are allowed. Integrated Silicon Solution, Inc. – www.issi.com – Rev. B1 06/25/2021 24 IS43/46TR16512B, IS43/46TR16512BL, IS43/46TR81024B, IS43/46TR81024BL 2.4.7.2 Procedure Description The Memory controller initiates Leveling mode of all DRAMs by setting bit 7 of MR1 to 1. When entering write leveling mode, the DQ pins are in undefined driving mode. During write leveling mode, only NOP or DESELECT commands are allowed, as well as an MRS command to exit write leveling mode. Since the controller levels one rank at a time, the output of other ranks must be disabled by setting MR1 bit A12 to 1. The Controller may assert ODT after tMOD, at which time the DRAM is ready to accept the ODT signal. The Controller may drive DQS low and DQS# high after a delay of tWLDQSEN, at which time the DRAM has applied on-die termination on these signals. After tDQSL and tWLMRD, the controller provides a single DQS, DQS# edge which is used by the DRAM to sample CK - CK# driven from controller. tWLMRD(max) timing is controller dependent. DRAM samples CK - CK# status with rising edge of DQS - DQS# and provides feedback on the DQ bus asynchronously after tWLO timing. In this product, all data bits ("prime DQ bit(s)") which are DQ0~DQ7 for x8, or DQ0~DQ15 for x16, provide the leveling feedback. (Note: It is recommended that the controller rely solely on DQ0 for x8, or DQ0 and DQ8 for x16 for the prime DQ bits to maintain the broadest industry compatibility.) There are no remaining DQ bits. However, any remaining bits would be driven Low statically after the first sampling procedure. There is a DQ output uncertainty of tWLOE defined to allow mismatch on DQ bits. The tWLOE period is defined from the transition of the earliest DQ bit to the corresponding transition of the latest DQ bit. There are no read strobes (DQS/DQS#) needed for these DQs. Controller samples incoming DQ and decides to increment or decrement DQS - DQS# delay setting and launches the next DQS/DQS# pulse after some time, which is controller dependent. Once a 0 to 1 transition is detected, the controller locks DQS - DQS# delay setting and write leveling is achieved for the device. Figure 2.4.7.2 describes the timing diagram and parameters for the overall Write Leveling procedure. T1 T2 tWLH tWLS CK#(5) CK (2) CMD tWLH tWLS (3) MRS NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP tMOD ODT tWLDQSEN diff_DQS tDQSL(6) tDQSH(6) tDQSL(6) tDQSH(6) (4) tWLMRD tWLO tWLO (1) Prime DQ tWLO Late Remaining DQs Early Remaining DQs tWLO tWLOE Figure 2.4.7.2 Write leveling sequence [DQS - DQS# is capturing CK-CK# low at T1 and CK-CK# high at T2] Undefined Driving Mode Time Break DON’T CARE Notes: 1. The JEDEC specification for DDR3 DRAM has the option to drive leveling feedback on a single prime DQ or all DQs. For best compatibility with future DDR3 products, applications should use the lowest order DQ for each byte lane (DQ0 for x8, or DQ0 and DQ8 for x16). 2. MRS: Load MR1 to enter write leveling mode. 3. NOP: NOP or Deselect. 4. diff_DQS is the differential data strobe (DQS, DQS#). Timing reference points are the zero crossings. DQS is shown with solid line, DQS# is shown with dotted line. 5. CK, CK# : CK is shown with solid dark line, where as CK# is drawn with dotted line. 6. DQS, DQS# needs to fulfill minimum pulse width requirements tDQSH(min) and tDQSL(min) as defined for regular Writes; the max pulse width is system dependent. Integrated Silicon Solution, Inc. – www.issi.com – Rev. B1 06/25/2021 25 IS43/46TR16512B, IS43/46TR16512BL, IS43/46TR81024B, IS43/46TR81024BL 2.4.7.3 Write Leveling Mode Exit The following sequence describes how the Write Leveling Mode should be exited: 1. After the last rising strobe edge, stop driving the strobe signals. Note: From now on, DQ pins are in undefined driving mode, and will remain undefined, until tMOD after the respective MR command. 2. Drive ODT pin low (tIS must be satisfied) and continue registering low. 3. After the RTT is switched off, disable Write Level Mode via MRS command. 4. After tMOD is satisfied, any valid command may be registered. (MR commands may be issued after tMRD ). 2.4.8 Extended Temperature Usage a. Auto Self-refresh supported b. Extended Temperature Range supported c. Double refresh required for operation in the Extended Temperature Range (applies only for devices supporting the Extended Temperature Range) Mode Register Description Field Bits ASR MR2 (A6) SRT MR2 (A7) Description Auto Self-Refresh (ASR) when enabled, DDR3 SDRAM automatically provides Self-Refresh power management functions for all supported operating temperature values. If not enabled, the SRT bit must be programmed to indicate TOPER during subsequent Self-Refresh operation 0 = Manual SR Reference (SRT) 1 = ASR enable Self-Refresh Temperature (SRT) Range If ASR = 0, the SRT bit must be programmed to indicate TOPER during subsequent Self-Refresh operation If ASR = 1, SRT bit must be set to 0b 0 = Normal operating temperature range 1 = Extended operating temperature range 2.4.8.1 Auto Self-Refresh mode - ASR Mode DDR3 SDRAM provides an Auto Self-Refresh mode (ASR) for application ease. ASR mode is enabled by setting MR2 bit A6 = 1b and MR2 bit A7 = 0b. The DRAM will manage Self-Refresh entry in either the Normal or Extended (optional) Temperature Ranges. In this mode, the DRAM will also manage Self-Refresh power consumption when the DRAM operating temperature changes, lower at low temperatures and higher at high temperatures. If the ASR option is not supported by the DRAM, MR2 bit A6 must be set to 0b. If the ASR mode is not enabled (MR2 bit.A6 = 0b), the SRT bit (MR2 A7) must be manually programmed with the operating temperature range required during Self-Refresh operation. Support of the ASR option does not automatically imply support of the Extended Temperature Range. Refer to operating temperature range for restrictions on operating conditions. Integrated Silicon Solution, Inc. – www.issi.com – Rev. B1 06/25/2021 26 IS43/46TR16512B, IS43/46TR16512BL, IS43/46TR81024B, IS43/46TR81024BL 2.4.8.2 Self-Refresh Temperature Range - SRT SRT applies to devices supporting Extended Temperature Range only. If ASR = 0b, the Self-Refresh Temperature (SRT) Range bit must be programmed to guarantee proper self-refresh operation. If SRT = 0b, then the DRAM will set an appropriate refresh rate for Self-Refresh operation in the Normal Temperature Range. If SRT = 1b then the DRAM will set an appropriate, potentially different, refresh rate to allow Self-Refresh operation in either the Normal or Extended Temperature Ranges. The value of the SRT bit can effect self-refresh power consumption, please refer to the IDD table for details. For parts that do not support the Extended Temperature Range, MR2 bit A7 must be set to 0b and the DRAM should not be operated outside the Normal Temperature Range. Self-Refresh mode summary MR2 A[6] MR2 A[7] 0 0 Self-refresh rate appropriate for the Normal Temperature Range Normal (0 to 85 oC) 0 1 Self-refresh rate appropriate for either the Normal or Extended Temperature Ranges. The DRAM must support Extended Temperature Range. The value of the SRT bit can effect selfrefresh power consumption, please refer to the IDD table for details. Normal (0 to 85 oC) and Extended (85 to 105 oC) 1 0 ASR enabled (for devices supporting ASR and Normal Temperature Range). Self-Refresh power consumption is temperature dependent Normal (0 to 85 oC) 1 0 ASR enabled (for devices supporting ASR and Extended Temperature Range). Self-Refresh power consumption is temperature dependent Normal (0 to 85 oC) and Extended (85 to 105 oC) 1 1 Illegal Self-Refresh operation Allowed Operating Temperature Range for SelfRefresh Mode Note: Self-Refresh Mode operation above 95ºC permitted only for Automotive grades (A2 and A25 as long as below 105°C); refer to 3.2 Component Operating Temperature Range. Integrated Silicon Solution, Inc. – www.issi.com – Rev. B1 06/25/2021 27 IS43/46TR16512B, IS43/46TR16512BL, IS43/46TR81024B, IS43/46TR81024BL 3. Absolute Maximum Ratings and AC & DC Operating Conditions 3.1 Absolute Maximum DC Ratings. Symbol Parameter Rating Units Note VDD Voltage on VDD pin relative to Vss -0.4 V ~ 1.975 V V 1,3 VDDQ Voltage on VDDQ pin relative to Vss -0.4 V ~ 1.975 V V 1,3 VIN, VOUT Voltage on any pin relative to Vss -0.4 V ~ 1.975 V V 1 TSTG Storage Temperature -55 to +150 °C 1,2 Notes: 1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions. 3. VDD and VDDQ must be within 300 mV of each other at all times; and VREF must be not greater than 0.6 x VDDQ, When VDD and VDDQ are less than 500 mV; VREF may be equal to or less than 300 mV 3.2 Component Operating Temperature Range Symbol Parameter Rating Tc = 0 to 85 Tc = 85 to 95 Tc = -40 to 85 Tc = 85 to 95 Tc = -40 to 85 Tc = 85 to 95 Tc = -40 to 85 Tc = 85 to 95 Tc = 95 to 105 Tc = -40 to 85 Tc = 85 to 95 Tc = 95 to 105 Tc = 105 to 115 Commercial Industrial TOPER Automotive (A1) Automotive (A2) Automotive (A25) Units °C °C °C °C °C °C °C °C °C °C °C °C °C Notes 1,2 1,3 1,2 1,3 1,2 1,3 1,2 1,3 1,3 1,2 1,3 1,3 1,4 Notes: 1. Operating Temperature TOPER is the case surface temperature (Tc) on the center / top side of the DRAM. 2. This temperature range specifies the temperatures where all DRAM specifications will be supported. During operation, the DRAM case temperature must be maintained in this range under all operating conditions. 3. Some applications require operation of the DRAM in the Extended Temperature Range (85°C < Tc  105°C). Full specifications are supported in this range, but the following additional conditions apply: a ) Refresh commands must be doubled in frequency, therefore reducing the Refresh interval tREFI to 3.9 µs. b) If Self-Refresh operation is required for this range, it is mandatory to use either the Manual Self-Refresh mode with Extended Temperature Range capability (MR2 A6 = 0b and MR2 A7 = 1b) or enable the Auto Self-Refresh mode (MR2 A6 = 1b and MR2 A7 = 0b). 4. Same as note 3, except part (b). No type of Self-Refresh is supported for this range. 3.3 Recommended DC Operating Conditions Symbol Parameter VDD Supply Voltage VDDQ Supply Voltage for Output DDR3 DDR3L DDR3 DDR3L Min 1.425 1.283 1.425 1.283 Rating Typ 1.5 1.35 1.5 1.35 Max 1.575 1.45 1.575 1.45 Unit Notes V V V V 1,2 1,2,3,4,5,6,7 1,2 1,2,3,4,5,6,7 Notes: 1. Under all conditions VDDQ must be less than or equal to VDD. 2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together. 3. Maximum DC value may not be greater than 1.425V. The DC value is the linear average of VDD/VDD (t) over a long period of time. 4. If the maximum limit is exceeded, the input levels are covered by the DDR3 specification. 5. With these supply voltages, the device operates with DDR3L specifications. 6. After initialized for DDR3 operation, the DDR3L may be used only upon reset. 7. The DDR3L product supports 1.5V operation, and if initialized as such, retains the original speed timing defined for DDR3L speed. Integrated Silicon Solution, Inc. – www.issi.com – Rev. B1 06/25/2021 28 IS43/46TR16512B, IS43/46TR16512BL, IS43/46TR81024B, IS43/46TR81024BL 3.4. Thermal Resistance Package Substrate 78-ball 96-ball 4-layer 4-layer Theta-ja (Airflow = 0m/s) 31.5 29.4 Theta-ja (Airflow = 1m/s) 27.1 25.2 Theta-ja (Airflow = 2m/s) 24.5 22.8 Theta-jc Units 2.6 2.6 C/W C/W 4. AC & DC INPUT MEASUREMENT LEVELS 4.1. AC and DC Logic Input Levels for Single-Ended Signals 4.1.1 AC and DC Input Levels for Single-Ended Command and Address Signals Symbol Parameter VIH.CA(DC100) DDR3-800/1066/1333/1600 DDR3-1866/2133 Units Note Min. Max. Min. Max. V 1 DC input logic high Vref + 0.100 VDD Vref + 0.100 VDD V 1 VIL.CA(DC100) DC input logic low VSS Vref - 0.100 VSS Vref - 0.100 V 1, 2, 5 VIH.CA(AC175) AC input logic high Vref + 0.175 Note2 -- -- V 1, 2, 5 VIL.CA(AC175) AC input logic low Note2 Vref - 0.175 -- -- V 1, 2, 5 VIH.CA(AC150) AC input logic high Vref + 0.150 Note2 -- -- V 1, 2, 5 VIL.CA(AC150) AC input logic low Note2 Vref - 0.150 -- -- V 1, 2, 5 VIH.CA(AC135) AC input logic high -- -- Vref + 0.135 Note2 V 1, 2, 5 VIL.CA(AC135) AC input logic low -- -- Note2 Vref - 0.135 V 1, 2, 5 VIH.CA(AC125) AC input logic high -- -- Vref + 0.125 Note2 V 1, 2, 5 VIL.CA(AC125) AC input logic low Reference Voltage for ADD, CMD inputs -- -- Note2 Vref - 0.125 V 1, 2, 5 0.49 * VDD 0.51* VDD 0.49 * VDD 0.51* VDD V 3, 4 VREFCA(DC) DDR3L-800/1066/1333/1600 DDR3L-1866 Units Note Min. Max. Min. Max. V 1 DC input logic high Vref + 0.09 VDD Vref + 0.09 VDD V 1 VIL.CA(DC90) DC input logic low VSS Vref - 0.09 VSS Vref - 0.09 V 1, 2, 5 VIH.CA(AC160) AC input logic high Vref + 0.16 Note2 -- -- V 1, 2, 5 VIL.CA(AC160) AC input logic low Note2 Vref - 0.160 -- -- V 1, 2, 5 VIH.CA(AC135) AC input logic high Vref + 0.135 Note2 Vref + 0.135 Note2 V 1, 2, 5 VIL.CA(AC135) AC input logic low Note2 Vref - 0.135 Note2 Vref - 0.135 V 1, 2, 5 VIH.CA(AC125) AC input logic high -- -- Vref + 0.125 Note2 V 1, 2, 5 VIL.CA(AC125) AC input logic low Reference Voltage for ADD, CMD inputs -- -- Note2 Vref - 0.125 V 1, 2, 5 0.49 * VDD 0.51* VDD 0.49 * VDD 0.51* VDD V 3, 4 Symbol Parameter VIH.CA(DC90) VREFCA(DC) Notes: 1. For input only pins except RESET.Vref=VrefCA(DC) 2. See "Overshoot and Undershoot Specifications" 3. The ac peak noise on Vref may not allow Vref to deviate from Vref(DC) by more than +/- 1.0% VDD. 4. For reference: DDR3 has approx. VDD/2 +/- 15mV, DDR3L has approx VDD/2 +/- 13.5mV. 5. To allow VREFCA margining, all DRAM Command and Address Input Buffers MUST use external VREF (provided by system) as the input for their VREFCA pins. All VIH/L input level MUST be compared with the external VREF level at the 1st stage of the Command and Address input buffer Integrated Silicon Solution, Inc. – www.issi.com – Rev. B1 06/25/2021 29 IS43/46TR16512B, IS43/46TR16512BL, IS43/46TR81024B, IS43/46TR81024BL 4.1.2 AC and DC Logic Input Levels for Single-Ended Signals & DQ and DM Symbol Parameter DDR3-800/1066 DDR3-1333/1600 DDR3-1866/2133 Min. Max. Min. Max. Min. Units Note Max. V 1 VIH.DQ(DC100) DC input logic high Vref + 0.100 VDD Vref + 0.100 VDD Vref + 0.100 VDD V 1 VIL.DQ(DC100) DC input logic low VSS Vref 0.100 VSS Vref 0.100 VSS Vref 0.100 V 1, 2, 5 VIH.DQ(AC175) AC input logic high Vref + 0.175 Note2 -- -- -- -- V 1, 2, 5 VIL.DQ(AC175) AC input logic low Note2 Vref 0.175 -- -- -- -- V 1, 2, 5 VIH.DQ(AC150) AC input logic high Vref + 0.150 Note2 Vref + 0.150 Note2 -- -- V 1, 2, 5 VIL.DQ(AC150) AC input logic low Note2 Vref 0.150 Note2 Vref 0.150 -- -- V 1, 2, 5 VIH.DQ(AC135) AC input logic high Vref + 0.135 Note2 Vref + 0.135 Note2 Vref + 0.135 Note2 V 1, 2, 5 VIL.DQ(AC135) AC input logic low Note2 Vref 0.135 Note2 Vref 0.135 Note2 Vref 0.135 V 1, 2, 5 VREFDQ(DC) Reference Voltage for DQ, DM inputs 0.49 * VDD 0.51* VDD 0.49 * VDD 0.51* VDD 0.49 * VDD 0.51* VDD V 3, 4 Integrated Silicon Solution, Inc. – www.issi.com – Rev. B1 06/25/2021 30 IS43/46TR16512B, IS43/46TR16512BL, IS43/46TR81024B, IS43/46TR81024BL Symbol Parameter DDR3L-800/1066 DDR3L-1333/1600 DDR3L-1866 Units Note Min. Max. Min. Max. Min. Max. V 1 VIH.DQ(DC90) DC input logic high Vref + 0.09 VDD Vref + 0.09 VDD Vref + 0.09 VDD V 1 VIL.DQ(DC90) DC input logic low VSS Vref 0.09 VSS Vref 0.09 VSS Vref 0.09 V 1, 2, 5 VIH.DQ(AC160) AC input logic high Vref + 0.16 Note2 Vref + 0.16 Note2 -- -- V 1, 2, 5 VIL.DQ(AC160) AC input logic low Note2 Vref 0.16 Note2 Vref 0.16 -- -- V 1, 2, 5 VIH.DQ(AC135) AC input logic high Vref + 0.135 Note2 Vref + 0.135 Note2 Vref + 0.135 Note2 V 1, 2, 5 VIL.DQ(AC135) AC input logic low Note2 Vref 0.135 Note2 Vref 0.135 Note2 Vref 0.135 V 1, 2, 5 VIH.DQ(AC130) AC input logic high -- -- -- -- Vref + 0.13 Note2 V 1, 2, 5 VIL.DQ(AC130) AC input logic low -- -- -- -- Note2 Vref 0.13 V 1, 2, 5 VREFDQ(DC) Reference Voltage for DQ, DM inputs 0.49 * VDD 0.51* VDD 0.49 * VDD 0.51* VDD 0.49 * VDD 0.51* VDD V 3, 4 Notes: 1. For input only pins except RESET#. Vref = VrefDQ(DC) 2. See "Overshoot and Undershoot Specifications" 3. The ac peak noise on Vref may not allow Vref to deviate from Vref(DC) by more than ± 1.0% VDD. 4. For reference: DDR3 has approx. VDD/2 ±15mV, and DDR3L has approx. VDD/2 ± 13.5mV. 5. Single-ended swing requirement for DQS-DQS#, is 350mV (peak to peak). Differential swing requirement for DQS-DQS#, is 700mV (peak to peak) Integrated Silicon Solution, Inc. – www.issi.com – Rev. B1 06/25/2021 31 IS43/46TR16512B, IS43/46TR16512BL, IS43/46TR81024B, IS43/46TR81024BL 4.2 Vref Tolerances The dc-tolerance limits and ac-moist limits for the reference voltages VrefCA and VrefDQ are illustrated in the following figure. It shows a valid reference voltage Vref(t) as a function of time. (Vref stands for VrefCA and VrefDQ likewise). Vref(DC) is the linear average of Vref(t) over a very long period of time (e.g.,1 sec). This average has to meet the min/max requirement in previous page. Furthermore Vref(t) may temporarily deviate from Vref(DC) by no more than ±1% VDD. The voltage levels for setup and hold time measurements VIH(AC), VIH(DC), VIL(AC), and VIL(DC) are dependent on Vref. “Vref” shall be understood as Vref(DC). The clarifies that dc-variations of Vref affect the absolute voltage a signal has to reach to achieve a valid high or low level and therefore the time to which setup and hold is measured. System timing and voltage budgets need to account for Vref(DC) deviations from the optimum position within the data-eye of the input signals. This also clarifies that the DRAM setup/hold specification and de-rating values need to include time and voltage associated with Vref ac-noise. Timing and voltage effects due to ac-noise on Vref up to the specified limit (±1% of VDD) are included in DRAM timing and their associated de-ratings. Figure 4.2 Illustration of Vref(DC) tolerance and Vrefac-noise limits Voltage VDD Vref ac-noise Vref(D C) Vref(t) Vref(DC) max Vref(DC) min VSS time Integrated Silicon Solution, Inc. – www.issi.com – Rev. B1 06/25/2021 32 IS43/46TR16512B, IS43/46TR16512BL, IS43/46TR81024B, IS43/46TR81024BL 4.3. AC and DC Logic Input Levels for Differential Signals 4.3.1 Differential signal definition Differential Input Voltage (i.e. DQS–DQS#, CK–CK#) Figure 4.3.1 Definition of differential ac-swing and “time above ac-level” tDVAC VIH.DIFF.AC.MIN VIH.DIFF.MIN Half cycle VIL.DIFF.MAX VIL.DIFF.AC.MAX tDVAC time 4.3.2 Differential swing requirements for clock (CK - CK#) and strobe (DQS - DQS#) 4.3.2.1 Differential AC and DC Input Levels Symbol Parameter VIHdiff Differential input logic high VILdiff VIHdiff(ac) VILdiff(ac) Differential input logic low Differential input high ac Differential input low ac Symbol Parameter VIHdiff Differential input logic high VILdiff VIHdiff(ac) VILdiff(ac) Differential input logic low Differential input high ac Differential input low ac DDR3-800, 1066, 1333, 1600, 1866, 2133 Min Max +0.200 Note3 Note3 2 x ( VIH(ac) – Vref ) Note3 -0.200 Note3 2 x ( Vref - VIL(ac) ) DDR3L-800, 1066, 1333, 1600, 1866 Min Max +0.180 Note3 Note3 2 x ( VIH(ac) – Vref ) Note3 -0.180 Note3 2 x ( Vref - VIL(ac) ) unit Notes V 1 V V V 1 2 2 unit Notes V 1 V V V 1 2 2 Notes: 1. Used to define a differential signal slew-rate. 2. For CK - CK# use VIH/VIL(ac) of ADD/CMD and VREFCA; for DQS - DQS#, DQSL, DQSL#, DQSU, DQSU# use VIH/VIL(ac) of DQs and VREFDQ; if a reduced ac-high or ac-low level is used for a signal group, then the reduced level applies also here. 3. These values are not defined; however, the single-ended signals CK, CK#, DQS, DQS#, DQSL, DQSL#, DQSU, DQSU# need to be within the respective limits (VIH(dc) max, VIL(dc)min) for single-ended signals as well as the limitations for overshoot and undershoot. Integrated Silicon Solution, Inc. – www.issi.com – Rev. B1 06/25/2021 33 IS43/46TR16512B, IS43/46TR16512BL, IS43/46TR81024B, IS43/46TR81024BL 4.3.2.2 Minimum required time before ringback (tDVAC) for CK - CK# and DQS - DQS# DDR3-800/1066/1333/1600 Slew Rate [V/ns] DDR3-1866/2133 tDVAC [ps] @ |VIH/Ldiff(AC)| = 350mV tDVAC [ps] @ |VIH/Ldiff(AC)| = 300mV tDVAC [ps] @ |VIH/Ldiff(AC)| = (DQS - DQS#) only tDVAC [ps] @ |VIH/Ldiff(AC)| = 300mV tDVAC [ps] @ |VIH/Ldiff(AC)| = (CK - CK#) only > 4.0 75 175 214 134 139 4 57 170 214 134 139 3 50 167 191 112 118 2 38 119 146 67 77 1.8 34 102 131 52 63 1.6 29 81 113 33 45 1.4 22 54 88 9 23 1.2 Note 19 56 Note Note 1 Note Note 11 Note Note 4.0 189 201 163 168 176 4 189 201 163 168 176 3 162 179 140 147 154 2 109 134 95 105 111 1.8 91 119 80 91 97 1.6 69 100 62 74 78 1.4 40 76 37 52 56 1.2 Note 44 5 22 24 1 Note Note Note Note Note 25 mV and VSEH – ((VDD/2) + Vix (max.)) > 25mV. 4.5 Slew Rate Definitions for Single-Ended Input Signals See “Address / Command Setup, Hold and Derating” for single-ended slew rate definitions for address and command signals. See “Data Setup, Hold and Slew Rate Derating” for single-ended slew rate definitions for data signals. Integrated Silicon Solution, Inc. – www.issi.com – Rev. B1 06/25/2021 36 IS43/46TR16512B, IS43/46TR16512BL, IS43/46TR81024B, IS43/46TR81024BL 4.6. Slew Rate Definition for Differential Input Signals 4.6.1 Differential Input Slew Rate Definition Description Differential input slew rate for rising edge (CK-CK# & DQSDQS#) Differential input slew rate for falling edge (CK-CK# & DQSDQS#) Measured From To Defined by VILdiffmax VIHdiffmin [VIHdiffmin-VILdiffmax] / DeltaTRdiff VIHdiffmin VILdiffmax [VIHdiffmin-VILdiffmax] / DeltaTFdiff Differential Input Voltage(i.e. DQS-DQS#, CK-CK#) Note : The differential signal (i.e., CK-CK# & DQS-DQS#) must be linear between these thresholds. Figure 4.6.1 Input Nominal Slew Rate Definition for DQS, DQS# and CK, CK# Integrated Silicon Solution, Inc. – www.issi.com – Rev. B1 06/25/2021 37 IS43/46TR16512B, IS43/46TR16512BL, IS43/46TR81024B, IS43/46TR81024BL 5. AC AND DC OUTPUT MEASUREMENT LEVELS 5.1 Single Ended AC and DC Output Levels Symbol VOH(DC) VOM(DC) VOL(DC) VOH(AC) VOL(AC) Parameter DC output high measurement level (for IV curve linearity) DC output mid measurement level (for IV curve linearity) DC output low measurement level (fro IV curve linearity) AC output high measurement level (for output SR) AC output low measurement level (for output SR) Value 0.8xVDDQ 0.5xVDDQ 0.2xVDDQ VTT+0.1xVDDQ VTT-0.1xVDDQ Unit V V V V V Notes 1 1 NOTE 1. The swing of ± 0.1 × VDDQ is based on approximately 50% of the static single-ended output high or low swing with a driver impedance of 40 and an effective test load of 25 to VTT = VDDQ/2. 5.2 Differential AC and DC Output Levels Symbol VOHdiff(AC) VOLdiff(AC) Parameter AC differential output high measurement level (for output SR) AC differential output low measurement level (for output SR) Value +0.2 x VDDQ -0.2 x VDDQ Unit V V Notes 1 1 NOTE 1. The swing of ± 0.2 × VDDQ is based on approximately 50% of the static single-ended output high or low swing with a driver impedance of 40 and an effective test load of 25 to VTT = VDDQ/2 at each of the differential outputs. 5.3 Single Ended Output Slew Rate 5.3.1 Single Ended Output Slew Rate Definition Description Defined by [VOH(AC)-VOL(AC)] / DeltaTRse [VOH(AC)-VOL(AC)] / DeltaTFse Single Ended Output Voltage(i.e. DQ) Single ended output slew rate for rising edge Single ended output slew rate for falling edge Measured From To VOL(AC) VOH(AC) VOH(AC) VOL(AC) Figure 5.3.1 Single Ended Output Slew Rate Definition 5.3.2 Output Slew Rate (single-ended) Parameter Singleended Output Slew Rate Symbol DDR3 DDR3L DDR3-800 Min. Max. DDR3-1066 Min. Max. DDR3-1333 Max. Max. DDR3-1600 Max. Max. DDR3-1866 Max. Max. DDR3-2133 Max. Max. 2.5 5 2.5 5 2.5 5 2.5 5 2.5 5 2.5 5 1.75 5 1.75 5 1.75 5 1.75 5 1.75 5 1.75 5 SRQse Unit V/ns Note: SR: Slew Rate. Q: Query Output (like in DQ, which stands for Data-in, Query -Output). se: Single-ended signals. For Ron = RZQ/7 setting. Integrated Silicon Solution, Inc. – www.issi.com – Rev. B1 06/25/2021 38 IS43/46TR16512B, IS43/46TR16512BL, IS43/46TR81024B, IS43/46TR81024BL 5.4 Differential Output Slew Rate 5.4.1 Differential Output Slew Rate Definition Measured Description From VOLdiff(AC) VOHdiff(AC) Differential output slew rate for rising Differential output slew rate for falling Defined by To VOHdiff(AC) VOLdiff(AC) [VOHdiff(AC)-VOLdiff(AC)]/DeltaTRdiff [VOHdiff(AC)-VOLdiff(AC)]/DeltaTFdiff Note: Output slew rate is verified by design and characterization, and not 100% tested in production. Figure 5.4.1 Differential Output Slew Rate Definition 5.4.2 Differential Output Slew Rate Parameter Differential Output DDR3-800 Min. Max. Symbol DDR3 DDR3L SRQdiff Slew Rate DDR3-1066 Min. Max. DDR3-1333 Max. Max. DDR3-1600 Max. Max. DDR3-1866 Max. Max. DDR3-2133 Max. Max. 5 10 5 10 5 10 5 10 5 10 5 10 3.5 12 3.5 12 3.5 12 3.5 12 3.5 12 3.5 12 Unit V/ns Description: SR: Slew Rate, Q: Query Output (like in DQ, which stands for Data-in, Query-Output), diff: Differential Signals, For Ron = RZQ/7 setting 5.5 Reference Load for AC Timing and Output Slew Rate The following figure represents the effective reference load of 25 ohms used in defining the relevant AC timing parameters of the device as well as output slew rate measurements. It is not intended as a precise representation of any particular system environment or a depiction of the actual load presented by a production tester. System designers should use IBIS or other simulation tools to correlate the timing reference load to a system environment. Manufacturers correlate to their production test conditions, generally one or more coaxial transmission lines terminated at the tester electronics. VDDQ DUT CK,CK# 25ohm DQ, DQS, DQS# VTT=VDDQ/2 Timing Reference Point Figure 5.5 Reference Load for AC Timing and Output Slew Rate Integrated Silicon Solution, Inc. – www.issi.com – Rev. B1 06/25/2021 39 IS43/46TR16512B, IS43/46TR16512BL, IS43/46TR81024B, IS43/46TR81024BL 5.6 Overshoot and Undershoot Specifications 5.6.1 AC Overshoot/Undershoot Specification for Address and Control Pins Item Maximum peak amplitude allowed for overshoot area Maximum peak amplitude allowed for undershoot area Maximum overshoot area above VDD undershoot area below VSS DDR3800 DDR31066 DDR31333 DDR31600 DDR31866 DDR32133 Units 0.4 0.4 0.4 0.4 0.4 0.4 V 0.4 0.4 0.4 0.4 0.4 0.4 V 0.67 0.67 0.5 0.5 0.4 0.4 0.33 0.33 0.28 0.28 0.25 0.25 V-ns V-ns Note: A0-A13, BA0-BA2, CS#, RAS#, CAS#, WE#, CKE, ODT Maximum Amplitude Volts(V) Overshoot Area VDD VSS Undershoot Area Maximum Amplitude Time(ns) 5.6.2 AC Overshoot/Undershoot Specification for Clock, Data, Strobe, and Mask Item Maximum peak amplitude allowed for overshoot area Maximum peak amplitude allowed for undershoot area Maximum overshoot area above VDD undershoot area below VSS DDR3800 DDR31066 DDR31333 DDR31600 DDR31866 DDR32133 Units 0.4 0.4 0.4 0.4 0.4 0.4 V 0.4 0.4 0.4 0.4 0.4 0.4 V 0.25 0.25 0.19 0.19 0.15 0.15 0.13 0.13 0.11 0.11 0.10 0.10 V-ns V-ns Note: CK, CK#, DQ, DQS, DQS#, DM Maximum Amplitude Volts(V) Overshoot Area VDDQ VSSQ Maximum Amplitude Time(ns) Integrated Silicon Solution, Inc. – www.issi.com – Rev. B1 06/25/2021 40 IS43/46TR16512B, IS43/46TR16512BL, IS43/46TR81024B, IS43/46TR81024BL 5.7 34Ohm Output Driver DC Electrical Characteristics A Functional representation of the output buffer is shown as below. Output driver impedance RON is defined by the value ofthe external reference resistor RZQ as follows: RON34 = RZQ / 7 (nominal 34.4ohms +/-10% with nominal RZQ=240ohms) The individual pull-up and pull-down resistors (RONPu and RONPd) are defined as follows: RONPu = [VDDQ-Vout] / | Iout | ------------------- under the condition that RONPd is turned off (1) RONPd = Vout / | Iout | -------------------------------under the condition that RONPu is turned off (2) Chip in Drive Mode Output Driver VDDQ To other circuitry IPu RONPu DQ Iout RONPd Vout IPd VSSQ Figure 5.7 Output Driver : Definition of Voltages and Currents 5.7.1 Output Driver DC Electrical Characteristics DDR3 (assuming 1.5V, RZQ = 240ohms; entire operating temperature range; after proper ZQ calibration) RONNom Resistor RON34Pd 34 ohms RON34Pu RON40Pd 40 ohms RON40Pu Mismatch between pull-up and pull-down, MMPuPd Integrated Silicon Solution, Inc. – www.issi.com – Rev. B1 06/25/2021 Vout VOLdc=0.2xVDDQ VOMdc=0.5xVDDQ VOHdc =0.8xVDDQ VOLdc=0.2xVDDQ VOMdc=0.5xVDDQ VOHdc=0.8xVDDQ Min 0.6 0.9 0.9 0.9 0.9 0.6 Nom 1 1 1 1 1 1 Max 1.1 1.1 1.4 1.4 1.1 1.1 Unit RZQ/7 RZQ/7 RZQ/7 RZQ/7 RZQ/7 RZQ/7 Notes 1,2,3 1,2,3 1,2,3 1,2,3 1,2,3 1,2,3 VOLdc=0.2xVDDQ 0.6 1 1.1 RZQ/6 1,2,3 VOMdc=0.5xVDDQ 0.9 1 1.1 RZQ/6 1,2,3 VOHdc =0.8xVDDQ 0.9 1 1.4 RZQ/6 1,2,3 VOLdc=0.2xVDDQ 0.9 1 1.4 RZQ/6 1,2,3 VOMdc=0.5xVDDQ 0.9 1 1.1 RZQ/6 1,2,3 VOHdc=0.8xVDDQ 0.6 1 1.1 RZQ/6 1,2,3 VOMdc= 0.5xVDDQ -10 +10 % 1,2,4 41 IS43/46TR16512B, IS43/46TR16512BL, IS43/46TR81024B, IS43/46TR81024BL DDR3L (assuming 1.35V, RZQ = 240ohms; entire operating temperature range; after proper ZQ calibration) RONNom Resistor Vout VOLdc=0.2xVDDQ Min 0.6 Nom 1 Max 1.15 Unit RZQ/7 Notes 1,2,3 RON34Pd VOMdc=0.5xVDDQ VOHdc =0.8xVDDQ VOLdc=0.2xVDDQ VOMdc=0.5xVDDQ VOHdc=0.8xVDDQ 0.9 0.9 0.9 0.9 0.6 1 1 1 1 1 1.15 1.45 1.45 1.15 1.15 RZQ/7 RZQ/7 RZQ/7 RZQ/7 RZQ/7 1,2,3 1,2,3 1,2,3 1,2,3 1,2,3 VOLdc=0.2xVDDQ 0.6 1 1.15 RZQ/6 1,2,3 34 ohms RON34Pu RON40Pd 40 ohms RON40Pu Mismatch between pull-up and pull-down, MMPuPd VOMdc=0.5xVDDQ 0.9 1 1.15 RZQ/6 1,2,3 VOHdc =0.8xVDDQ 0.9 1 1.45 RZQ/6 1,2,3 VOLdc=0.2xVDDQ 0.9 1 1.45 RZQ/6 1,2,3 VOMdc=0.5xVDDQ 0.9 1 1.15 RZQ/6 1,2,3 VOHdc=0.8xVDDQ 0.6 1 1.15 RZQ/6 1,2,3 VOMdc= 0.5xVDDQ -10 +10 % 1,2,4 Notes: 1. The tolerance limits are specified after calibration with stable voltage and temperature. For the behavior of the tolerance limits if temperature or voltage changes after calibration, see following section on voltage and temperature sensitivity. 2. The tolerance limits are specified under the condition that VDDQ=VDD and that VSSQ=VSS. 3. Pull-down and pull-up output driver impedances are recommended to be calibrated at 0.5xVDDQ. Other calibration schemes may be used to achieve the linearity spec shown above, e.g. calibration at 0.2 * VDDQ and 0.8 x VDDQ. 4. Measurement definition for mismatch between pull-up and pull-down, MMPuPd: Measure RONPu and RONPd, both at 0.5 x VDDQ: MMPuPd = [RONPu - RONPd] / RONNom x 100 5.7.2 Output Driver Temperature and Voltage sensitivity If temperature and/or voltage after calibration, the tolerance limits widen according to the following table below. Delta T = T - T(@calibration); Delta V = VDDQ - VDDQ(@calibration); VDD = VDDQ 5.7.2.1 Output Driver Sensitivity Definition Items Min. Max. Unit RONPU@VOHdc 0.6 - dRONdTH*lDelta Tl - dRONdVH*lDelta Vl 1.1 + dRONdTH*lDelta Tl - dRONdVH*lDelta Vl RZQ/7 RON@VOMdc 0.9 - dRONdTM*lDelta Tl - dRONdVM*lDelta Vl 1.1 + dRONdTM*lDelta Tl - dRONdVM*lDelta Vl RZQ/7 RONPD@VOLdc 0.6 - dRONdTL*lDelta Tl - dRONdVL*lDelta Vl 1.1 + dRONdTL*lDelta Tl - dRONdVL*lDelta Vl RZQ/7 Note: dRONdT and dRONdV are not subject to production test but are verified by design and characterization. Integrated Silicon Solution, Inc. – www.issi.com – Rev. B1 06/25/2021 42 IS43/46TR16512B, IS43/46TR16512BL, IS43/46TR81024B, IS43/46TR81024BL 5.7.2.2 Output Driver Voltage and Temperature Sensitivity Speed Bin Items dRONdTM dRONdVM dRONdTL dRONdVL dRONdTH dRONdVH DDR3-800/1066/1333 Min. Max 0 1.5 0 0.15 0 1.5 0 0.15 0 1.5 0 0.15 DDR3-1600/1866/2133 Min. Max 0 1.5 0 0.13 0 1.5 0 0.13 0 1.5 0 0.13 Unit %/°C %/mV %/°C %/mV %/°C %/mV Note: dRONdT and dRONdV are not subject to production test but are verified by design and characterization. 5.8 On-Die Termination (ODT) Levels and I-V Characteristics 5.8.1 On-Die Termination (ODT) Levels and I-V Characteristics On-Die Termination effective resistance RTT is defined by bits A9, A6, and A2 of the MR1 Register. ODT is applied to the DQ, DM, DQS/DQS, and TDQS/TDQS (x8 devices only) pins. A functional representation of the on-die termination is shown in the following figure. The individual pull-up and pull-down resistors (RTTPu and RTTPd) are defined as follows: RTTPu = [VDDQ - Vout] / | Iout | ------------------ under the condition that RTTPd is turned off (3) RTTPd = Vout / | Iout | ------------------------------ under the condition that RTTPu is turned off (4) Chip in Termination Mode ODT VDDQ To other circuitry IPu Iout = Ipd -Ipu RTTPu DQ Iout RTTPd Vout IPd VSSQ Figure 5.8.1 On-Die Termination : Definition of Voltages and Currents 5.8.2 ODT DC Electrical Characteristics The following table provides an overview of the ODT DC electrical characteristics. The values for RTT60Pd120, RTT60Pu120, RTT120Pd240, RTT120Pu240, RTT40Pd80, RTT40Pu80, RTT30Pd60, RTT30Pu60, RTT20Pd40, RTT20Pu40 are not specification requirements, but can be used as design guide lines: Integrated Silicon Solution, Inc. – www.issi.com – Rev. B1 06/25/2021 43 IS43/46TR16512B, IS43/46TR16512BL, IS43/46TR81024B, IS43/46TR81024BL ODT DC Electrical Characteristics (assuming RZQ = 240ohms +/- 1% entire operating temperature range; after proper ZQ calibration) MR1 A9, A6, A2 RTT Resistor RTT120Pd240 0,1,0 120 RTT120Pu240 1 Unit Notes RZQ 1,2,3,4 0.5 x VDDQ 0.9 1 1.1 1.15 RZQ 1,2,3,4 VOHdc = 0.8 x VDDQ 0.9 1 1.4 1.45 RZQ 1,2,3,4 VOLdc = 0.2 x VDDQ 0.9 1 1.4 1.45 RZQ 1,2,3,4 0.5 x VDDQ 0.9 1 1.1 1.15 RZQ 1,2,3,4 RZQ RZQ/2 RZQ/2 RZQ/2 RZQ/2 1,2,3,4 1,2,5 1,2,3,4 1,2,3,4 1,2,3,4 RZQ/2 RZQ/2 RZQ/2 RZQ/4 RZQ/3 RZQ/3 RZQ/3 1,2,3,4 1,2,3,4 1,2,3,4 1,2,5 1,2,3,4 1,2,3,4 1,2,3,4 RZQ/3 RZQ/3 RZQ/3 RZQ/6 RZQ/4 RZQ/4 RZQ/4 1,2,3,4 1,2,3,4 1,2,3,4 1,2,5 1,2,3,4 1,2,3,4 1,2,3,4 RZQ/4 RZQ/4 RZQ/4 RZQ/8 RZQ/6 RZQ/6 RZQ/6 1,2,3,4 1,2,3,4 1,2,3,4 1,2,5 1,2,3,4 1,2,3,4 1,2,3,4 RZQ/6 RZQ/6 RZQ/6 RZQ/12 % 1,2,3,4 1,2,3,4 1,2,3,4 1,2,5 1,2,5,6 1.1 1.6 1.1 1.1 1.4 VOLdc = 0.2 x VDDQ 0.5 x VDDQ VOHdc = 0.8 x VDDQ VIL(ac) to VIH(ac) VOLdc = 0.2 x VDDQ 0.5 x VDDQ VOHdc = 0.8 x VDDQ 0.9 0.9 0.6 0.9 0.6 0.9 0.9 1 1 1 1 1 1 1 1.4 1.1 1.1 1.6 1.1 1.1 1.4 1.45 VOLdc = 0.2 x VDDQ 0.5 x VDDQ VOHdc = 0.8 x VDDQ VIL(ac) to VIH(ac) VOLdc = 0.2 x VDDQ 0.5 x VDDQ VOHdc = 0.8 x VDDQ 0.9 0.9 0.6 0.9 0.6 0.9 0.9 1 1 1 1 1 1 1 1.4 1.1 1.1 1.6 1.1 1.1 1.4 1.45 VOLdc = 0.2 x VDDQ 0.5 x VDDQ VOHdc = 0.8 x VDDQ VIL(ac) to VIH(ac) VOLdc = 0.2 x VDDQ 0.5 x VDDQ VOHdc = 0.8 x VDDQ 0.9 0.9 0.6 0.9 0.6 0.9 0.9 1 1 1 1 1 1 1 1.4 1.1 1.1 1.6 1.1 1.1 1.4 1.45 VOLdc = 0.2 x VDDQ RTT20Pu40 0.5 x VDDQ VOHdc = 0.8 x VDDQ RTT20 VIL(ac) to VIH(ac) Deviation of VM w.r.t VDDQ/2, DVM 0.9 0.9 0.6 0.9 -5 1 1 1 1 - 1.4 1.1 1.1 1.6 +5 1.45 60 RTT40Pd80 40 RTT40Pu80 RTT40 RTT30Pd60 30 RTT30Pu60 RTT30 RTT20Pd40 20 0.6 Max (DDR3L) 1.15 1 1 1 1 1 RTT60 1,0,0 VOLdc = 0.2 x VDDQ Max (DDR3) 1.1 0.6 0.9 0.6 0.9 0.9 RTT60Pu120 1,0,1 Nom VOHdc = 0.8 x VDDQ VIL(ac) to VIH(ac) VOLdc = 0.2 x VDDQ 0.5 x VDDQ VOHdc = 0.8 x VDDQ RTT60Pd120 0,1,1 Min 1.15 RTT120 0,0,1 Vout 1.65 1.15 1.15 1.45 1.15 1.15 1.65 1.15 1.15 1.45 1.15 1.15 1.65 1.15 1.15 1.45 1.15 1.15 1.65 1.15 1.15 1.45 1.15 1.15 1.65 +5 Notes: 1. The tolerance limits are specified after calibration with stable voltage and temperature. For the behavior of the tolerance limits if temperature or voltage changes after calibration, see following section on voltage and temperature sensitivity. 2. The tolerance limits are specified under the condition that VDDQ = VDD and that VSSQ = VSS. 3. Pull-down and pull-up ODT resistors are recommended to be calibrated at 0.5 x VDDQ. Other calibration schemes may be used to achieve the linearity spec shown above. 4. Not a specification requirement, but a design guide line. 5. Measurement definition for RTT: Apply VIH(ac) to pin under test and measure current I(VIH(ac)), then apply VIL(ac) to pin under test and measure current I(VIL(ac)) respectively. RTT = [VIH(ac) - VIL(ac)] / [I(VIH(ac)) - I(VIL(ac))] 6. Measurement definition for VM and DVM: Measure voltage (VM) at test pin (midpoint) with no load: Delta VM = [2VM / VDDQ -1] x 100 Integrated Silicon Solution, Inc. – www.issi.com – Rev. B1 06/25/2021 44 IS43/46TR16512B, IS43/46TR16512BL, IS43/46TR81024B, IS43/46TR81024BL 5.8.3 ODT Temperature and Voltage sensitivity If temperature and/or voltage after calibration, the tolerance limits widen according to the following table. Delta T = T - T(@calibration); Delta V = VDDQ - VDDQ(@calibration); VDD = VDDQ 5.8.3.1 ODT Sensitivity Definition RTT min 0.9 - dRTTdT*lDelta Tl - dRTTdV*lDelta Vl max 1.6 + dRTTdT*lDelta Tl + dRTTdV*lDelta Vl Unit RZQ/2,4,6,8,12 5.8.3.2 ODT Voltage and Temperature Sensitivity dRTTdT dRTTdV Min 0 0 Max 1.5 0.15 Unit %/°C %/mV Note: These parameters may not be subject to production test. They are verified by design and characterization 5.9 ODT Timing Definitions 5.9.1 Test Load for ODT Timings Different than for timing measurements, the reference load for ODT timings is defined in the following figure. VDDQ DUT CK,CK# DQ,DM DQS, DQS#, TDQS, TDQS# 25ohm VTT=VSSQ VSSQ Timing Reference Point Figure 5.9.1 ODT Timing Reference Load 5.9.2 ODT Timing Definitions Definitions for tAON, tAONPD, tAOF, tAOFPD, and tADC are provided in the following table and subsequent figures. Symbol tAON tAONPD tAOF tAOFPD tADC Begin Point Definition Rising edge of CK - CK defined by the end point of ODTLon Rising edge of CK - CK with ODT being first registered high Rising edge of CK - CK defined by the end point of ODTLoff Rising edge of CK - CK with ODT being first registered low Rising edge of CK - CK defined by the end point of ODTLcnw, ODTLcwn4, or ODTLcwn8 Integrated Silicon Solution, Inc. – www.issi.com – Rev. B1 06/25/2021 End Point Definition Extrapolated point at VSSQ Extrapolated point at VSSQ End point: Extrapolated point at VRTT_Nom End point: Extrapolated point at VRTT_Nom End point: Extrapolated point at VRTT_Wr and VRTT_Nom respectively 45 IS43/46TR16512B, IS43/46TR16512BL, IS43/46TR81024B, IS43/46TR81024BL Reference Settings for ODT Timing Measurements Measured Parameter RTT_Nom Setting RZQ/4 RZQ/12 RZQ/4 RZQ/12 RZQ/4 RZQ/12 RZQ/12 RZQ/12 tAON tAONPD tAOFPD tADC DDR3 DDR3L RTT_Wr Setting NA NA NA NA NA NA RZQ/2 RZQ/2 VSW1[V] 0.05 0.10 0.05 0.10 0.05 0.10 0.20 0.20 VSW2[V] 0.10 0.20 0.10 0.20 0.10 0.20 0.30 0.25 Figure 5.9.2.1 Definition of tAON Begin Point : Rising edge of CK-CK# defined by the end of ODTLon CK VTT CK# tAON Tsw2 Tsw1 DQ,DM,DQS, DQS#,TDQS, TDQS# Vsw2 Vsw1 VSSQ End Point : Extrapolated point at VSSQ Figure 5.9.2.2 Definition of tAONPD Begin Point : Rising edge of CK-CK# with ODT being first register high CK VTT CK# tAONPD Tsw2 Tsw1 DQ,DM,DQS, DQS#,TDQS, TDQS# Integrated Silicon Solution, Inc. – www.issi.com – Rev. B1 06/25/2021 Vsw2 Vsw1 VSSQ End Point : Extrapolated point at VSSQ 46 IS43/46TR16512B, IS43/46TR16512BL, IS43/46TR81024B, IS43/46TR81024BL Figure 5.9.2.3 Definition of tAOF Begin Point : Rising edge of CK-CK# with defined by the end point of ODTLoff CK VTT CK# tAOF VRTT_NOM End Point : Extrapolated point at VRTT_NOM Tsw2 Tsw1 Vsw2 DQ,DM,DQS, DQS#,TDQS, TDQS# Vsw1 VSSQ Figure 5.9.2.4 Definition of tAOFPD Begin Point : Rising edge of CK-CK# with ODT being first registered low CK VTT CK# tAOFPD VRTT_NOM End Point : Extrapolated point at VRTT_NOM Tsw2 DQ,DM,DQS, DQS#,TDQS, TDQS# Integrated Silicon Solution, Inc. – www.issi.com – Rev. B1 06/25/2021 Tsw1 Vsw2 Vsw1 VSSQ 47 IS43/46TR16512B, IS43/46TR16512BL, IS43/46TR81024B, IS43/46TR81024BL Figure 5.9.2.5 Definition of tADC Begin Point : Rising edge of CK-CK# defined by the end point of ODTLcnw Begin Point : Rising edge of CK-CK# defined by the end point of ODTLcwn4 or ODTLcwn8 CK VTT CK# tADC tADC VRTT_NOM DQ,DM,DQS, DQS#,TDQS, TDQS# Tsw21 End Point : Extrapolated Tsw11 point at VRTT_NOM Tsw22 Vsw2 Tsw12 VRTT_Wr Vsw1 End Point : Extrapolated point at VRTT_Wr VSSQ Integrated Silicon Solution, Inc. – www.issi.com – Rev. B1 06/25/2021 48 IS43/46TR16512B, IS43/46TR16512BL, IS43/46TR81024B, IS43/46TR81024BL 6. INPUT / OUTPUT CAPACITANCE Symbol CIO DDR3/ DDR3L-800 Min Max Parameter Input/output capacitance (DQ, DM, DQS, DQS#,TDQS,TDQS#) DDR3 DDR3L 1.4 3 DDR3/ DDR3L-1066 Min Max 1.4 2.7 DDR3/ DDR3L-1333 Min Max 1.4 2.5 DDR3/ DDR3L-1600 Min Max 1.4 2.3 DDR3/ DDR3L-1866 Min Max 1.4 2.2 DDR3-2133 Min Max 1.4 2.1 Units Notes pF 1,2,3 1.4 2.5 1.4 2.5 1.4 2.3 1.4 2.2 1.4 2.1 - - 0.8 1.6 0.8 1.6 0.8 1.4 0.8 1.4 0.8 1.3 0.8 1.3 pF 2,3 CCK Input capacitance, CK and CK# CDCK Input capacitance delta, CK and CK# 0 0.15 0 0.15 0 0.15 0 0.15 0 0.15 0 0.15 pF 2,3,4 CDDQS Input/output capacitance delta, DQS and DQS# 0 0.15 0 0.15 0 0.15 0 0.15 0 0.15 0 0.15 pF 2,3,5 0.75 1.4 0.75 1.35 0.75 1.3 0.75 1.3 0.75 1.2 0.75 1.2 pF 2,3,7, 8 CI CDI_CTRL CDI_ADD_C MD Input capacitance, CTRL, ADD, command input-only pins DDR3 DDR3L Input capacitance delta, all CTRL input-only pins Input capacitance delta, all ADD/CMD input-only pins 0.75 1.3 0.75 1.3 0.75 1.3 0.75 1.2 0.75 1.2 - - -0.5 0.3 -0.5 0.3 -0.4 0.2 -0.4 0.2 -0.4 0.2 -0.4 0.2 pF -0.5 0.5 -0.5 0.5 -0.4 0.4 -0.4 0.4 -0.4 0.4 -0.4 0.4 pF 2,3,7, 8 2,3,9, 10 CDIO Input/output capacitance delta, DQ, DM, DQS, DQS# TDQS,TDQS# -0.5 0.3 -0.5 0.3 -0.5 0.3 -0.5 0.3 -0.5 0.3 -0.5 0.3 pF 2,3,11 CZQ Input/output capacitance of ZQ pin - 3 - 3 - 3 - 3 - 3 - 3 pF 2,3,12 Notes: 1. Although the DM, TDQS and TDQS# pins have different functions, the loading matches DQ and DQS 2. This parameter is not subject to production test. It is verified by design and characterization. VDD=VDDQ=1.5V, VBIAS=VDD/2 and on-die termination off. 3. This parameter applies to monolithic devices only; stacked/dual-die devices are not covered here 4. Absolute value of CCK-CCK# 5. Absolute value of CIO(DQS)-CIO(DQS#) 6. CI applies to ODT, CS#, CKE, A0-A15, BA0-BA2, RAS#,CAS#,WE#. 7. CDI_CTRL applies to ODT, CS# and CKE 8. CDI_CTRL=CI(CTRL)-0.5*(CI(CK)+CI(CK#)) 9. CDI_ADD_CMD applies to A0-A15, BA0-BA2, RAS#, CAS# and WE# 10. CDI_ADD_CMD=CI(ADD_CMD) - 0.5*(CI(CK)+CI(CK#)) 11. CDIO=CIO(DQ,DM) - 0.5*(CIO(DQS)+CIO(DQS#)) 12. Maximum external load capacitance on ZQ pin: 5 pF. Integrated Silicon Solution, Inc. – www.issi.com – Rev. B1 06/25/2021 49 IS43/46TR16512B, IS43/46TR16512BL, IS43/46TR81024B, IS43/46TR81024BL 7. IDD SPECIFICATIONS AND MEASUREMENT CONDITIONS IDD Specifications (x8), 1.5 Operation Voltage Symbol IDD0 IDD1 IDD2P0 IDD2P1 Parameter/Condition DDR3-1066 Max. DDR3-1333 Max. DDR3-1600 Max. DDR3-1866 Max. Unit 83 87 94 98 mA 93 100 107 112 mA 37 37 37 38 mA 41 42 43 43 mA Operating Current 0 -> One Bank Activate-> Precharge Operating Current 1 -> One Bank Activate-> Read-> Precharge Precharge Power-Down Current Slow Exit - MR0 bit A12 = 0 Precharge Power-Down Current Fast Exit - MR0 bit A12 = 1 IDD2PQ Precharge Quiet Standby Current 60 63 67 69 mA IDD2N Precharge Standby Current 62 65 70 72 mA IDD3P Active Power-Down Current Always Fast Exit 56 58 61 62 mA IDD3N Active Standby Current 78 83 92 98 mA IDD4R Operating Current Burst Read 120 138 157 173 mA IDD4W Operating Current Burst Write 156 181 207 231 mA Burst Refresh Current 165 168 172 173 mA 43 43 43 43 mA 48 48 48 48 mA 167 183 204 226 mA IDD5B IDD6 IDD6ET IDD7 Note: 1. 2. Self-Refresh Current Normal Temperature Range (0-85°C) Self-Refresh Current: extended temperature range All Bank Interleave Read Current Columns for DDR3-1066 and DDR3-1333 are for reference only Values applicable for operation with Tc ≤ 95°C. When Tc > +95°C, all IDD values must be derated by 10%. When Tc > +105°C, all IDD values must be derated by 20%. The specifications and notes shown in Component Operating Temperature Range, section 3.2 always apply. Integrated Silicon Solution, Inc. – www.issi.com – Rev. B1 06/25/2021 50 IS43/46TR16512B, IS43/46TR16512BL, IS43/46TR81024B, IS43/46TR81024BL IDD Specifications (x16), 1.5 Operation Voltage DDR3-1066 Max. DDR3-1333 Max. DDR3-1600 Max. DDR3-1866 Max. Unit 83 87 94 98 mA 93 100 107 112 mA 37 37 37 38 mA 41 42 43 43 mA Precharge Quiet Standby Current 60 63 67 69 mA IDD2N Precharge Standby Current 62 65 70 72 mA IDD3P Active Power-Down Current Always Fast Exit 56 58 61 62 mA IDD3N Active Standby Current 78 83 92 98 mA IDD4R Operating Current Burst Read 120 138 157 173 mA IDD4W Operating Current Burst Write 156 181 207 231 mA IDD5B Burst Refresh Current 165 168 172 173 mA 43 43 43 43 mA 48 48 48 48 mA 167 183 204 226 mA Symbol IDD0 IDD1 IDD2P0 IDD2P1 IDD2PQ IDD6 IDD6ET IDD7 Note: 1. 2. Parameter/Condition Operating Current 0 -> One Bank Activate-> Precharge Operating Current 1 -> One Bank Activate-> Read-> Precharge Precharge Power-Down Current Slow Exit - MR0 bit A12 = 0 Precharge Power-Down Current Fast Exit - MR0 bit A12 = 1 Self-Refresh Current Normal Temperature Range (0-85°C) Self-Refresh Current: extended temperature range All Bank Interleave Read Current Columns for DDR3-1066 and DDR3-1333 are for reference only Values applicable for operation with Tc ≤ 95°C. When Tc > +95°C, all IDD values must be derated by 10%. When Tc > +105°C, all IDD values must be derated by 20%. The specifications and notes shown in Component Operating Temperature Range, section 3.2 always apply. Integrated Silicon Solution, Inc. – www.issi.com – Rev. B1 06/25/2021 51 IS43/46TR16512B, IS43/46TR16512BL, IS43/46TR81024B, IS43/46TR81024BL IDD Specifications (x8), 1.35 Operation Voltage DDR3L-1066 Max. DDR3L-1333 Max. DDR3L-1600 Max. DDR3L-1866 Max. Unit 77 81 88 93 mA 87 93 101 106 mA 33 34 34 34 mA 37 37 39 40 mA Precharge Quiet Standby Current 54 57 61 64 mA IDD2N Precharge Standby Current 56 59 64 67 mA IDD3P Active Power-Down Current Always Fast Exit 51 52 56 58 mA IDD3N Active Standby Current 73 77 89 95 mA IDD4R Operating Current Burst Read 113 130 150 167 mA IDD4W Operating Current Burst Write 147 172 198 223 mA Burst Refresh Current 149 152 156 159 mA 39 39 39 39 mA 44 44 44 44 mA 165 177 195 213 mA Symbol IDD0 IDD1 IDD2P0 IDD2P1 IDD2PQ IDD5B IDD6 IDD6ET IDD7 Note: 1. 2. Parameter/Condition Operating Current 0 -> One Bank Activate-> Precharge Operating Current 1 -> One Bank Activate-> Read-> Precharge Precharge Power-Down Current Slow Exit - MR0 bit A12 = 0 Precharge Power-Down Current Fast Exit - MR0 bit A12 = 1 Self-Refresh Current Normal Temperature Range (0-85°C) Self-Refresh Current: extended temperature range All Bank Interleave Read Current Columns for DDR3L-1066 and DDR3L-1333 are for reference only Values applicable for operation with Tc ≤ 95°C. When Tc > +95°C, all IDD values must be derated by 10%. When Tc > +105°C, all IDD values must be derated by 20%. The specifications and notes shown in Component Operating Temperature Range, section 3.2 always apply. Integrated Silicon Solution, Inc. – www.issi.com – Rev. B1 06/25/2021 52 IS43/46TR16512B, IS43/46TR16512BL, IS43/46TR81024B, IS43/46TR81024BL IDD Specifications (x16), 1.35 Operation Voltage Symbol IDD0 IDD1 IDD2P0 IDD2P1 Parameter/Condition DDR3L-1066 Max. DDR3L-1333 Max. DDR3L-1600 Max. DDR3L-1866 Max. Unit 77 81 88 93 mA 87 93 101 106 mA 33 34 34 34 mA 37 37 39 40 mA Operating Current 0 -> One Bank Activate-> Precharge Operating Current 1 -> One Bank Activate-> Read-> Precharge Precharge Power-Down Current Slow Exit - MR0 bit A12 = 0 Precharge Power-Down Current Fast Exit - MR0 bit A12 = 1 IDD2PQ Precharge Quiet Standby Current 54 57 61 64 mA IDD2N Precharge Standby Current 56 59 64 67 mA IDD3P Active Power-Down Current Always Fast Exit 51 52 56 58 mA IDD3N Active Standby Current 73 77 89 95 mA IDD4R Operating Current Burst Read 113 130 150 167 mA IDD4W Operating Current Burst Write 147 172 198 223 mA Burst Refresh Current 149 152 156 159 mA 39 39 39 39 mA 44 44 44 44 mA 165 177 195 213 mA IDD5B IDD6 IDD6ET IDD7 Note: 1. 2. Self-Refresh Current Normal Temperature Range (0-85°C) Self-Refresh Current: extended temperature range All Bank Interleave Read Current Columns for DDR3L-1066 and DDR3L-1333 are for reference only Values applicable for operation with Tc ≤ 95°C. When Tc > +95°C, all IDD values must be derated by 10%. When Tc > +105°C, all IDD values must be derated by 20%. The specifications and notes shown in Component Operating Temperature Range, section 3.2 always apply. Integrated Silicon Solution, Inc. – www.issi.com – Rev. B1 06/25/2021 53 IS43/46TR16512B, IS43/46TR16512BL, IS43/46TR81024B, IS43/46TR81024BL 8. ELECTRICAL CHARACTERISTICS AND AC TIMING FOR DDR3-800 TO DDR3-1600 8.1 Clock Specification The jitter specified is a random jitter meeting a Gaussian distribution. Input clocks violating the min/max values may result in malfunction of the DDR3 SDRAM device. 8.1.1 Definition for tCK(avg) tCK(avg) is calculated as the average clock period across any consecutive 200 cycle window, where each clock period is calculated from rising edge to rising edge. tCK(avg) = ( tCKj ) / N Where N=200 8.1.2 Definition for tCK(abs) tCK(abs) is defind as the absolute clock period, as measured from one rising edge to the next consecutive rising edge. tCK(abs) is not subject to production test. 8.1.3 Definition for tCH(avg) and tCL(avg) tCH(avg) is defined as the average high pulse width, as calculated across any consecutive 200 high pulses: tCH(avg) = ( tCHj ) / (N x tCK(avg) Where N=200 tCL(avg) is defined as the average low pulse width, as calculated across any consecutive 200 low pulses: tCL(avg) = ( tCLj ) / (N x tCK(avg) Where N=200 8.1.4 Definition for note for tJIT(per), tJIT(per, Ick) tJIT(per) is defined as the largest deviation of any single tCK from tCK(avg). tJIT(per) = min/max of {tCKi-tCK(avg) where i=1 to 200} tJIT(per) defines the single period jitter when the DLL is already locked. tJIT(per,lck) uses the same definition for single period jitter, during the DLL locking period only. tJIT(per) and tJIT(per,lck) are not subject to production test. Integrated Silicon Solution, Inc. – www.issi.com – Rev. B1 06/25/2021 54 IS43/46TR16512B, IS43/46TR16512BL, IS43/46TR81024B, IS43/46TR81024BL 8.1.5 Definition for tJIT(cc), tJIT(cc, Ick) tJIT(cc) is defined as the absolute difference in clock period between two consecutive clock cycles: tJIT(cc) = Max of |{tCKi+1-tCKi}| tJIT(cc) defines the cycle to cycle jitter when the DLL is already locked. tJIT(cc,lck) uses the same definition for cycle to cycle jitter, during the DLL locking period only. tJIT(cc) and tJIT(cc,lck) are not subject to production test. 8.1.6 Definition for tERR(nper) tERR is defined as the cumulative error across n multiple consecutive cycles from tCK(avg). tERR is not subject to production test. 8.2 Refresh Parameters Refresh parameters(1,2) Parameter Symbol All Bank Refresh to active/refresh cmd time Average periodic refresh interval Notes: 1. 2. tRFC tREFI -40°C < TCASE < 85°C 85°C < TCASE < 95°C 95°C < TCASE < 105°C 105°C < TCASE < 115°C Units 350 ns 7.8 3.9 1.95 0.97 μs μs μs μs The permissible Tcase (Tc) operating temperature is specified by temperature grade. The maximum Tc is 95°C unless: a. A2 grade, for which the maximum is 105°C. b. A25 grade, for which the maximum is 115°C. In general, the Refresh command needs to be issued at the tREFI interval. For flexibility, a maximum of 8 Refresh commands may be postponed or pulled-in (done in advance). However, in either case, the maximum interval between any two consecutive Refresh commands is 9 x tREFI. 8.3 Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin DDR3-1066MT/s Speed Bin CL-nRCD-nRP Parameter Internal read command to first data ACT to internal read or write delay time PRE command period ACT to ACT or REF command period ACT to PRE command period CWL =5 CL=5 CWL=6 CWL =5 CL=6 CWL=6 CWL =5 CL=7 CWL=6 CWL =5 CL=8 CWL=6 Supported CL Settings Supported CWL Settings Integrated Silicon Solution, Inc. – www.issi.com – Rev. B1 06/25/2021 Symbol tAA tRCD tRP tRC tRAS tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) DDR3/DDR3L-1066 7-7-7 (-187F) Min Max 13.125 20.000 13.125 13.125 50.625 37.500 9*tREFI 3.000 3.300 Reserved 2.500 3.300 Reserved Reserved 1.875