IS46LD32320A-3BPLA25

IS43/46LD16640A IS43/46LD32320A 1Gb (x16, x32) Mobile LPDDR2 S4 SDRAM AUGUST 2014 FEATURES description • Low-voltage Core and I/O Power Supplies VDD2 = 1.14-1.30V, VDDCA/VDDQ = 1.14-1.30V, VDD1 = 1.70-1.95V • High Speed Un-terminated Logic(HSUL_12) I/O Interface • Clock Frequency Range : 10MHz to 400MHz (data rate range : 20Mbps to 800 Mbps per I/O) • Four-bit Pre-fetch DDR Architecture • Multiplexed, double data rate, command/address inputs • Eight internal banks for concurrent operation • Bidirectional/differential data strobe per byte of data (DQS/DQS#) • Programmable Read/Write latencies(RL/WL) and burst lengths(4,8 or 16) • Per-bank refresh for concurrent operation • ZQ Calibration • On-chip temperature sensor to control self refresh rate • Partial –array self refresh(PASR) – Bank & Segment masking • Deep power-down mode(DPD) • Operation Temperature The IS43/46LD16640A/32320A is 1,073,741,824 bits CMOS Mobile Double Data Rate Synchronous DRAMs organized as 8 banks (S4). The deviceis organized as 8 banks of 8Meg words of 16bits or 4Meg words of 32bits. This product uses a double-data-rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 4N prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. This product offers fully synchronous operations referenced to both rising and falling edges of the clock. The data paths are internally pipelined and 4n bits prefetched to achieve very high bandwidth. Commercial (TC = 0°C to 85°C) Industrial (TC = -40°C to 85°C) Automotive, A1 (TC = -40°C to 85°C) Automotive, A2 (TC = -40°C to 105°C) OPTIONS • Configuration: − 64Mx16 (8M x 16 x 8 banks) − 32Mx32 (4M x 32 x 8 banks) Package: − 134-ball BGA for x16 / x32 − 168-ball PoP BGA for x32 ADDRESS TABLE Parameter Row Addresses Column Addresses Bank Addresses Refresh Count 32Mx32 R0-R12 C0-C8 BA0-BA2 4K 64Mx16 R0-R12 C0-C9 BA0-BA2 4K kEY TIMING PARAMETERS Speed Grade -25 -3 Data Rate (Mb/s) 800 667 Write Read tRCD/ Latency Latency tRP 3 2 6 5 Typical Typical Note: Other clock frequencies/data rates supported; please refer to AC timing tables. Copyright © 2014 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc. — www.issi.com 1 Rev. A 8/6/2014 IS43/46LD16640A IS43/46LD32320A BALL ASSIGNMENTS AND DESCRIPTIONS 134-ball FBGA (x32), 0.65mm pitch A B C D E F G H J K L M N P R T U 1 2 3 DNU DNU DNU NC NC VDD1 VSS RFU VSS VDD2 ZQ VSSCA CA9 CA8 VDDCA CA6 VDD2 4 5 7 8 10 DNU DNU DQ26 DNU DQ31 VSS VSSQ VDDQ DQ25 VSSQ VDDQ VDDQ DQ30 DQ27 DQS3_t DQS3_c VSSQ DQ28 DQ24 DM3 DQ15 VDDQ VSSQ CA7 VSSQ DQ11 DQ13 DQ14 DQ12 VDDQ CA5 Vref(CA) DQS1_c DQS1_t DQ10 DQ9 DQ8 VSSQ VDDCA VSS CK_c DM1 VDDQ VSSCA NC CK_t VSSQ VDDQ VDD2 VSS Vref(DQ) CKE RFU RFU DM0 VDDQ CS_n RFU RFU DQS0_c DQS0_t DQ5 DQ6 DQ7 VSSQ CA4 CA3 CA2 VSSQ DQ4 DQ2 DQ1 DQ3 VDDQ VSSCA VDDCA CA1 DQ19 DQ23 DM2 DQ0 VDDQ VSSQ VSS VDD2 CA0 VDDQ DQ17 DQ20 DQS2_t DQS2_c VSSQ VDD1 VSS NC VSS VSSQ VDDQ DQ22 VSSQ VDDQ DNU NC NC VDD2 VDD1 DQ16 DQ18 DQ21 DNU DNU DNU DNU DNU 1 2 9 10 4 5 6 7 DQ29 9 VDD1 3 VDD2 6 8 A B C D E F G H J K L M N P R T U DQ CA Power Ground No ball ZQ Clock NC, DNU, RFU Top View (ball down) 2 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 8/6/2014 IS43/46LD16640A IS43/46LD32320A BALL ASSIGNMENTS AND DESCRIPTIONS 134-ball FBGA (x16), 0.65mm pitch A B C D E F G H J K L M N P R T U 1 2 3 9 10 DNU DNU DNU DNU DNU NC NC VDD2 VDD1 NC NC NC DNU VDD1 VSS RFU VSS VSSQ VDDQ NC VSSQ VDDQ VSS VDD2 ZQ VDDQ NC NC NC NC VSSQ VSSCA CA9 CA8 NC NC NC DQ15 VDDQ VSSQ VDDCA CA6 CA7 VSSQ DQ11 DQ13 DQ14 DQ12 VDDQ VDD2 CA5 Vref(CA) DQS1_c DQS1_t DQ10 DQ9 DQ8 VSSQ VDDCA VSS CK_c DM1 VDDQ VSSCA NC CK_t VSSQ VDDQ CKE RFU RFU DM0 VDDQ CS_n RFU RFU DQS0_c DQS0_t DQ5 DQ6 DQ7 VSSQ CA4 CA3 CA2 VSSQ DQ4 DQ2 DQ1 DQ3 VDDQ VSSCA VDDCA CA1 NC NC NC DQ0 VDDQ VSSQ VSS VDD2 CA0 VDDQ NC NC NC NC VSSQ VDD1 VSS NC VSS VSSQ VDDQ NC VSSQ VDDQ DNU NC NC VDD2 VDD1 NC NC NC DNU DNU DNU DNU DNU 1 2 9 10 3 4 4 5 5 6 6 7 VDD2 7 8 VSS 8 Vref(DQ) A B C D E F G H J K L M N P R T U DQ CA Power Ground No ball ZQ Clock NC, DNU, RFU Top View (ball down) Integrated Silicon Solution, Inc. — www.issi.com 3 Rev. A 8/6/2014 IS43/46LD16640A IS43/46LD32320A 168-ball FBGA - 12mm x 12mm (x32), 0.5mm pitch 1 2 3 4 5 6 7 8 9 10 11 12 A DNU DNU NC NC NC NC NC NC NC NC V DD1 V SSQ B DNU DNU V DD1 NC V SS NC NC V SS NC V SS V DD2 DQ31 V DDQ C V SS V DD2 D NC E 21 22 23 V SS DNU DNU A V DD2 DNU DNU B DQ15 V SSQ C NC V DDQ DQ14 D NC NC DQ12 DQ13 E F NC V SS 1 DQ11 V SSQ F G NC NC V DDQ DQ10 G H NC NC DQ8 DQ9 H J NC V SS 1 DQS1 V SSQ J K NC NC V DDQ DQS#1 L NC NC V DD2 DM1 L M NC V SS V REFDQ V SS M N NC V DD1 V DD1 DM0 N P ZQ V REFCA DQS#0 V SSQ P R V SS V DD2 V DDQ DQS0 R T CA9 CA8 DQ6 DQ7 T U CA7 V DDCA DQ5 V SSQ U V V SSCA CA6 V DDQ DQ4 V W CA5 V DDCA DQ2 DQ3 W Y CK# CK DQ1 V SSQ Y AA V SS V DD2 V DDQ DQ0 AA AB DNU DNU CS# NC V DD1 CA1 V SSCA V DD2 DNU DNU AB AC DNU DNU CKE NC V SS CA0 CA2 V DDCA AC 1 2 3 4 5 6 1 7 1 CA3 8 CA4 V SS 9 1 13 14 DQ30 DQ29 DQ28 DQ18 V DD2 V SS DQ16 V DDQ NC NC V SSQ DQ17 DQ19 10 11 12 13 14 15 16 17 V SSQ DQ26 DQ25 18 DQ20 V DDQ DQ22 DQS2 15 16 17 20 V SSQ DQS#3 V DD1 DQ27 V DDQ DQ24 DQS3 V SSQ DQ21 DQ23 19 V DDQ V DDQ DM3 DM2 V SSQ DQS#2 V DD1 V SS DNU DNU 19 21 22 23 18 20 K Top View (ball down) Note: 1. Balls labeled Vss1 (at coordinates B5, B8, F2, J2, AC9) may be connected to Vss or left unconnected. 2. Balls indicated as (NC) are no connects. 4 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 8/6/2014 IS43/46LD16640A IS43/46LD32320A INPUT/OUTPUT FUNCTIONAL DESCRIPTION Pad Definition and Description Type Description CK_t, CK_c Name Input Clock: CK_t and CK_c are differential clock inputs. All Double Data Rate (DDR) CA inputs are sampled on both positive and negative edge of CK_t. Single Data Rate (SDR) inputs, CS_n and CKE, are sampled at the positive Clock edge. Clock is defined as the differential pair, CK_t and CK_c. The positive Clock edge is defined by the crosspoint of a rising CK_t and a falling CK_c. The negative Clock edge is defined by the crosspoint of a falling CK_t and a rising CK_c. CKE Input Clock Enable: CKE HIGH activates and CKE LOW deactivates internal clock signals and therefore device input buffers and output drivers. Power savings modes are entered and exited through CKE transitions. CKE is considered part of the command code. See Command Truth Table for command code descriptions. CKE is sampled at the positive Clock edge. CS_n Input Chip Select: CS_n is considered part of the command code. See Command Truth Table for command code descriptions. CS_n is sampled at the positive Clock edge. CA0 - CA9 Input DDR Command/Address Inputs: Uni-directional command/address bus inputs. CA is considered part of the command code. See Command Truth Table for command code descriptions. I/O Data Inputs/Output: Bi-directional data bus I/O Data Strobe (Bi-directional, Differential): The data strobe is bi-directional (used for read and write data) and differential (DQS_t and DQS_c). It is output with read data and input with write data. DQS_t is edge-aligned to read data and centered with write data. DQ0 - DQ15 (x16) DQ0 - DQ31 (x32) DQS0_t, DQS0_c, DQS1_t, DQS1_c (x16) DQS0_t DQS3_t, DQS0_c DQS3_c (x32) For x16, DQS0_t and DQS0_c correspond to the data on DQ0 - DQ7; DQS1_t and DQS1_c to the data on DQ8 - DQ15. For x32 DQS0_t and DQS0_c correspond to the data on DQ0 - DQ7, DQS1_t and DQS1_c to the data on DQ8 - DQ15, DQS2_t and DQS2_c to the data on DQ16 - DQ23, DQS3_t and DQS3_c to the data on DQ24 - DQ31. Input DM0-DM1 (x16) DM0 - DM3 (x32) Input Data Mask: For LPDDR2 devices that do not support the DNV feature, DM is the input mask signal for write data. Input data is masked when DM is sampled HIGH coincident with that input data during a Write access. DM is sampled on both edges of DQS_t. Although DM is for input only, the DM loading shall match the DQ and DQS_t (or DQS_c). DM0 is the input data mask signal for the data on DQ0-7. For x16 and x32 devices, DM1 is the input data mask signal for the data on DQ8-15. For x32 devices, DM2 is the input data mask signal for the data on DQ16-23 and DM3 is the input data mask signal for the data on DQ24-31. Integrated Silicon Solution, Inc. — www.issi.com 5 Rev. A 8/6/2014 IS43/46LD16640A IS43/46LD32320A Name Type Description VDD1 Supply Core Power Supply 1 VDD2 Supply Core Power Supply 2 VDDCA Supply Input Receiver Power Supply: input buffers. VDDQ Supply I/O Power Supply: Power supply for Data input/output buffers. VREF(CA) Supply Reference Voltage for CA Command and Control Input Receiver: for all CA0-9, CKE, CS_n, CK_t, and CK_c input buffers. VREF(DQ) Supply Reference Voltage for DQ Input Receiver: VSS Supply Ground VSSCA Supply Ground for Input Receivers VSSQ Supply I/O Ground ZQ I/O Power supply for CA0-9, CKE, CS_n, CK_t, and CK_c Reference voltage Reference voltage for all Data input buffers. Reference Pin for Output Drive Strength Calibration NOTE 1 Data includes DQ and DM. 6 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 8/6/2014 IS43/46LD16640A IS43/46LD32320A FUNCTIONAL BLOCK DIAGRAM CS# CA0 CA1 CA2 CA3 CA4 CA5 CA6 CA7 CA8 CA9 Control logic Command / Address Multiplex and Decode CKE CK CK# Mode registers x Refresh x counter Rowaddress MUX Bank 7 Bank 7 Bank 6 Bank 6 Bank 5 Bank 5 Bank 4 Bank 4 Bank 3 Bank 3 Bank 2 Bank 2 Bank 1 Bank 1 Bank 0 Bank 0 rowMemory array address latch and decoder COL0 n 4n Read latch n MUX n n Sense amplifier 3 I/O gating DM mask logic Bank control logic Columnaddress counter/ latch y-1 Column decoder DRVRS DQ0–DQn-1 DQS generator DQS, DQS# Input registers 4 4 4n 3 n DATA WRITE FIFO and 4n drivers CK, CK# 1 8 Mask CK out 4n CK in Data 4 4 4 4 4 4 n n n n n n n n DQS, DQS# 4 RCVRS n DM COL0 Integrated Silicon Solution, Inc. — www.issi.com 7 Rev. A 8/6/2014 IS43/46LD16640A IS43/46LD32320A SIMPLIFIED STATE DIAGRAM Power applied Deep power-down DPDX Power-on RE Automatic sequence SET Resetting MR reading Command sequence MRR Self refreshing Resetting DPD MRR SR EF REF Idle 1 Refreshing X M PD RW Idle MR reading X T SE RE X PD Resetting power-down SR EF PD PD Idle power-down MR writing ACT Active power-down Active MR reading PD X PD R MR Active BST PR BST RD WR RD Reading A WR RD Writing A WR PR, PRA WRA RDA Writing with auto precharge Reading with auto precharge Precharging Abbreviation ACT RD(A) WR(A) PR(A) MRW MRR Function Active Read (w/ Autoprecharge) Write (w/ Autoprecharge) Precharge (All) Mode Register Write Mode Register Read Abbreviation PD PDX DPD DPDX BST RESET Function Enter Power Down Exit Power Down Enter Deep Power Down Abbreviation REF SREF Function Refresh Enter self refresh SREFX Exit self refresh Exit Deep Power Down Burst Terminate Reset is achieved through MRW command Note: For LPDDR2-S4 SDRAM in the idle state, all banks are precharged. 8 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 8/6/2014 IS43/46LD16640A IS43/46LD32320A FUNCTIONAL DESCRIPTION LPDDR2-S4 is a high-speed SDRAM device internally configured as an 8-Bank memory. This device contains 1,073,741,824 bits (1 Gigabit) All LPDDR2 devices use a double data rate archiecture on the Command/Address (CA) bus to reduce the number of input pins in the system. The 10-bit CA bus contains command, address, and Bank/Row Buffer information. Each command uses one clock cycle, during which command information is transferred on both the positive and negative edge of the clock. This LPDDR2-S4 device also uses a double data rate architecture on the DQ pins to achieve high speed operation. The double data rate architecture is essentially a 4n prefetch architecture with an interface designed to transfer two data bits per DQ every clock cycle at the I/O pins. A single read or write access for the memory device effectively consists of a single 4n-bit wide, one clock cycle data transfer at the internal SDRAM core and four corresponding nbit wide, one-half-clock-cycle data transfers at the I/O pins. Read and write accesses to the LPDDR2 are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an Activate command, which is then followed by a Read or Write command. The address and BA bits registered coincident with the Activate command are used to select the row and the Bank to be accessed. The address bits registered coincident with the Read or Write command are used to select the Bank and the starting column location for the burst access. Prior to normal operation, the LPDDR2 must be initialized. The following section provides detailed information covering device initialization, register definition, command description and device operation. Integrated Silicon Solution, Inc. — www.issi.com 9 Rev. A 8/6/2014 IS43/46LD16640A IS43/46LD32320A Power-up and Initialization DDR2 SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. The following sequence is required for Power-up and Initialization. 1. Voltage ramp up sequence is required : A. While applying power, attempt to maintain CKE below 0.2 x VDDCA and all other inputs must be between VILmin and VIHmax. The device outputs remain at High-Z while CKE is held LOW. The voltage ramp time tINIT0 ( Tb-Ta) must be no greater than 20 ms from Tb which is point for all supply and reference voltage are within their defined operating ranges , to Ta which is point for any power supply first reaches 300mV. B. The following conditions apply for voltage ramp after Ta is reached, − VDD1 must be greater than VDD2-200mV AND − VDD1 and VDD2 must be greater than VDDCA-200mV AND − VDD1 and VDD2 must be greater than VDDQ-200mV AND − VREF must always be less than all other supply voltages − The voltage difference between any of VSS, VSSQ, and VSSCA pins must not exceed 100mV 2. Start clock and maintain stable condition. Beginning at Tb, CKE must remain LOW for at least tINIT1 = 100 ns, after which CKE can be asserted HIGH. The clock must be stable at least tINIT2 = 5 × tCK prior to the first CKE LOW-to-HIGH transition (Tc). CKE, /CS, and CA inputs must observe setup and hold requirements (tIS, tIH) with respect to the first rising clock edge (and to subsequent falling and rising edges). Once the ramping of the supply voltages is complete ( Tb), CKE must be maintained LOW. DQ, DM, DQS and DQS# voltage levels must be between VSSQ and VDDQ during voltage ramp to avoid latchup. CK, /CK, /CS, and CA input levels must be between VSSCA and VDDCA during voltage ramp to avoid latch-up If any Mode Register Read ( MRRs ) are issued, the clock period must be within the range defined for tCKb (18ns to 100ns). Mode Register Write (MRWs) can be issued at normal clock frequencies as long as all AC timings are met. Some AC parameters could have relaxed timings before the system is appropriately configured. While keeping CKE HIGH, NOP commands must be issued for at least tINIT3 = 200μs (Td). 3. RESET Command After tINIT3 is satisfied, the MRW RESET command must be issued (Td). An optional PRECHARGE ALL command can be issued prior to the MRW RESET command. Wait at least tINIT4 while keeping CKE asserted and issuing NOP commands 4. Mode Register Reads and Device Auto Initialization (DAI) Polling: After tINIT4 is satisfied (Te), only MRR commands and power-down entry/exit commands are supported. After Te, CKE can go LOW in alignment with power-down entry and exit specifications. Use the MRR command to poll the DAI bit and report when device auto initialization is complete; otherwise, the controller must wait a minimum of tINIT5, or until the DAI bit is set before proceeding. As the memory output buffers are not properly configured by Te, some AC parameters must have relaxed timings before the system is appropriately configured. After the DAI bit (MR0, DAI) is set to zero by the memory device (DAI complete), the device is in the idle state (Tf ). DAI status can be determined by issuing the MRR command to MR0. The device sets the DAI bit no later than tINIT5 after the RESET command. The controller must wait at least tINIT5 or until the DAI bit is set before proceeding 10 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 8/6/2014 IS43/46LD16640A IS43/46LD32320A 5. ZQ Calibration After tINIT5 (Tf ), the MRR initialization calibration (ZQ_CAL) command can be issued to the memory (MR10). This command is used to calibrate output impedance over process, voltage, and temperature. In systems where more than one LPDDR2 device exists on the same bus, the controller must not overlap MRR ZQ_CAL commands. The device is ready for normal operation after tZQINIT. 6. Normal Operation After tZQINIT (Tg), MRW commands must be used to properly configure the memory . Specifically, MR1, MR2, and MR3 must be set to configure the memory for the target frequency and memory configuration After the initialization sequence is complete, the device is ready for any valid command. After Tg, the clock frequency can be changed using the procedure described in Input Clock Frequency Changes and Clock Stop Events‖. Initialization Timing Symbol Parameter tINIT0 Value Maximum Power Ramp Time Unit min max - 20 ms tINIT1 Minimum CKE low time after completion of power ramp 100 - ns tINIT2 Minimum stable clock before first CKE high 5 - tCK tINIT3 Minimum idle time after first CKE assertion 200 - us tINIT4 Minimum idle time after Reset command, this time will be about 2 x tRFCab + tRPab 1 - us tINIT5 Maximum duration of Device Auto-Initialization - 10 us tCKb Clock cycle time during boot 18 100 ns ZQ initial calibration 1 - us tZQINIT Figure - Power Ramp and Initialization Sequence Ta Tb t INIT2 Tc Td Te Tf Tg CK/CK# t INIT0 Supplies t INIT1 t INIT3 CKE t ISCKE CA t INIT4 RESET t INIT5 MRR t ZQINIT MRW ZQ_CAL Valid R TT DQ Initialization After RESET (without voltage ramp): If the RESET command is issued before or after the power-up initialization sequence, the re-initialization procedure must begin at Td Integrated Silicon Solution, Inc. — www.issi.com 11 Rev. A 8/6/2014 IS43/46LD16640A IS43/46LD32320A Power-Off Sequence Use the following sequence to power off the device. Unless specified otherwise, this procedure is mandatory and applies to S4 devices. While powering off, CKE must be held LOW (≤ 0.2 × VDDCA); all other inputs must be between VILmin and VIHmax. The device outputs remain at High-Z while CKE is held LOW. DQ, DM, DQS, and /DQS voltage levels must be between VSSQ and VDDQ during the power-off sequence to avoid latch-up. CK, /CK, /CS, and CA input levels must be between VSSCA and VDDCA during the power-off sequence to avoid latch-up. Tx is the point where any power supply drops below the minimum value specified in the DC operating condition table. Tz is the point where all power supplies are below 300mV. After Tz, the device is powered off Required Power Supply Conditions Between Tx and Tz: • VDD1 must be greater than VDD2 - 200mV • VDD1 must be greater than VDDCA - 200mV • VDD1 must be greater than VDDQ - 200mV • VREF must always be less than all other supply voltages The voltage difference between VSS, VSSQ, and VSSCA must not exceed 100mV. For supply and reference voltage operating conditions, see Recommended DC Operating Conditions table. Uncontrolled Power-Off Sequence When an uncontrolled power-off occurs, the following conditions must be met: 1. At Tx, when the power supply drops below the minimum values specified, all power supplies must be turned off and all power-supply current capacity must be at zero, except for any static charge remaining in the system. 2. After Tz , the device must power off. The time between Tx and Tz must not exceed 20ms. During this period, the relative voltage between power supplies is uncontrolled. VDD1 and VDD2 must decrease with a slope lower than 0.5 V/μs between Tx and Tz. An uncontrolled power-off sequence can occur a maximum of 400 times over the life of the device Mode Register Definition LPDDR2 devices contain a set of mode registers used for programming device operating parameters, reading device information and status, and for initiating special operations such as DQ calibration, ZQ calibration, and device reset. 12 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 8/6/2014 IS43/46LD16640A IS43/46LD32320A Mode Register Assignment The MRR command is used to read from a register. The MRW command is used to write to a register. Mode Register Assignment MR# MA Function Access OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 0 00H Device Info. R DI DAI 1 01H Device Feature1 W nWR (for AP) 2 02H Device Feature2 W (RFU) RL & WL 3 03H I/O Config-1 W (RFU) DS 4 04H Refresh Rate R 5 05H Basic Config-1 R LPDDR2 Manufacturer ID 6 06H Basic Config-2 R Revision ID1 7 07H Basic Config-3 R Revision ID2 8 08H Basic Config-4 R 9 09H Test Mode W Vendor-Specific Test Mode 10 0AH IO Calibration W Calibration Code 11~15 0BH~0FH (reserved) (RFU) TUF WC BT BL (RFU) I/O width Refresh Rate Density Type (RFU) Mode Register Assignment MR# MA Function Access OP7 OP6 OP5 OP4 OP3 16 10H PASR_BANK W Bank Mask 17 11H PASR_Seg W Segment Mask 18-19 12H-13H (Reserved) OP2 OP1 OP0 (RFU) Integrated Silicon Solution, Inc. — www.issi.com 13 Rev. A 8/6/2014 IS43/46LD16640A IS43/46LD32320A Mode Register Assignment MR# MA 20-31 18H-1FH Function Access OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 Reserved Mode Register Assignment (Reset Command & RFU part) MR# MA Function Access 32 20H DQ calibration pattern A R See “Data Calibration Pattern Description” 33-39 21H-27H (Do Not Use) 40 28H DQ calibration pattern B R See “Data Calibration Pattern Description” 41-47 29H-2FH (Do Not Use) 48-62 30H-3EH (Reserved) 63 3FH Reset 64-126 40H-7EH (Reserved) 127 7FH (Do Not Use) 128-190 80H-BEH (Reserved for Vendor Use) 191 BFH (Do Not Use) 192-254 C0H-FEH (Reserved for Vendor Use) 255 FFH (Do Not Use) (RFU) W X (RFU) (RFU) (RFU) Notes: 1. RFU bits shall be set to ‘0’ during Mode Register writes. 2.RFU bits shall be read as ‘0’ during Mode Register reads. 3.All Mode Registers that are specified as RFU or write-only shall return undefined data when read and DQS shall be toggled. 4.All Mode Registers that are specified as RFU shall not be written. 5.See Vendor Device Datasheets for details on Vendor Specific Mode Registers. 6.Writes to read-only registers shall have no impact on the functionality of the device. MR0_Device Information (MA = 00H): OP7 OP6 OP5 OP4 OP3 OP2 (RFU) OP1 OP0 14 DI (Device Information) DAI (Device Auto-Initialization Status) OP1 OP0 DI DAI Read-only Read-only 0B: SDRAM 1B: Do Not Use 0B: DAI complete 1B: DAI still in progress Integrated Silicon Solution, Inc. — www.issi.com Rev. A 8/6/2014 IS43/46LD16640A IS43/46LD32320A MR1_Devcie Feature 1 (MA = 01H): OP7 OP6 OP5 nWR (for AP) OP4 OP3 WC BT OP2 OP1 OP0 BL 010B: BL4 (default) OP BL (Burst Length) 011B: BL8 Write-only 100B: BL16 All others: reserved *1 OP3 BT (Burst Type) Write-only OP4 WC (Wrap) Write-only 0B: Sequential (default) 1B: Interleaved 0B: Wrap (default) 1B: No wrap (allowed for SDRAM BL4 only) 001B: nWR=3 (default) 010B: nWR=4 011B: nWR=5 OP *2 nWR Write-only 100B: nWR=6 101B: nWR=7 110B: nWR=8 All others: reserved Notes: 1. BL16, interleaved is not an official combination to be supported. 2. Programmed value in nWR register is the number of clock cycles which determines when to start internal precharge operation for a write burst with AP enabled. It is determined by RU(tWR/tCK) Burst Sequence by BL, BT, and WC C3 C2 C1 C0 x x 0B 0B x x 1B 0B x x x 0B WC BT BL wrap any 4 nw any Burst Cycle Number and Burst Address Sequence 1 2 3 4 0 1 2 3 2 3 0 1 y 5 6 7 8 9 10 11 12 13 14 15 16 y+1 y+2 y+3 Integrated Silicon Solution, Inc. — www.issi.com 15 Rev. A 8/6/2014 IS43/46LD16640A IS43/46LD32320A C1 C0 WC Burst Cycle Number and Burst Address Sequence C3 C2 BT BL x 0B 0B 0B x 0B 1B 0B x 1B 0B 0B x 1B 1B 0B x 0B 0B 0B x 0B 1B 0B x 1B 0B 0B x 1B 1B 0B x x x 0B 0B 0B 0B 0B 0 1 2 3 4 5 6 7 8 0B 0B 1B 0B 2 3 4 5 6 7 8 9 0B 1B 0B 0B 4 5 6 7 8 9 A 0B 1B 1B 0B 6 7 8 9 A B 1B 0B 0B 0B wrap 8 9 A B C 1B 0B 1B 0B A B C D 1B 1B 0B 0B C D E 1B 1B 1B 0B E F 0 x x x 0B int illegal (not allowed) x x x 0B nw any illegal (not allowed) seq 8 wrap int 1 2 3 4 5 6 7 8 0 1 2 3 4 5 6 7 2 3 4 5 6 7 0 1 4 5 6 7 0 1 2 3 6 7 0 1 2 3 4 5 0 1 2 3 4 5 6 7 2 3 0 1 6 7 4 5 4 5 6 7 0 1 2 3 6 7 4 5 2 3 0 1 11 12 13 14 15 16 9 A B C D E F A B C D E F 0 1 B C D E F 0 1 2 3 C D E F 0 1 2 3 4 5 D E F 0 1 2 3 4 5 6 7 E F 0 1 2 3 4 5 6 7 8 9 F 0 1 2 3 4 5 6 7 8 9 A B 1 2 3 4 5 6 7 8 9 A B C D nw any 9 10 illegal (not allowed) seq 16 Notes: 1. C0 input is not present on CA bus. It is implied zero. 2. For BL=4, the burst address represents C1~C0. 3. For BL=8, the burst address represents C2~C0. 4. For BL=16, the burst address represents C3~C0. 5. For no-wrap, BL4, the burst must not cross the page boundary or the sub-page boundary.The variabley can start at any address with C0 equal to 0, but must not start at any address shown below Non-Wrap Restrictions Width 64Mb 128Mb/256Mb 512Mb/1Gb/2Gb 4Gb/8Gb Cannot cross full page boundary X16 FE, FF, 00, 01 1FE, 1FF, 000, 001 3FE, 3FF, 000, 001 7FE, 7FF, 000, 001 X32 7E, 7F, 00, 01 FE, FF, 00, 01 1FE, 1FF, 000, 001 3FE, 3FF, 000, 001 Cannot cross sub-page boundary X16 7E, 7F, 80, 81 0FE, 0FF, 100, 101 1FE, 1FF, 200, 201 3FE, 3FF, 400, 401 X32 none none None none Note: Non-wrap BL=4 data orders shown are prohibited. . 16 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 8/6/2014 IS43/46LD16640A IS43/46LD32320A MR2_Devcie Feature 2 (MA = 02H): OP7 OP6 OP5 OP4 OP3 (RFU) OP2 OP1 OP0 RL & WL 0001B: RL3 / WL1 (default) 0010B: RL4 / WL2 0011B: RL5 / WL2 RL & WL (Read Latency & Write OP Write-only Latency) 0100B: RL6 / WL3 0101B: RL7 / WL4 0110B: RL8 / WL4 All others: reserved MR3_I/O Configuration 1 (MA = 03H): OP7 OP6 OP5 OP4 OP3 OP2 (RFU) OP1 OP0 DS 0000B: reserved 0001B: 34.3 ohm typical 0010B: 40.0 ohm typical (default) OP DS (Drive Strength) Write-only 0011B: 48.0 ohm typical 0100B: 60.0 ohm typical 0101B: reserved 0110B: 80.0 ohm typical All others: reserved MR4_Device Temperature (MA = 04H): OP7 OP6 TUF OP5 OP4 OP3 (RFU) OP2 OP1 OP0 SDRAM Refresh Rate 000B: 4 x tREFI, SDRAM Low Temp. operating limit exceeded 001B: 4 × tREFI, 4 × tREFIpb, 4 × tREFW OP SDRAM Refresh Rate Read-only 010B: 2 × tREFI, 2 × tREFIpb, 2 × tREFW , 011B: 1 × tREFI, 1 × tREFIpb, 1 × tREFW ( tCK Burst Read: RL=5, BL=4, tDQSCK > tCK Integrated Silicon Solution, Inc. — www.issi.com 35 Rev. A 8/6/2014 IS43/46LD16640A IS43/46LD32320A Burst READ – RL = 3, BL = 8, tDQSCK < tCK t t Burst Read: RL=3, BL=8, DQSCK < CK 36 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 8/6/2014 IS43/46LD16640A IS43/46LD32320A tDQSCKDL Timing Notes: 1. tDQSCKDL = (tDQSCKn - tDQSCKm). 2. tDQSCKDL (MAX) is defined as the maximum of ABS (tDQSCKn - tDQSCKm) for any (tDQSCKn, tDQSCKm) pair within any 32ms rolling window. Integrated Silicon Solution, Inc. — www.issi.com 37 Rev. A 8/6/2014 IS43/46LD16640A IS43/46LD32320A tDQSCKDM Timing t DQSCKDM timing Notes: 1. tDQSCKDM = (tDQSCKn - tDQSCKm). 2. tDQSCKDM (MAX) is defined as the maximum of ABS (tDQSCKn - tDQSCKm) for any (tDQSCKn, tDQSCKm) pair within any 1.6μs rolling window. 38 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 8/6/2014 IS43/46LD16640A IS43/46LD32320A DQSCKDS timing tDQSCKDS t Timing Notes: 1. tDQSCKDS = (tDQSCKn - tDQSCKm). 2. tDQSCKDS (MAX) is defined as the maximum of ABS (tDQSCKn - tDQSCKm) for any (tDQSCKn, tDQSCKm) pair for READs within a consecutive burst, within any 160ns rolling window. Integrated Silicon Solution, Inc. — www.issi.com 39 Rev. A 8/6/2014 IS43/46LD16640A IS43/46LD32320A Burst READ Followed by Burst WRITE – RL = 3, WL = 1, BL = 4 The minimum time from the burst READ command to the burst WRITE command is defined by the read latency (RL) and the burst length (BL). Minimum READ-to-WRITE latency is RL + RU(tDQSCK(MAX)/tCK) + BL/2 + 1 - WL clock cycles. Note that if a READ burst is truncated with a burst TERMINATE (BST) command, the effective burst length of the truncated READ burst should be used for BL when calculating the minimum READ-to-WRITE delay. Seamless Burst READ – RL = 3, BL = 4, tCCD = 2 A seamless burst READ operation is supported by enabling a READ command at every other clock cycle for BL = 4 operation, every fourth clock cycle for BL = 8 operation, and every eighth clock cycle for BL = 16 operation. This operation is supported as long as the banks are activated, whether the accesses read the same or different banks. 40 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 8/6/2014 IS43/46LD16640A IS43/46LD32320A READs Interrupted by a READ For LP-DDR2-S4 devices, burst READ can be interrupted by another READ with a 4-bit burst boundary, provided that tCCD is met. A burst READ can be interrupted by other READs on any subsequent clock, provided that tCCD is met. READ Burst Interrupt Example – RL = 3, BL = 8, tCCD = 2 Note: READs can only be interrupted by other READs or the BST command. Integrated Silicon Solution, Inc. — www.issi.com 41 Rev. A 8/6/2014 IS43/46LD16640A IS43/46LD32320A Burst WRITE The burst WRITE command is initiated with CS# LOW, CA0 HIGH, CA1 LOW, and CA2 LOW at the rising edge of the clock. The command address bus inputs, CA5r–CA6r and CA1f–CA9f, determine the starting column address for the burst. Write latency (WL) is defined from the rising edge of the clock on which the WRITE command is issued to the rising edge of the clock from which the tDQSS delay is measured. The first valid data must be driven WL × tCK + tDQSS from the rising edge of the clock from which the WRITE command is issued. The data strobe signal (DQS) must be driven LOW tWPRE prior to data input. The burst cycle data bits must be applied to the DQ pins tDS prior to the associated edge of the DQS and held valid until tDH after that edge. Burst data is sampled on successive edges of the DQS until the 4-, 8-, or 16-bit burst length is completed. After a burst WRITE operation, tWR must be satisfied before a PRECHARGE command to the same bank can be issued. Pin input timings are measured relative to the crosspoint of DQS and its complement, DQS#. Data Input (WRITE) Timing Data input (Write) timing 42 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 8/6/2014 IS43/46LD16640A IS43/46LD32320A Burst WRITE – WL = 1, BL = 4 NT6TL64M32AQ Burst Burst WRITE Followed by Burst READ – write: RL =WL=1, 3, WLBL=4 = 1, BL = 4 Burst write followed by burst read: RL=3, WL=1, BL=4 Notes: 1. The minimum number of clock cycles from the burst WRITE command to the burst READ command for any bank is [WL + 1 + BL/2 + RU(tWTR/tCK)]. 2. tWTR starts at the rising edge of the clock after the last valid input data. 3. If a WRITE burst is truncated with a BST command, the effective burst length of the truncated WRITE burst should be used as BL to calculate the minimum WRITE-to-READ delay. Integrated Silicon Solution, Inc. — www.issi.com 43 Rev. A 8/6/2014 IS43/46LD16640A IS43/46LD32320A Seamless Burst WRITE – WL = 1, BL = 4, tCCD = 2 Note: The seamless burst WRITE operation is supported by enabling a WRITE command every other clock for BL = 4 operation, every four clocks for BL = 8 operation, or every eight clocks for BL = 16 operation. This operation is supported for any activated bank. WRITEs Interrupted by a WRITE For LPDDR2-S4 devices, a burst WRITE can only be interrupted by another WRITE with a 4-bit burst boundary, provided that tCCD (MIN) is met. A WRITE burst interrupt can occur on any clock after the initial WRITE command, provided that tCCD (MIN) is met. WRITE Burst Interrupt Timing – WL = 1, BL = 8, tCCD = 2 Notes: 1. WRITEs can only be interrupted by other WRITEs or the BST command. 2. The effective burst length of the first WRITE equals two times the number of clock cycles between the first WRITE and the interrupting WRITE 44 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 8/6/2014 IS43/46LD16640A IS43/46LD32320A BURST TERMINATE (BST) The BURST TERMINATE (BST) command is initiated with CS# LOW, CA0 HIGH, CA1 HIGH, CA2 LOW, and CA3 LOW at the rising edge of the clock. A BST command can only be issued to terminate an active READ or WRITE burst. Therefore, a BST command can only be issued up to and including BL/2 - 1 clock cycles after a READ or WRITE command. The effective burst length of a READ or WRITE command truncated by a BST command is as follows: • Effective burst length = 2 × (number of clock cycles from the READ or WRITE command to the BST command). • If a READ or WRITE burst is truncated with a BST command, the effective burst length of the truncated burst should be used for BL when calculating the minimum READ to-WRITE or WRITEto-READ delay. • The BST command only affects the most recent READ or WRITE command. The BST command truncates an ongoing READ burst RL × tCK + tDQSCK + tDQSQ after the rising edge of the clock where the BST command is issued. The BST command truncates an ongoing WRITE burst WL × tCK + tDQSS after the rising edge of the clock where the BST command is issued. • The 4-bit prefetch architecture enables BST command assertion on even clock cycles following a WRITE or READ command. The effective burst length of a READ or WRITE command truncated by a BST command is thus an integer multiple of four. Burst WRITE Truncated by BST – WL = 1, BL = 16 Burst Write truncated by BST: WL=1, BL=16 Notes: 1. The BST command truncates an ongoing WRITE burst WL × tCK + tDQSS after the rising edge of the clock where the BST command is issued. 2. BST can only be issued an even number of clock cycles after the WRITE command. 3. Additional BST commands are not supported after T4 and must not be issued until after the next READ or WRITE command. Integrated Silicon Solution, Inc. — www.issi.com 45 Rev. A 8/6/2014 IS43/46LD16640A IS43/46LD32320A Burst READ Truncated by BST – RL = 3, BL = 16 Notes: 1. The BST command truncates an ongoing READ burst (RL × tCK + tDQSCK + tDQSQ) after the rising edge of the clock where the BST command is issued. 2. BST can only be issued an even number of clock cycles after the READ command. 3. Additional BST commands are not supported after T4 and must not be issued until after the next READ or WRITE command Write Data Mask On LPDDR2 devices, one write data mask (DM) pin for each data byte (DQ) is supported, consistent with the implementation on LPDDR SDRAM. Each DM can mask its respective DQ for any given cycle of the burst. Data mask timings match data bit timing, but are inputs only. Internal data mask loading is identical to data bit loading to ensure matched system timing. Data Mask Timing Data Mask Timing 46 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 8/6/2014 IS43/46LD16640A IS43/46LD32320A Write Data Mask – Second Data Bit Masked Integrated Silicon Solution, Inc. — www.issi.com 47 Rev. A 8/6/2014 IS43/46LD16640A IS43/46LD32320A PRECHARGE The PRECHARGE command is used to precharge or close a bank that has been activated. The PRECHARGE command is initiated with CS# LOW, CA0 HIGH, CA1 HIGH, CA2 LOW, and CA3 HIGH at the rising edge of the clock. The PRECHARGE command can be used to precharge each bank independently or all banks simultaneously. For 4-bank devices, the AB flag and bank address bits BA0 and BA1 are used to determine which bank(s) to precharge. For 8-bank devices, the AB flag and the bank address bits BA0, BA1, and BA2 are used to determine which bank(s) to precharge. The precharged bank(s) will be available for subsequent row access tRPab after an all bank PRECHARGE command is issued, or tRPpb after a single-bank PRECHARGE command is issued. In order to ensure that 8-bank devices can meet the instantaneous current demand required to operate, the row precharge time (tRP) for an all bank PRECHARGE in 8-bank devices (tRPab) will be longer than the row precharge time for a single-bank PRECHARGE (tRPpb). For 4-bank devices, tRPab is equal to tRPpb. Bank Selection for PRECHARGE by Address Bits AB (CA4r) BA2 (CA9r) BA1 (CA8r) BA0 (CA7r) 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 1 Don't care 0 0 1 1 0 0 1 1 Don't care 0 1 0 1 0 1 0 1 Don't care Precharged Bank(s) Precharged Bank(s) 4-bank device 8-bank device Bank 0 only Bank 1 only Bank 2 only Bank 3 only Bank 0 only Bank 1 only Bank 2 only Bank 3 only All Banks Bank 0 only Bank 1 only Bank 2 only Bank 3 only Bank 4 only Bank 5 only Bank 6 only Bank 7 only All Banks Bank selection for Precharge by address bits 48 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 8/6/2014 IS43/46LD16640A IS43/46LD32320A READ Burst operation Followed by PRECHARGE For the earliest possible precharge, the PRECHARGE command can be issued BL/2 clock cycles after a READ command. A new bank ACTIVATE command can be issued to the same bank after the row precharge time (tRP) has elapsed. A PRECHARGE command cannot be issued until after tRAS is satisfied. The minimum READ-to-PRECHARGE time (tRTP) must also satisfy a minimum analog time from the rising clock edge that initiates the last 4-bit prefetch of a READ command. tRTP begins BL/2 2 clock cycles after the READ command. If the burst is truncated by a BST command, the effective BL value is used to calculate when tRTP begins. READ Burst Followed by PRECHARGE – RL = 3, BL = 8, RU(tRTP(MIN)/tCK) = 2 t t Burst Read followed by Precharge: RL=3, BL=8, RU( RTP(min)/ CK)=2 Integrated Silicon Solution, Inc. — www.issi.com 49 Rev. A 8/6/2014 IS43/46LD16640A IS43/46LD32320A READ Burst Followed by PRECHARGE – RL = 3, BL = 4, RU(tRTP(MIN)/tCK) = 3 Burst Read followed by Precharge: RL=3, BL=4, RU( tRTP(min)/tCK) = 3 50 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 8/6/2014 IS43/46LD16640A IS43/46LD32320A WRITE Burst operation Followed by PRECHARGE For WRITE cycles, a WRITE recovery time ( tWR) must be provided before a PRECHARGE command can be issued. This delay is referenced from the last valid burst input data to the completion of the burst WRITE. The PRECHARGE command must not be issued prior to the tWR delay. These devices write data to the array in prefetch quadruples (prefetch = 4). An internal WRITE operation can only begin after a prefetch group has been completely latched. The minimum WRITE-to-PRECHARGE time for commands to the same bank is WL + BL/2 + 1 + RU(tWR/tCK) clock cycles. For untruncated bursts, BL is the value set in the mode register. For truncated bursts, BL is the effective burst length. WRITE Burst Followed by PRECHARGE – WL = 1, BL = 4 Burst Write followed by Precharge: WL=1, BL=4 Integrated Silicon Solution, Inc. — www.issi.com 51 Rev. A 8/6/2014 IS43/46LD16640A IS43/46LD32320A Auto Precharge Before a new row can be opened in an active bank, the active bank must be precharged using either the PRECHARGE command or the auto precharge function. When a READ or WRITE command is issued to the device, the auto precharge bit (AP) can be set to enable the active bank to automatically begin precharge at the earliest possible moment during the burst READ or WRITE cycle. If AP is LOW when the READ or WRITE command is issued, then normal READ or WRITE burst operation is executed and the bank remains active at the completion of the burst. If AP is HIGH when the READ or WRITE command is issued, the auto precharge function is engaged. This feature enables the PRECHARGE operation to be partially or completely hidden during burst READ cycles (dependent upon READ or WRITE latency), thus improving system performance for random data access. READ Burst with Auto Precharge If AP (CA0f) is HIGH when a READ command is issued, the READ with auto precharge function is engaged. These devices start an auto precharge on the rising edge of the clock BL/2 or BL/2 - 2 + RU(tRTP/ tCK) clock cycles later than the READ with auto precharge command, whichever is greater. For auto precharge calculations see following table. 52 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 8/6/2014 IS43/46LD16640A IS43/46LD32320A LPDDR2-S4: PRECHARGE and Auto Precharge Clarification LPDDR2-S4: Precharge & Auto Precharge clarification From Command To Command Precharge (to same Bank as Read) Precharge All Precharge (to same Bank as Read) BST (for Reads) Precharge All Precharge (to same Bank as Read w/AP) Precharge All Read Minimum Delay between "From Command" to Note Unit "To Command" s BL/2 + max(2, RU(tRTP/tCK)) - 2 BL/2 + max(2, RU(tRTP/tCK)) - 2 1 1 BL/2 + max(2, RU(tRTP/tCK)) - 2 BL/2 + max(2, RU(tRTP/tCK)) - 2 BL/2 + max(2, RU( RTP/ CK)) - 2 + Activate (to same Bank as Read w/AP) RU(tRP /tCK) Read w/AP Write or Write w/AP (same bank) illegal t Write or Write w/AP (different bank) RL + BL/2 + RU( DQSCKmax/tCK) - WL + 1 Read or Read w/AP (same bank) illegal Read or Read w/AP (different bank) BL/2 Precharge (to same Bank as Write) WL + BL/2 + RU(tWR/tCK) + 1 Write Precharge All WL + BL/2 + RU(tWR/tCK) + 1 Precharge (to same Bank as Write) BST WL + RU(tWR/tCK) + 1 (for Writes) Precharge All WL + RU(tWR/tCK) + 1 Precharge (to same Bank as Write w/AP) WL + BL/2 + RU(tWR/tCK) + 1 Precharge All WL + BL/2 + RU(tWR/tCK) + 1 Activate (to same Bank as Write w/AP) WL + BL/2 + RU(tWR/tCK) + 1 + RU(tRPpb/tCK) Write w/AP Write or Write w/AP (same bank) illegal Write or Write w/AP (different bank) BL/2 Read or Read w/AP (same bank) illegal Read or Read w/AP (different bank) WL + BL/2 + RU(tWTR/tCK) + 1 Precharge (to same Bank as Precharge) 1 Precharge Precharge All 1 Precharge Precharge 1 All Precharge All 1 clks clks clks clks clks clks 1 1 1 1 1,2 1 clks clks clks clks clks clks clks clks clks clks clks clks clks clks clks clks clks clks clks clks 1 3 3 3 3 1 1 1 1 1 1 1 3 3 3 3 1 1 1 1 Notes: 1. For a given bank, the PRECHARGE period should be counted from the latest PRECHARGE command—either a one-bank PRECHARGE or PRECHARGE ALL—issued to that bank. The PRECHARGE period is satisfied after tRP, depending on the latest PRECHARGE command issued to that bank. 2. Any command issued during the specified minimum delay time is illegal. 3. After READ with auto precharge, seamless READ operations to different banks are supported. After WRITE with auto precharge, seamless WRITE operations to different banks are supported. READ with auto precharge and WRITE with auto precharge must not be interrupted or truncated. Following an auto precharge operation, an ACTIVATE command can be issued to the same bank if the following two conditions are satisfied simultaneously: • The RAS precharge time (tRP) has been satisfied from the clock at which the auto precharge begins. • The RAS cycle time (tRC) from the previous bank activation has been satisfied. Integrated Silicon Solution, Inc. — www.issi.com 53 Rev. A 8/6/2014 IS43/46LD16640A IS43/46LD32320A READ Burst with Auto Precharge – RL = 3, BL = 4, RU(tRTP(MIN)/tCK) = 2 - 54 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 8/6/2014 IS43/46LD16640A IS43/46LD32320A WRITE Burst operation Followed by PRECHARGE For WRITE cycles, a WRITE recovery time ( tWR) must be provided before a PRECHARGE command can be issued. This delay is referenced from the last valid burst input data to the completion of the burst WRITE. The PRECHARGE command must not be issued prior to the tWR delay. These devices write data to the array in prefetch quadruples (prefetch = 4). An internal WRITE operation can only begin after a prefetch group has been completely latched. The minimum WRITE-to-PRECHARGE time for commands to the same bank is WL + BL/2 + 1 + RU(tWR/tCK) clock cycles. For untruncated bursts, BL is the value set in the mode register. For truncated bursts, BL is the effective burst length. WRITE Burst Followed by PRECHARGE – WL = 1, BL = 4 CK# CK T0 T1 T2 T3 T4 T5 T6 T7 T8 BL/2 RL = 3 CA[9:0] Bankm Col addr a col addr a Bankm row addr ≥ t RPpb t RTP CMD READ w/AP NOP Row addr NOP NOP NOP ACTIVATE NOP NOP NOP DQS# DQS DQ DOUT A0 DOUT A1 DOUT A2 DOUT A3 Transitioning data Integrated Silicon Solution, Inc. — www.issi.com 55 Rev. A 8/6/2014 IS43/46LD16640A IS43/46LD32320A REFRESH The REFRESH command is initiated with CS# LOW, CA0 LOW, CA1 LOW, and CA2 HIGH at the rising edge of the clock. Per-bank REFRESH is initiated with CA3 LOW at the rising edge of the clock. All-bank REFRESH is initiated with CA3 HIGH at the rising edge of the clock. Per-bank REFRESH is only supported in devices with eight banks. A per-bank REFRESH command (REFpb) performs a per-bank REFRESH operation to the bank scheduled by the bank counter in the memory device. The bank sequence for per-bank REFRESH is fixed to be a sequential round-robin: 0-1-2-3-4-5-6-7-0-1-.... The bank count is synchronized between the controller and the SDRAM by resetting the bank count to zero. Synchronization can occur upon issuing a RESET command or at every exit from self refresh. Bank addressing for the per-bank REFRESH count is the same as established for the single-bank PRECHARGE command. A bank must be idle before it can be refreshed. The controller must track the bank being refreshed by the per-bank REFRESH command. The REFpb command must not be issued to the device until the following conditions have been met: • tRFCab has been satisfied after the prior REFab command • tRFCpb has been satisfied after the prior REFpb command • tRP has been satisfied after the prior PRECHARGE command to that bank • tRRD has been satisfied after the prior ACTIVATE command (if applicable, for example after activating a row in a different bank than the one affected by the REFpb command) The target bank is inaccessible during per-bank REFRESH cycle time (tRFCpb), however, other banks within the device are accessible and can be addressed during the cycle. During the REFpb operation, any of the banks other than the one being refreshed can be maintained in an active state or accessed by a READ or WRITE command. When the per-bank REFRESH cycle has completed, the affected bank will be in the idle state. After issuing REFpb, the following conditions must be met: • tRFCpb must be satisfied before issuing a REFab command • tRFCpb must be satisfied before issuing an ACTIVATE command to the same bank • tRRD must be satisfied before issuing an ACTIVATE command to a different bank • tRFCpb must be satisfied before issuing another REFpb command 56 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 8/6/2014 IS43/46LD16640A IS43/46LD32320A An all-bank REFRESH command (REFab) issues a REFRESH command to all banks. All banks must be idle when REFab is issued (for instance, by issuing a PRECHARGE ALL command prior to issuing an all-bank REFRESH command). REFab also synchronizes the bank count between the controller and the SDRAM to zero. The REFab command must not be issued to the device until the following conditions have been met: • tRFCab has been satisfied following the prior REFab command • tRFCpb has been satisfied following the prior REFpb command • tRP has been satisfied following the prior PRECHARGE commands After an all-bank REFRESH cycle has completed, all banks will be idle. After issuing REFab: • tRFCab latency must be satisfied before issuing an ACTIVATE command • tRFCab latency must be satisfied before issuing a REFab or REFpb command REFRESH Command Scheduling Separation Requirements Command Scheduling Separations related to Refresh Symbol minimum delay from to Activate cmd to any bank . REFpb REFab Activate cmd to same bank as REFpb REFpb Activate cmd to different bank than REFpb REFpb affecting an idle bank (different bank than Activate) t RFCab REFab t RFCpb REFpb REFpb t RRD Activate Notes REFab 1 Activate cmd to different bank than prior Activate Note: A bank must be in the idle state before it is refreshed, so REFab is prohibited following an ACTIVATE command. REFpb is supported only if it affects a bank that is in the idle state. Integrated Silicon Solution, Inc. — www.issi.com 57 Rev. A 8/6/2014 IS43/46LD16640A IS43/46LD32320A The LPDDR2 devices provide significant flexibility in scheduling REFRESH commands as long as the required boundary conditions are met (see figure of tSRF Definition). In the most straightforward implementations, a REFRESH command should be scheduled every tREFI. In this case, self refresh can be entered at any time. Users may choose to deviate from this regular refresh pattern, for instance, to enable a period in which no refresh is required. As an example, using a 1Gb LPDDR2 device, the user can choose to issue a refresh burst of 4096 REFRESH commands at the maximum supported rate (limited by tREFBW), followed by an extended period without issuing any REFRESH commands, until the refresh window is complete. The maximum supported time without REFRESH commands is calculated as follows: tREFW - (R/8) × tREFBW= tREFW - R × 4 × tRFCab. For example, a 1Gb device at TC ≤ 85˚C can be operated without a refresh for up to 32ms - 4096 × 4 × 130ns ≈ 30ms. Both the regular and the burst/pause patterns can satisfy refresh requirements if they are repeated in every 32ms window. It is critical to satisfy the refresh requirement in every rolling refresh window during refresh pattern transitions. The supported transition from a burst pattern to a regular distributed pattern is shown in figure of Supported Transition from Repetitive REFRESH Burst . If this transition occurs immediately after the burst refresh phase, all rolling tREFW intervals will meet the minimum required number of REFRESH commands. A nonsupported transition is shown in Figure of Nonsupported Transition from Repetitive REFRESH Burst . In this example, the regular refresh pattern starts after the completion of the pause phase of the burst/pause refresh pattern. For several rolling tREFW intervals, the minimum number of REFRESH commands is not satisfied. Understanding this pattern transition is extremely important, even when only one pattern is employed. In self refresh mode, a regular distributed refresh pattern must be assumed. ISSI recommends entering self refresh mode immediately following the burst phase of a burst/ pause refresh pattern; upon exiting self refresh, begin with the burst phase (see Figure of Recommended Self Refresh Entry and Exit ). 58 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 8/6/2014 IS43/46LD16640A IS43/46LD32320A Regular Distributed Refresh Pattern Notes: 1. Compared to repetitive burst REFRESH with subsequent REFRESH pause. 2. As an example, in a 1Gb LPDDR2 device at TC ≤ 85˚C, the distributed refresh pattern has one REFRESH command per 7.8μs; the burst refresh pattern has one REFRESH command per 0.52μs, followed by ≈ 30ms without any REFRESH command. Integrated Silicon Solution, Inc. — www.issi.com 59 Rev. A 8/6/2014 IS43/46LD16640A IS43/46LD32320A Supported Transition from Repetitive REFRESH Burst Notes: 1. Shown with subsequent REFRESH pause to regular distributed refresh pattern. 2. As an example, in a 1Gb LPDDR2 device at TC ≤ 85˚C, the distributed refresh pattern has one REFRESH command per 7.8μs; the burst refresh pattern has one REFRESH command per 0.52μs, followed by ≈ 30ms without any REFRESH command 60 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 8/6/2014 IS43/46LD16640A IS43/46LD32320A Nonsupported Transition from Repetitive REFRESH Burst Notes: 1. Shown with subsequent REFRESH pause to regular distributed refresh pattern. 2. There are only ≈ 2048 REFRESH commands in the indicated tREFW window. This does not provide the required minimum number of REFRESH commands (R). Integrated Silicon Solution, Inc. — www.issi.com 61 Rev. A 8/6/2014 IS43/46LD16640A IS43/46LD32320A Recommended Self Refresh Entry and Exit Note: In conjunction with a burst/pause refresh pattern REFRESH Requirements 1. Minimum Number of REFRESH Commands Mobile LPDDR2 requires a minimum number, R, of REFRESH (REFab) commands within any rolling refresh window (tREFW = 32 ms @ MR4[2:0] = 011 or TC ≤ 85˚C). For actual values per density and the resulting average refresh interval (tREFI). For tREFW and tREFI refresh multipliers at different MR4 settings, see the MR4 Device Temperature (MA[7:0] = 04h) table. For devices supporting per-bank REFRESH, a REFab command can be replaced by a full cycle of eight REFpb commands. 2. Burst REFRESH Limitation To limit current consumption, a maximum of eight REFab commands can be issued in any rolling tREFBW (tREFBW = 4 × 8 × tRFCab). This condition does not apply if REFpb commands are used. 3. REFRESH Requirements and Self Refresh If any time within a refresh window is spent in self refresh mode, the number of required REFRESH commands in that window is reduced to the following: R’ = RU〔tSRF / tREFI〕= R - RU ×〔R x tSRF / tREFW〕 Where RU represents the round-up function. 62 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 8/6/2014 IS43/46LD16640A IS43/46LD32320A tSRF Definition Notes: 1. Time in self refresh mode is fully enclosed in the refresh window (tREFW). 2. At self refresh entry. 3. At self refresh exit. 4. Several intervals in self refresh during one tREFW interval. In this example, tSRF = tSRF1 +tSRF2. Integrated Silicon Solution, Inc. — www.issi.com 63 Rev. A 8/6/2014 IS43/46LD16640A IS43/46LD32320A All-Bank REFRESH Operation Per-Bank REFRESH Operation Notes: 1. Prior to T0, the REFpb bank counter points to bank 0. 2. Operations to banks other than the bank being refreshed are supported during the tRFCpb period 64 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 8/6/2014 IS43/46LD16640A IS43/46LD32320A SELF REFRESH Operation The SELF REFRESH command can be used to retain data in the array, even if the rest of the system is powered down. When in the self refresh mode, the device retains data without external clocking. The device has a built-in timer to accommodate SELF REFRESH operation. The SELF REFRESH command is executed by taking CKE LOW, CS# LOW, CA0 LOW, CA1 LOW, and CA2 HIGH at the rising edge of the clock. CKE must be HIGH during the clock cycle preceding a SELF REFRESH command. A NOP command must be driven in the clock cycle following the SELF REFRESH command. After the power-down command is registered, CKE must be held LOW to keep the device in self refresh mode. LPDDR2-S4 devices can operate in self refresh mode in both the standard and extended temperature ranges. These devices also manage self refresh power consumption when the operating temperature changes, resulting in the lowest possible power consumption across the operating temperature range. After the device has entered self refresh mode, all external signals other than CKE are“Don’t Care.” For proper self refresh operation, power supply pins (VDD1, VDD2, VDDQ, and VDDCA) must be at valid levels. VDDQ can be turned off during self refresh. If VDDQ is turned off, VREFDQ must also be turned off. Prior to exiting self refresh, both VDDQ and VREFDQ must be within their respective minimum/maximum operating ranges . VREFDQ can be at any level between 0 and VDDQ; VREFCA can be at any level between 0 and VDDCA during self refresh. Before exiting self refresh, VREFDQ and VREFCA must be within specified limits (see AC and DC Logic Input Measurement Levels for Single-Ended Signals . After entering self refresh mode, the device initiates at least one all-bank REFRESH command internally during tCKESR. The clock is internally disabled during SELF REFRESH operation to save power. The device must remain in self refresh mode for at least tCKESR. The user can change the external clock frequency or halt the external clock one clock after self refresh entry is registered; however, the clock must be restarted and stable before the device can exit SELF REFRESH operation. Exiting self refresh requires a series of commands. First, the clock must be stable prior to CKE returning HIGH. After the self refresh exit is registered, a minimum delay, at least equal to the self refresh exit interval (tXSR), must be satisfied before a valid command can be issued to the device. This provides completion time for any internal refresh in progress. For proper operation, CKE must remain HIGH throughout tXSR, except during self refresh re-entry. NOP commands must be registered on each rising clock edge during tXSR. Using self refresh mode introduces the possibility that an internally timed refresh event could be missed when CKE is driven HIGH for exit from self refresh mode. Upon exiting self refresh, at least one REFRESH command (one all-bank command or eight per-bank commands) must be issued before issuing a subsequent SELF REFRESH command. Integrated Silicon Solution, Inc. — www.issi.com 65 Rev. A 8/6/2014 IS43/46LD16640A IS43/46LD32320A SELF REFRESH Operation Notes: 1. Input clock frequency can be changed or stopped during self refresh, provided that upon exiting self-refresh, a minimum of two cycles of stable clocks (tINIT2) are provided, and the clock frequency is between the minimum and maximum frequencies for the particular speed grade. 2. The device must be in the all banks idle state prior to entering self refresh mode. 3. tXSR begins at the rising edge of the clock after CKE is driven HIGH. 4. A valid command can be issued only after tXSR is satisfied. NOPs must be issued during tXSR. 66 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 8/6/2014 IS43/46LD16640A IS43/46LD32320A Partial-Array Self Refresh – Bank Masking Devices in densities of 64Mb–512Mb are comprised of four banks; densities of 1Gb and higher are comprised of eight banks. Each bank can be configured independently whether or not a SELF REFRESH operation will occur in that bank. One 8-bit mode register (accessible via the MRW command) is assigned to program the bank-masking status of each bank up to eight banks. For bank masking bit assignments, see the MR16 PASR Bank Mask (MA[7:0] = 010h) and MR16 Op-Code Bit Definitions tables. The mask bit to the bank enables or disables a refresh operation of the entire memory space within the bank. If a bank is masked using the bank mask register, a REFRESH operation to the entire bank is blocked and bank data retention is not guaranteed in self refresh mode. To enable a REFRESH operation to a bank, the corresponding bank mask bit must be programmed as “unmasked.” When a bank mask bit is unmasked, the array space being refreshed within that bank is determined by the programmed status of the segment mask bits. Partial-Array Self Refresh – Segment Masking Programming segment mask bits is similar to programming bank mask bits. For densities 1Gb and higher, eight segments are used for masking (see the MR17 PASR Segment Mask (MA[7:0] = 011h) and MR17 PASR Segment Mask Definitions tables). A mode register is used for programming segment mask bits up to eight bits. For densities less than 1Gb, segment masking is not supported. When the mask bit to an address range (represented as a segment) is programmed as“masked,” a REFRESH operation to that segment is blocked. Conversely, when a segment mask bit to an address range is unmasked, refresh to that segment is enabled. A segment masking scheme can be used in place of or in combination with a bank masking scheme. Each segment mask bit setting is applied across all banks. For segment masking bit assignments, see the tables noted above. Bank and Segment Masking Example Segment Mask (MR17) Bank Mask (MR16) Bank 0 Bank 1 Bank 2 Bank 3 Bank 4 Bank 5 Bank 6 Bank 7 0 1 0 0 0 0 0 1 Segment 0 0 – M – – – – – M Segment 1 0 – M – – – – – M Segment 2 1 M M M M M M M M Segment 3 0 – M – – – – – M Segment 4 0 – M – – – – – M Segment 5 0 – M – – – – – M Segment 6 0 – M – – – – – M Segment 7 1 M M M M M M M M Note: This table provides values for an 8-bank device with REFRESH operations masked to banks 1 and 7, and segments 2 and 7. Integrated Silicon Solution, Inc. — www.issi.com 67 Rev. A 8/6/2014 IS43/46LD16640A IS43/46LD32320A MODE REGISTER READ The MODE REGISTER READ (MRR) command is used to read configuration and status data from SDRAM mode registers. The MRR command is initiated with CS# LOW, CA0 LOW, CA1 LOW, CA2 LOW, and CA3 HIGH at the rising edge of the clock. The mode register is selected by CA1f–CA0f and CA9r–CA4r. The mode register contents are available on the first data beat of DQ[7:0] after RL × tCK + tDQSCK + tDQSQ and following the rising edge of the clock where MRR is issued. Subsequent data beats contain valid but undefined content, except in the case of the DQ calibration function, where subsequent data beats contain valid content as described in Data Calibration Pattern Description. All DQS are toggled for the duration of the mode register READ burst. The MRR command has a burst length of four. MRR operation (consisting of the MRR command and the corresponding data traffic) must not be interrupted. The MRR command period (tMRR) is two clock cycles. MRR Timing – RL = 3, tMRR = 2 Notes: 1. MRRs to DQ calibration registers MR32 and MR40 are described in DQ Calibration . 2. Only the NOP command is supported during tMRR. 3. Mode register data is valid only on DQ[7:0] on the first beat. Subsequent beats contain valid but undefined data. DQ[MAX:8] contain valid but undefined data for the duration of the MRR burst. 4. Minimum MRR to write latency is RL + RU(tDQSCKmax/tCK) + 4/2 + 1 - WL clock cycles. 5. Minimum MRR to MRW latency is RL + RU(tDQSCKmax/tCK) + 4/2 + 1 clock cycles. 68 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 8/6/2014 IS43/46LD16640A IS43/46LD32320A READ bursts and WRITE bursts cannot be truncated by MRR. Following a READ command, the MRR command must not be issued before BL/2 clock cycles have completed. Following a WRITE command, the MRR command must not be issued before WL + 1 + BL/2 + RU(tWTR/tCK) clock cycles have completed. If a READ or WRITE burst is truncated with a BST command, the effective burst length of the truncated burst should be used for the BL value. READ to MRR Timing – RL = 3, tMRR = 2 Notes: 1. The minimum number of clock cycles from the burst READ command to the MRR command is BL/2. 2. Only the NOP command is supported during tMRR. Burst WRITE Followed by MRR – RL = 3, WL = 1, BL = 4 Notes: 1. The minimum number of clock cycles from the burst WRITE command to the MRR command is [WL + 1 + BL/2 + RU(tWTR/ tCK)]. 2. Only the NOP command is supported during tMRR. Integrated Silicon Solution, Inc. — www.issi.com 69 Rev. A 8/6/2014 IS43/46LD16640A IS43/46LD32320A Temperature Sensor LPDDR2 devices feature a temperature sensor whose status can be read from MR4. This sensor can be used to determine an appropriate refresh rate, determine whether AC timing derating is required in the extended temperature range, and/or monitor the operating temperature. Either the temperature sensor or the device operating temperature can be used to determine whether operating temperature requirements are being met (see Operating Temperature Range table). Temperature sensor data can be read from MR4 using the mode register read protocol. Upon exiting self-refresh or power-down, the device temperature status bits will be no older than tTSI. When using the temperature sensor, the actual device case temperature may be higher than the operating temperature specification that applies for the standard or extended temperature ranges (see table noted above). For example, TCASE could be above 85˚C when MR4[2:0] equals 011b. To ensure proper operation using the temperature sensor, applications must accommodate the parameters in the temperature sensor definitions table. Temperature Sensor Definitions and Operating Conditions Parameter Symbol Max/Min System Temperature Gradient TempGradient Max MR4 Read Interval Max ReadInterval Temperature Sensor Interval tTSI Max System Response Delay SysRespDela y Max Device Temperature Margin TempMargin Max Value Unit Notes Maximum temperature gradient System Dependent C/s experienced by the memory device at the temperature of interest over a range of 2°C. Time period between MR4 READs from the System Dependent ms system. Maximum delay between internal updates 16 ms of MR4. Maximum response time from an MR4 System Dependent ms READ to the system response. Margin above maximum temperature to 2 C support controller response. LPDDR2 devices accommodate the temperature margin between the point at which the device temperature enters the extended temperature range and the point at which the controller reconfigures the system accordingly. To determine the required MR4 polling frequency, the system must use the maximum TempGradient and the maximum response time of the system according to the following equation: TempGradient × (ReadInterval + tTSI + SysRespDelay) ≤ 2°C For example, if TempGradient is 10˚C/s and the SysRespDelay is 1ms: 10°C / s × (ReadInterval + 32ms + 1ms) ≤ 2°C In this case, ReadInterval must not exceed 167ms 70 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 8/6/2014 IS43/46LD16640A IS43/46LD32320A Temperature Sensor Timing DQ Calibration Mobile LPDDR2 devices feature a DQ calibration function that outputs one of two predefined system timing calibration patterns. For x16 devices, pattern A (MRR to MRR32), and pattern B (MRR to MRR40), will return the specified pattern on DQ0 and DQ8; x32 devices return the specified pattern on DQ0, DQ8, DQ16, and DQ24. For x16 devices, DQ[7:1] and DQ[15:9] drive the same information as DQ0 during the MRR burst. For x32 devices, DQ[7:1], DQ[15:9], DQ[23:17], and DQ[31:25] drive the same information as DQ0 during the MRR burst. MRR DQ calibration commands can occur only in the idle state. Integrated Silicon Solution, Inc. — www.issi.com 71 Rev. A 8/6/2014 IS43/46LD16640A IS43/46LD32320A MR32 and MR40 DQ Calibration Timing – RL = 3, tMRR = 2 Note: Only the NOP command is supported during Tmrr 72 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 8/6/2014 IS43/46LD16640A IS43/46LD32320A Data Calibration Pattern Description Pattern MR# Bit Time 0 Bit Time 1 Bit Time 2 Bit Time 3 Notes Pattern A MR32 1 0 1 0 Reads to MR32 return DQ callibration pattern A Pattern B MR40 0 0 1 1 Reads to MR32 return DQ callibration pattern B MODE REGISTER WRITE Command The MODE REGISTER WRITE (MRW) command is used to write configuration data to the mode registers. The MRW command is initiated with CS# LOW, CA0 LOW, CA1 LOW, CA2 LOW, and CA3 LOW at the rising edge of the clock. The mode register is selected by CA1f–CA0f, CA9r–CA4r. The data to be written to the mode register is contained in CA9f–CA2f. The MRW command period is defined by tMRW. MRWs to read-only registers have no impact on the functionality of the device. MRW can only be issued when all banks are in the idle precharge state. One method of ensuring that the banks are in this state is to issue a PRECHARGE ALL command. MODE REGISTER WRITE Timing – RL = 3, tMRW = 5 CK# CK T0 T1 T2 Tx Tx + 1 t MRW CA[9:0] CMD MR addr MR addr NOP 2 Ty 1 Ty + 1 Ty + 2 t MRW MR data MRW Tx + 2 NOP 2 MR data MRW NOP 2 NOP 2 Valid Truth Table for MRR and MRW Current State All Banks idle Bank(s) Active Command Intermediate State Next State MRR Mode Register Reading (All Banks idle) All Banks idle MRW Mode Register Writing (All Banks idle) All Banks idle MRW (Reset) Restting (Device Auto-Init) All Banks idle MRR Mode Register Reading (Bank(s) idle) Bank(s) Active MRW Not Allowed Not Allowed MRW (Reset) Not Allowed Not Allowed Notes: 1. At time Ty, the device is in the idle state. 2. Only the NOP command is supported during tMRW. Integrated Silicon Solution, Inc. — www.issi.com 73 Rev. A 8/6/2014 IS43/46LD16640A IS43/46LD32320A MRW RESET Command The MRW RESET command brings the device to the device auto initialization (resetting) state in the power-on initialization sequence (see RESET Command under Power-Up ). The MRW RESET command can be issued from the idle state. This command resets all mode registers to their default values. Only the NOP command is supported during tINIT4. After MRW RESET, boot timings must be observed until the device initialization sequence is complete and the device is in the idle state. Array data is undefined after the MRW RESET command has completed. For MRW RESET timing, see Figure of Voltage Ramp and Initialization Sequence. MRW ZQ Calibration Commands The MRW command is used to initiate a ZQ calibration command that calibrates output driver impedance across process, temperature, and voltage. LPDDR2-S4 devices support ZQ calibration. To achieve tighter tolerances, proper ZQ calibration must be performed. There are four ZQ calibration commands and related timings: tZQINIT, tZQRESET, tZQCL, and tZQCS. tZQINIT is used for initialization calibration; tZQRESET is used for resetting ZQ to the default output impedance; tZQCL is used for long calibration(s); and tZQCS is used for short calibration(s). See the MR10 Calibration (MA[7:0] = 0Ah) table for ZQ calibration command code definitions. ZQINIT must be performed for LPDDR2 devices. ZQINIT provides an output impedance accuracy of ±15%. After initialization, the ZQ calibration long (ZQCL) can be used to recalibrate the system to an output impedance accuracy of ±15%. A ZQ calibration short (ZQCS) can be used periodically to compensate for temperature and voltage drift in the system. ZQRESET resets the output impedance calibration to a default accuracy of ±30% across process, voltage, and temperature. This command is used to ensure output impedance accuracy to ±30% when ZQCS and ZQCL commands are not used. One ZQCS command can effectively correct at least 1.5% (ZQ correction) of output impedance errors within tZQCS for all speed bins, assuming the maximum sensitivities specified in the tables "output Driver Sensitivity Definition" and "Output Driver Temperature and Voltage Sensitivity" (page 133) are met. The appropriate interval between ZQCS commands can be determined using these tables and system-specific parameters. LPDDR2 devices are subject to temperature drift rate (Tdriftrate) and voltage drift rate (Vdriftrate) in various applications. To accommodate drift rates and calculate the necessary interval between ZQCS commands, apply the following formula. ZQcorrection / 〔(Tsens × Tdriftrate) + (Vsens × Vdriftrate)〕 Where Tsens = MAX (dRONdT) and Vsens = MAX (dRONdV) define temperature and voltage 74 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 8/6/2014 IS43/46LD16640A IS43/46LD32320A sensitivities. For example, if Tsens = 0.75%/˚C, Vsens = 0.20%/mV, Tdriftrate = 1˚C/sec, and Vdriftrate =15 mV/ sec, then the interval between ZQCS commands is calculated as: 1.5 / 〔(0.75 × 1) + (0.20 × 15)〕= 0.4s A ZQ calibration command can only be issued when the device is in the idle state with all banks precharged. No other activities can be performed on the data bus during calibration periods (tZQINIT, tZQCL, or tZQCS). The quiet time on the data bus helps to accurately calibrate output impedance. There is no required quiet time after the ZQRESET command. If multiple devices share a single ZQ resistor, only one device can be calibrating at any given time. After calibration is complete, the ZQ ball circuitry is disabled to reduce power consumption. In systems sharing a ZQ resistor between devices, the controller must prevent tZQINIT, tZQCS, and tZQCL overlap between the devices. ZQRESET overlap is acceptable. If the ZQ resistor is absent from the system, ZQ must be connected to VDDCA. In this situation, the device must ignore ZQ calibration commands and the device will use the default calibration settings. ZQ Timings Notes: 1. Only the NOP command is supported during ZQ calibrations. 2. CKE must be registered HIGH continuously during the calibration period. 3. All devices connected to the DQ bus should be High-Z during the calibration process. Integrated Silicon Solution, Inc. — www.issi.com 75 Rev. A 8/6/2014 IS43/46LD16640A IS43/46LD32320A ZQ External Resistor Value, Tolerance, and Capacitive Loading To use the ZQ calibration function, a 240 ohm (±1% tolerance) external resistor must be connected between the ZQ pin and ground. A single resistor can be used for each device or one resistor can be shared between multiple devices if the ZQ calibration timings for each device do not overlap. The total capacitive loading on the ZQ pin must be limited. Power-Down Power-down is entered synchronously when CKE is registered LOW and CS# is HIGH at the rising edge of clock. A NOP command must be driven in the clock cycle following power-down entry. CKE must not go LOW while MRR, MRW, READ, or WRITE operations are in progress. CKE can go LOW while any other operations such as ACTIVATE, PRECHARGE, auto precharge, or REFRESH are in progress, but the power-down IDD specification will not be applied until such operations are complete. If power-down occurs when all banks are idle, this mode is referred to as idle power-down; if power-down occurs when there is a row active in any bank, this mode is referred to as active power-down. Entering power-down deactivates the input and output buffers, excluding CK, CK#, and CKE. In power-down mode, CKE must be held LOW; all other input signals are “Don’t Care.” CKE LOW must be maintained until tCKE is satisfied. VREFCA must be maintained at a valid level during power-down. VDDQ can be turned off during power-down. If VDDQ is turned off, VREFDQ must also be turned off. Prior to exiting power-down, both VDDQ and VREFDQ must be within their respective minimum/maximum operating ranges (see AC and DC Operating Conditions). No refresh operations are performed in power-down mode. The maximum duration in power-down mode is only limited by the refresh requirements outlined in REFRESH Command. The power-down state is exited when CKE is registered HIGH. The controller must drive CS# HIGH in conjunction with CKE HIGH when exiting the power-down state. CKE HIGH must be maintained until tCKE is satisfied. A valid, executable command can be applied with power-down exit latency tXP after CKE goes HIGH. Power-down exit latency is defined in the AC Timing section. 76 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 8/6/2014 IS43/46LD16640A IS43/46LD32320A Power-Down Entry and Exit Timing Note: Input clock frequency can be changed or the input clock stopped during power-down, provided that the clock frequency is between the minimum and maximum specified frequencies for the speed grade in use, and that prior to power-down exit, a minimum of two stable clocks complete. CKE Intensive Environment REFRESH-to-REFRESH Timing in CKE Intensive Environments CK# CK t CKE CKE CMD t CKE t XP t CKE t REFI REFRESH t CKE t XP REFRESH Note: The pattern shown can repeat over an extended period of time. With this pattern, all AC and DC timing and voltage specifications with temperature and voltage drift are ensured. Integrated Silicon Solution, Inc. — www.issi.com 77 Rev. A 8/6/2014 IS43/46LD16640A IS43/46LD32320A READ to Power-Down Entry Read to Power-Down entry Notes: 1. CKE must be held HIGH until the end of the burst operation. 2. CKE can be registered LOW at (RL + RU(tDQSCK(MAX)/tCK) + BL/2 + 1) clock cycles after the clock on which the READ command is registered 78 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 8/6/2014 IS43/46LD16640A IS43/46LD32320A READ with Auto Precharge to Power-Down Entry Notes: 1. CKE must be held HIGH until the end of the burst operation. 2. CKE can be registered LOW at (RL + RU(tDQSCK/tCK)+ BL/2 + 1) clock cycles after the clock on which the READ command is registered. 3. BL/2 with tRTP = 7.5ns and tRAS (MIN) is satisfied. 4. Start internal PRECHARGE Integrated Silicon Solution, Inc. — www.issi.com 79 Rev. A 8/6/2014 IS43/46LD16640A IS43/46LD32320A WRITE to Power-Down Entry Note: CKE can be registered LOW at (WL + 1 + BL/2 + RU(tWR/tCK)) clock cycles after the clock on which the WRITE command is registered. 80 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 8/6/2014 IS43/46LD16640A IS43/46LD32320A WRITE with Auto Precharge to Power-Down Entry Write with Auto-precharge to Power-Down entry Notes: 1. CKE can be registered LOW at (WL + 1 + BL/2 + RU(tWR/tCK + 1) clock cycles after the WRITE command is registered. 2. Start internal PRECHARGE Integrated Silicon Solution, Inc. — www.issi.com 81 Rev. A 8/6/2014 IS43/46LD16640A IS43/46LD32320A REFRESH Command to Power-Down Entry Note: CKE can go LOW tIHCKE after the clock on which the REFRESH command is registered. ACTIVATE Command to Power-Down Entry Note: CKE can go LOW at tIHCKE after the clock on which the ACTIVATE command is registered PRECHARGE Command to Power-Down Entry Note: CKE can go LOW tIHCKE after the clock on which the PRECHARGE command is registered. 82 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 8/6/2014 IS43/46LD16640A IS43/46LD32320A MRR Command to Power-Down Entry Note: CKE can be registered LOW at (RL + RU(tDQSCK/tCK)+ BL/2 + 1) clock cycles after the clock on which the MRR command is registered. MRW Command to Power-Down Entry Note: CKE can be registered LOW tMRW after the clock on which the MRW command is registered Integrated Silicon Solution, Inc. — www.issi.com 83 Rev. A 8/6/2014 IS43/46LD16640A IS43/46LD32320A Deep Power-Down Deep power-down (DPD) is entered when CKE is registered LOW with CS# LOW, CA0 HIGH, CA1 HIGH, and CA2 LOW at the rising edge of the clock. The NOP command must be driven in the clock cycle following power-down entry. CKE must not go LOW while MRR or MRW operations are in progress. CKE can go LOW while other operations such as ACTIVATE, auto precharge, PRECHARGE, or REFRESH are in progress, however, deep power-down IDD specifications will not be applied until those operations complete. The contents of the array will be lost upon entering DPD mode. In DPD mode, all input buffers except CKE, all output buffers, and the power supply to internal circuitry are disabled within the device. VREFDQ can be at any level between 0 and VDDQ, and VREFCA can be at any level between 0 and VDDCA during DPD. All power supplies (including VREF) must be within the specified limits prior to exiting DPD (see AC and DC Operating Conditions). To exit DPD, CKE must be HIGH, tISCKE must be complete, and the clock must be stable. To resume operation, the device must be fully reinitialized using the power-up initialization sequence. Deep Power-Down Entry and Exit Timing Notes: 1. The initialization sequence can start at any time after Tx + 1. 2. tINIT3 and Tx + 1 refer to timings in the initialization sequence. For details, see Mode Register Definition 84 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 8/6/2014 IS43/46LD16640A IS43/46LD32320A Input Clock Frequency Changes and Stop Events LPDDR2 support Clock frequency changes and clock stop under the conditions detailed in this section Input Clock Frequency Changes and Clock Stop with CKE LOW During CKE LOW, Mobile LPDDR2 devices support input clock frequency changes and clock stop under the following conditions: • Refresh requirements are met • Only REFab or REFpb commands can be in process • Any ACTIVATE or PRECHARGE commands have completed prior to changing the frequency • Related timing conditions,tRCD and tRP, have been met prior to changing the frequency • The initial clock frequency must be maintained for a minimum of two clock cycles after CKE goes LOW • The clock satisfies tCH(abs) and tCL(abs) for a minimum of two clock cycles prior to CKE going HIGH For input clock frequency changes, tCK(MIN) and tCK(MAX) must be met for each clock cycle. After the input clock frequency is changed and CKE is held HIGH, additional MRW commands may be required to set the WR, RL, etc. These settings may require adjustment to meet minimum timing requirements at the target clock frequency. For clock stop, CK is held LOW and CK# is held HIGH. NO OPERATION Command The NO OPERATION (NOP) command prevents the device from registering any unwanted commands issued between operations. A NOP command can only be issued at clock cycle N when the CKE level is constant for clock cycle N-1 and clock cycle N. The NOP command has two possible encodings: CS# HIGH at the clock rising edge N; and CS# LOW with CA0, CA1, CA2 HIGH at the clock rising edge N. The NOP command will not terminate a previous operation that is still in process, such as a READ burst or WRITE burst cycle Integrated Silicon Solution, Inc. — www.issi.com 85 Rev. A 8/6/2014 IS43/46LD16640A IS43/46LD32320A Electrical Specifications Absolute Maximum DC Ratings Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Parameter Symbol Min Max Units Notes VDD1 supply voltage relative to VSS VDD1 -0.4 2.3 V 2 VDD2 supply voltage relative to VSS VDD2 -0.4 1.6 V 2 VDDCA -0.4 1.6 V 2,4 VDDQ -0.4 1.6 V 2,3 VIN, VOUT -0.4 1.6 V 125 °C VDDCA supply voltage relative to VSSCA VDDQ supply voltage relative to VSSQ Voltage on any ball relative to VSS Storage Temperature TSTG -55 5 Notes: 1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability 2. See “Power-Ramp” section in “Power-up, Initialization, and Power-Off” for relationships between power supplies. 3. VREFDQ 0.6 x VDDQ; however, VREFDQ may be VDDQ provided that VREFDQ 300mV. 4. VREFCA 0.6 x VDDCA; however, VREFCA may be VDDCA provided that VREFCA 300mV. 5. Storage Temperature is the case surface temperature on the center/top side of the LPDDR2 device. For the measurement conditions, please refer to JESD51-2 standard. 86 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 8/6/2014 IS43/46LD16640A IS43/46LD32320A Input/Output Capacitance LPDDR2 800-466 Parameter MIN MAX MIN MAX Unit Notes Input capacitance, CK and CK# C CK 1.0 2.0 1.0 2.0 pF 2, 3 Input capacitance delta, CK and CK# C DCK 0 0.20 0 0.25 pF 2, 3, 4 Input capacitance, all other inputonly pins CI 1.0 2.0 1.0 2.0 pF 2, 3, 5 Input capacitance delta, all other inputonly pins C DI –0.40 +0.40 –0.50 +0.50 pF 2, 3, 6 Input/output capacitance, DQ, DM, DQS, DQS# C IO 1.25 2.5 1.25 2.5 pF 2, 3, 7, 8 C DDQS 0 0.25 0 0.30 pF 2, 3, 8, 9 C DIO –0.5 +0.5 –0.6 +0.6 pF 2, 3, 8, 10 Input/output capacitance delta, DQS, DQS# Input/output capacitance delta, DQ, DM Symbol LPDDR2 400-200 Notes: 1. TC –25˚C to +105˚C; VDDQ = 1.14–1.3V; VDDCA = 1.14–1.3V; VDD1 = 1.7–1.95V; VDD2 = 1.14–1.3V). 2. This parameter applies to die devices only (does not include package capacitance). 3. This parameter is not subject to production testing. It is verified by design and characterization. The capacitance is measured according to JEP147 (procedure for measuring input capacitance using a vector network analyzer), with VDD1, VDD2, VDDQ, VSS, VSSCA, and VSSQ applied; all other pins are left floating. 4. Absolute value of CCK - CCK#. 5. CI applies to CS#, CKE, and CA[9:0]. 6. CDI = CI - 0.5 × (CCK + CCK#). 7. DM loading matches DQ and DQS. 8. MR3 I/O configuration drive strength OP[3:0] = 0001b (34.3 ohm typical). 9. Absolute value of CDQS and CDQS#. 10. CDIO = CIO - 0.5 × (CDQS + CDQS#) in byte-lane. 11. Maximum external load capacitance on ZQ pin: 5pF. Integrated Silicon Solution, Inc. — www.issi.com 87 Rev. A 8/6/2014 IS43/46LD16640A IS43/46LD32320A Operation or timing that is not specified is illegal, and after such an event, in order to guarantee proper operation, the LPDDR2 Device must be powered down and then restarted through the specialized initialization sequence before normal operation can continue. Recommended DC Operating Conditions Recommended LPDDR2-S4 DC Operating Conditions Symbol VDD1 LPDDR2-S4B Min Typ Max 1.70 1.80 1.95 DRAM Unit Core Power1 V VDD2 1.14 1.20 1.3 Core Power2 V VDDCA 1.14 1.20 1.3 Input Buffer Power V VDDQ 1.14 1.20 1.3 I/O Buffer Power V NOTE 1 VDD1 uses significantly less power than VDD2 88 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 8/6/2014 IS43/46LD16640A IS43/46LD32320A Input Leakage Current Parameter/Condition Symbol Min Max Unit Notes IL -2 2 uA 2 IVREF -1 1 uA 1 Input Leakage current For CA, CKE, CS_n, CK_t, CK_c Any input 0V ≤ VIN ≤ VDDCA (All other pins not under test = 0V) VREF supply leakage current VREFDQ = VDDQ/2 or VREFCA = VDDCA/2 (All other pins not under test = 0V) Notes: 1. The minimum limit requirement is for testing purposes. The leakage current on VREFCA and VREFDQ pins should be minimal. 2. Although DM is for input only, the DM leakage shall match the DQ and DQS_t/DQS_c output leakage specification. Operating Temperature Range Parameter/Condition Symbol Standard TOPER Extended Min Max Unit -40 85 oC 85 105 o C Notes: 1. Operating Temperature is the case surface temperature on the center/top side of the LPDDR2 device. For the measurement conditions, please refer to JESD51-2 standard. 2. Some applications require operation of LPDDR2 in the maximum temperature conditons in the Extended Temperature Range between 85°C and 105°C case temperature. For LPDDR2 devices, some derating is neccessary to operate in this range. See MR4 on page 40. 3. Either the device case temperature rating or the temperature sensor (See “Temperature Sensor”) may be used to set an appropriate refresh rate, determine the need for AC timing de-rating and/or monitor the operating temperature. When using the temperature sensor, the actual device case temperature may be higher than the TOPER rating that applies for the Standard or Extended Temperature Ranges. For example, TCASE may be above 85°C when the temperature sensor indicates a temperature of less than 85°C. Thermal Resistance Package Substrate Theta-ja (Airflow= 0m/s) Theta-ja Theta-ja (Airflow=1m/s) (Airflow=2m/s) Theta-jc Units 134-ball BGA 4-layer 33.8 28.1 26.1 4.0 C/W 168-ball PoP BGA 4-layer 26.6 22.0 20.4 3.8 C/W Integrated Silicon Solution, Inc. — www.issi.com 89 Rev. A 8/6/2014 IS43/46LD16640A IS43/46LD32320A AC and DC Input Levels for Single-Ended CA and CS_n Signals Single-Ended AC and DC Input Levels for CA and CS_n Inputs Symbol Parameter LPDDR2-800 to LPDDR2-466 LPDDR2-400 to LPDDR2-200 Max Single-Ended AC and DC Input Levels for CA and CS_n Inputs V (AC) AC input logic high Vref + 0.220 Note IHCA Single-Ended AC and DC Input Levels for CA and CS_n Inputs 2 Min Min Max Unit Notes Vref + 0.300 Note 2 V 1, 2 LPDDR2-800 to LPDDR2-200 Note 2 to LPDDR2-466 Vref - 0.220 LPDDR2-400 Note 2 Vref - 0.300 V 1, 2 VILCA(AC) AC input logic low Symbol Parameter Unit LPDDR2-800 LPDDR2-400 VIHCA (DC) DC input logic high Vref + 0.130 to LPDDR2-466 VDDCA Vref + 0.200 to LPDDR2-200 VDDCA V Notes 1 Max Min Max Min Symbol Parameter Unit Notes VSSCA Vref 0.130 VSSCA Vref 0.200 V 1 VILCA(DC) DC input logic low Max Min Max Min VIHCA(AC) AC input logic high Vref + 0.220 Note 2 Vref + 0.300 Note 2 V 1, 2 (DC) Reference Voltage for CA and 0.49 * VDDCA 0.51 * VDDCA 0.49 * VDDCA 0.51 * VDDCA V 3, 4 V VRefCA (AC) AC AC input input logic logic low high Vref + 0.220 Note 2 Vref + 0.300 Note 2 V 1, IHCA Note 2 Vref - 0.220 Note 2 Vref - 0.300 V 1, 2 2 V ILCA(AC) CS_n inputs (AC) AC input logic low Note 2 Vref - 0.220 Note 2 Vref - 0.300 V 1,12 V VILCA (DC) DC input logic high Vref + 0.130 VDDCA Vref + 0.200 VDDCA V IHCA V (DC) DC DC input input logic logic low high Vref + 0.130 VDDCA Vref + 0.200 VDDCA V 1 Notes: VSSCA Vref - 0.130 VSSCA Vref - 0.200 V 1 VIHCA ILCA(DC) 1. VFor CA and CS_n input only pins. Vref = VrefCA(DC). (DC) DC input logic low VSSCA Vref 0.130 VSSCA Vref 0.200 V 0.49 * VDDCA 0.51 * VDDCA 0.49 * VDDCA 0.51 * VDDCA V 3,14 VILCA RefCA(DC) Reference Voltage for CA and 2. VSee “Overshoot and Undershoot Voltage forSpecifications” CA and 0.49 * VDDCA 0.51 * VDDCA 0.49 * VDDCA 0.51 * VDDCA V 3, 4 CS_n inputs RefCA(DC) Reference 3. The ac peakCS_n noiseinputs on VRefCA may not allow VRefCA to deviate from VRefCA(DC) by more than +/-1% VDDCA (forInput reference: approx. +/- 12 mV). AC and DC Levels for CKE 4. For reference: approx. VDDCA/2 +/- 12 mV. Single-Ended AC and DC Input Levels for CKE Symbol Parameter Min AC and DC Input Levels for CKE VIHCKE Input High for Level 0.8 * VDDCA AC and DCCKE Input Levels CKE CKE Input Low Level Note 1 V Single-Ended AC and DC Input Levels for CKE ILCKE Single-Ended AC and DC Input Levels for CKE Symbol Parameter Min Symbol Parameter Min VIHCKE CKE Input High Level 0.8 * VDDCA Max Note 1 0.2 * VDDCA Max Max Note 1 V High Level * VDDCA 1 AC and DC CKE InputInput Levels Single-Ended0.8 Data Signals CKE Input Low for Level Note 1 0.2 Note * VDDCA VIHCKE ILCKE CKE Input Low Level Note 1 0.2 * VDDCA VILCKE Note: Single-Ended AC and DC InputSpecifications” Levels for DQ and DM 1. See “Overshoot and Undershoot AC and DC Input Levels for Single-Ended Data Signals LPDDR2-800 to LPDDR2-466 Parameter AC Symbol and DC Input Levels for Single-Ended Data Signals Max Min Single-Ended AC and DC Input Levels for DQ and DM VIHDQ(AC) 0.220DM Note 2 ACand input logic high Single-Ended AC DC Input Levels forVref DQ+ and LPDDR2-800 VILDQ(AC) Note 2 to LPDDR2-466 Vref - 0.220 AC input logic low Symbol Parameter LPDDR2-800 to LPDDR2-466 VIHDQ (DC) Vref Min + 0.130 VDDQ DC input logic high Max Symbol Parameter Max Min V (DC) VSSQ Vref - 0.130 DC input logic low VILDQ Vref + 0.220 Note 2 AC input logic high IHDQ(AC) V (AC) Vref + 0.220 Note 2 0.49 * VDDQ 0.51 * VDDQ AC input logic high Reference Voltage for IHDQ RefDQ(DC) VILDQ(AC) Note 2 Vref - 0.220 AC input logic low DQ, DM inputs V (AC) Note 2 Vref 0.220 AC input logic low VILDQ Vref + 0.130 VDDQ DC input logic high IHDQ(DC) V (DC) Vref + 0.130 VDDQ DC input logic high IHDQ VILDQ(DC) VSSQ Vref - 0.130 DC input logic low V (DC) VSSQ Vref - VDDQ 0.130 DC input logic low VILDQ 0.49 * VDDQ 0.51 * Reference Voltage for RefDQ(DC) VRefDQ(DC) 0.49 * VDDQ 0.51 * VDDQ Reference Voltage for DQ, DM inputs DQ, DM inputs Unit Notes V V 1 1 Unit Notes Unit Notes V V V V 1 1 1 1 LPDDR2-400 to LPDDR2-200 Min Max Vref + 0.300 Note 2 LPDDR2-400 to LPDDR2-200 Note 2 Vref - 0.300 LPDDR2-400 to LPDDR2-200 VrefMin + 0.200 VDDQ Max Min VrefVSSQ + 0.300 Vref + VDDQ 0.300 0.49 * Note 2 Max Vref - 0.200 Note 2 Note 2 0.51 * VDDQ Vref - 0.300 0.49VSSQ * VDDQ 0.49 * VDDQ Vref *- VDDQ 0.200 0.51 0.51 * VDDQ Note 2 Vref + 0.200 VrefVSSQ + 0.200 Vref - 0.300 VDDQ VDDQ Vref - 0.200 Unit Notes V V Unit V Unit V V V V V V V V V V V 1, 2, 5 1, 2, 5 Notes 1 Notes 1 5 1, 2, 1, 1,3,2, 2,45 5 1, 2, 1 5 1 1 3,14 3, 4 Notes: 1. For DQ input only pins. Vref = VrefDQ(DC). 2. See “Overshoot and Undershoot Specifications” 3. The ac peak noise on VRefDQ may not allow VRefDQ to deviate from VRefDQ(DC) by more than +/-1% VDDQ (for reference: approx. +/- 12 mV). 4. For reference: approx. VDDQ/2 +/- 12 mV. 90 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 8/6/2014 IS43/46LD16640A IS43/46LD32320A LPDDR2-S4 Refresh Requirement Parameters Parameter Symbol Number of Banks 1Gb Unit 8 Refresh Window Tcase ≤ 85°C tREFW 32 ms Refresh Window 85°C < Tcase ≤ 105°C tREFW 8 ms R 4096 REFab tREFI 7.8 REFpb tREFIpb 0.975 Refresh Cycle time tRFCab 130 ns Per Bank Refresh Cycle time tRFCpb 60 ns Burst Refresh Window = (4 x 8 x tRFCab) tREFBW 4.16 us Required number of REFRESH commands (min) Average time between REFRESH commands (for reference only) Tcase ≤ 85°C" us Integrated Silicon Solution, Inc. — www.issi.com 91 Rev. A 8/6/2014 92 tCK(avg) tCH(avg) tCL(avg) tCK(abs) tCH(abs), allowed tCL(abs), allowed tJIT(per), allowed tJIT(cc), allowed tJIT(duty), allowed tERR(2per), allowed tERR(3per), allowed tERR(4per), allowed tERR(5per), allowed tERR(6per), allowed tERR(7per), allowed Average high pulse width Average low pulse width Absolute Clock Period Absolute clock HIGH pulse width (with allowed jitter) Absolute clock LOW pulse width (with allowed jitter) Clock Period Jitter (with allowed jitter) Maximum Clock Jitter between two consecutive clock cycles (with allowed jitter) Duty cycle Jitter (with allowed jitter) Cumulative error across 2 cycles Cumulative error across 3 cycles Cumulative error across 4 cycles Cumulative error across 5 cycles Cumulative error across 6 cycles Cumulative error across 7 cycles Symbol Average Clock Period Max. Frequency*4 Parameter 400 800 -110 -120 300 360 180 500 250 ps ps -194 194 -209 209 -222 222 -232 232 min max min max min max min max 256 -256 244 -244 230 -230 214 -214 192 279 -279 266 -266 251 -251 233 -233 210 302 -302 288 -288 272 -272 253 -253 227 325 -325 311 -311 293 -293 272 -272 245 -245 175 -227 -175 min max -210 206 191 177 162 147 -192 -206 -191 -177 -162 -147 min max 348 -348 333 -333 314 -314 291 -291 262 -262 221 -221 418 -418 399 -399 377 -377 350 -350 314 581 -581 555 -555 524 -524 486 -486 437 -437 368 265 -314 -368 -265 ps ps ps ps ps ps ps 280 150 ps 260 140 -250 tCK(avg) tCK(avg) tCK(avg) tCK(avg) ps tCK(avg) tCK(avg) ns MHz Unit min((tCH(abs),min - tCH(avg),min), (tCL(abs),min - tCL(avg),min)) * tCK(avg) 240 130 -180 10 100 200 *5 max((tCH(abs),max - tCH(avg),max), (tCL(abs),max - tCL(avg),max)) * tCK(avg) 220 120 -150 7.5 133 266 *5 min 200 110 -140 6 166 333 max max 100 max 0.57 -130 max -100 0.43 min min 0.43 0.57 min max tCK(avg)min + tJIT(per),min 0.45 0.55 min max 5 200 400 min 0 .5 5 max 4.3 233 466 *5 0. 4 5 3.75 266 533 min 3 333 667 LPDDR2 1 00 2.5 Clock Timing min t CK max min ~ min max LPDDR2 AC Timing Table *9 IS43/46LD16640A IS43/46LD32320A AC TIMINGS Integrated Silicon Solution, Inc. — www.issi.com Rev. A 8/6/2014 IS43/46LD16640A IS43/46LD32320A LPDDR2 AC Timing Table *9 Parameter min t CK LPDDR2 Symbol min max Cumulative error across 8 cycles tERR(8per), allowed Cumulative error across 9 cycles tERR(9per), allowed Cumulative error across 10 cycles tERR(10per), allowed Cumulative error across 11 cycles tERR(11per), allowed Cumulative error across 12 cycles tERR(12per), allowed Cumulative error across n = 13, 14 . . . 49, 50 cycles tERR(nper), allowed min tERR(nper),allowed,min = (1 + 0.68ln(n)) * tJIT(per),allowed,min max tERR(nper),allowed,max = (1 + 0.68ln(n)) * tJIT(per),allowed,max 800 667 533 466*5 400 333 266*5 200*5 min -214 -266 -290 -314 -338 -362 -435 -604 max 214 266 290 314 338 362 435 604 min -249 -274 -299 -324 -349 -374 -449 -624 max 249 274 299 324 349 374 449 624 min -257 -282 -308 -334 -359 -385 -462 -641 max 257 282 308 334 359 385 462 641 min -263 -289 -316 -342 -368 -395 -474 -658 max 263 289 316 342 368 395 474 658 min -269 -296 -323 -350 -377 -403 -484 -672 max 269 296 323 350 377 403 484 672 Unit ps ps ps ps ps ps Integrated Silicon Solution, Inc. — www.issi.com 93 Rev. A 8/6/2014 94 max max min tQHS tQSH Data hold skew factor DQS Output High Pulse Width tHZ(DQS) tHZ(DQ) clock*15 clock*15 DQ high-Z from DQS high-Z from DQ low-Z from DQS low-Z from clock tLZ(DQ) tRPST Read postamble*15,*17 tLZ(DQS) tRPRE Read preamble*15,*16 clock*15 min tQH DQ / DQS output hold time from DQS *15 min Data Half Period max max min min min min min tQSL tQHP DQS Output Low Pulse Width DQSCK Delta Long DQS - DQ skew max max tDQSCKDM tDQSQ *20 max tDQSCKDL DQSCK Delta tDQSCKDS Medium*19 DQSCK Delta Short*18 280 240 1200 900 450 *14 540 670 770 466*5 50 90 360 1 340 280 1400 1050 tCK(avg) ps ps ps ps tCL(abs) - 0.05 tDQSCK(MIN) - 300 tDQSCK(MIN) - (1.4 * tQHS(MAX)) tDQSCK(MAX) - 100 tDQSCK(MAX) + (1.4 * tDQSQ(MAX)) ps tQHP - tQHS tCK(avg) tCK(avg) ps ps ps ps tCK(avg) 1000 700 - 2100 ps ps ns ns ns us Unit tCL(abs) - 0.05 750 600 - 2000 1800 200*5 min(tQSH, t QSL) 600 500 - 1900 1350 266*5 tCK(avg) 480 400 2400 1800 1080 333 tCH(abs) - 0.05 450 370 2100 1550 900 400 0.9 400 340 1800 1350 5500 tDQSCK DQS output access time from CK_t/CK_c Read Parameters 3 6 533 2500 min 6 667 LPDDR2 *5 min min tZQRESET Short Calibration Time Calibration Reset Time 800 ZQ Calibration Parameters min t CK max min Long Calibration Time tZQCL min tZQINIT Initialization Calibration Time tZQCS min max Symbol Parameter LPDDR2 AC Timing Table *9 IS43/46LD16640A IS43/46LD32320A Integrated Silicon Solution, Inc. — www.issi.com Rev. A 8/6/2014 Rev. A 8/6/2014 min min tWPRE Write postamble Write preamble min tDSS DQS falling edge to CK setup time min min tDQSL DQS input low-level width tDSH min tDQSH DQS input high-level width tWPST min max tDQSS Write command to 1st DQS latching transition DQS falling edge hold time from CK 0.75 1.25 min tDIPW DQ and DM input pulse width 270 350 430 450 450 0.35 0.4 0.2 0.2 0.4 0.4 0.35 min 430 tDS 350 *14 DQ and DM input setup time (Vref based) 270 Write Parameters 466*5 min 533 tDH 667 DQ and DM input hold time (Vref based) 800 LPDDR2 min max Symbol Parameter min t CK LPDDR2 AC Timing Table *9 480 480 400 600 600 333 750 750 266*5 1000 1000 200*5 tCK(avg) tCK(avg) tCK(avg) tCK(avg) tCK(avg) tCK(avg) tCK(avg) tCK(avg) ps ps Unit IS43/46LD16640A IS43/46LD32320A Integrated Silicon Solution, Inc. — www.issi.com 95 96 min min min tCKE tISCKE*2 tIHCKE*3 CKE min. pulse width (high and low pulse width) CKE input setup time CKE input hold time 800 3 CKE Input Parameters min t CK 667 min min min min min min max max min min tIS tIH*1 tIPW tCKb tISCKEb tIHCKEb tISb tIHb tDQSCKb tDQSQb tQHSb tMRW tMRR Address and control input setup time (Vref based) Address and control input hold time (Vref based) Address and control input pulse width Clock Cycle Time CKE Input Setup Time CKE Input Hold Time Address & Control Input Setup Time Address & Control Input Hold Time DQS Output Data Access Time from CK_t/CK_c Data Strobe Edge to Ouput Data Edge tDQSQb - 1.2 Data Hold Skew Factor MODE REGISTER Write command period Mode Register Read command period 290 290 460 370 max min min max 2 5 Mode Register Parameters - - - - - - - - *8,10,11 460 *14 533 370 Boot Parameters (10 MHz - 55 MHz) min *1 Command Address Input Parameters min max Symbol Parameter LPDDR2 AC Timing Table *9 520 520 466 *5 2 5 1.2 1.2 10.0 2.0 1150 1150 2.5 2.5 18 100 0.40 0.25 0.25 3 LPDDR2 740 740 600 333 600 400 900 900 266 *5 1150 1150 200 *5 tCK(avg) tCK(avg) ns ns ns ps ps ns ns ns tCK(avg) ps ps tCK(avg) tCK(avg) tCK(avg) Unit IS43/46LD16640A IS43/46LD32320A Integrated Silicon Solution, Inc. — www.issi.com Rev. A 8/6/2014 Rev. A 8/6/2014 2 3 min min min min min min min Fast min min min min RL WL tRC tCKESR tXSR tXP tCCD tRTP tRCD tRPpb tRPab 4-bank tRPab 8-bank tRAS tWR tWTR tRRD tFAW tDPD Write Latency ACTIVE to ACTIVE command period CKE min. pulse width during Self-Refresh (low pulse width during Self-Refresh) Self refresh exit to next valid command delay Exit power down to next valid command delay LPDDR2-S4 CAS to CAS delay Internal Read to Precharge command delay RAS to CAS Delay Row Precharge Time (single bank) Row Precharge Time (all banks) Row Precharge Time (all banks) Row Active Time Write Recovery Time Internal Write to Read Command Delay Active bank A to Active bank B Four Bank Activate Window Minimum Deep Power Down Time 800 8 2 2 3 - min max Typ 3 3 Fast 3 3 Slow min 3 Typ Slow 3 3 Fast 3 3 Typ 3 Fast Slow 3 3 Typ 2 2 2 3 1 3 Slow min 3 6 LPDDR2 SDRAM Core Parameters Read Latency min t CK Symbol Parameter min max LPDDR2 AC Timing Table *9 500 50 10 7.5 15 70 42 27 21 18 24 18 15 24 18 15 24 18 15 7.5 2 7.5 15 2 5 *12 667 466 *5 2 4 400 tRFCab + 10 50 ns ns ns ns ns ns ns tCK(avg) ns ns ns ns tCK(avg) tCK(avg) Unit 500 10 10 15 70 42 27 us ns ns ns ns us ns ns ns 21 ns ns 18 24 ns 200 *5 ns 266 *5 18 60 1 3 333 15 24 18 15 24 18 15 7.5 2 7.5 15 tRAS + tRPab (with all-bank Precharge) tRAS + tRPpb (with per-bank Precharge) 2 4 533 LPDDR2 IS43/46LD16640A IS43/46LD32320A Integrated Silicon Solution, Inc. — www.issi.com 97 IS43/46LD16640A IS43/46LD32320A Notes: 1. Frequency values are for reference only. Clock cycle time (tCK) is used to determine device capabilities. 2. All AC timings assume an input slew rate of 1 V/ns. 3. READ, WRITE, and input setup and hold values are referenced to VREF. 4. tDQSCKDS is the absolute value of the difference between any two tDQSCK measurements (in a byte lane) within a contiguous sequence of bursts in a 160ns rolling window. tDQSCKDS is not tested and is guaranteed by design. Temperature drift in the system is < 10°C/s. Values do not include clock jitter. 5. tDQSCKDM is the absolute value of the difference between any two tDQSCK measurements (in a byte lane) within a 1.6μs rolling window. tDQSCKDM is not tested and is guaranteed by design. Temperature drift in the system is < 10 °C/s. Values do not include clock jitter. 6. tDQSCKDL is the absolute value of the difference between any two tDQSCK measurements (in a byte lane) within a 32ms rolling window. tDQSCKDL is not tested and is guaranteed by design. Temperature drift in the system is < 10 °C/s. Values do not include clock jitter. 7. For LOW-to-HIGH and HIGH-to-LOW transitions, the timing reference is at the point when the signal crosses the transition threshold (VTT). tHZ and tLZ transitions occur in the same access time (with respect to clock) as valid data transitions. These parameters are not referenced to a specific voltage level but to the time when the device output is no longer driving (for tRPST, tHZ(DQS) and tHZ(DQ)), or begins driving (for tRPRE, tLZ(DQS), tLZ(DQ)). Figure shows a method to calculate the point when device is no longer driving tHZ(DQS) and tHZ(DQ), or begins driving tLZ(DQS), tLZ(DQ) by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the calculation is consistent. The parameters tLZ(DQS), tLZ(DQ), tHZ(DQS), and tHZ(DQ) are defined as single-ended. The timing parameters tRPRE and tRPST are determined from the differential signal DQS, /DQS. Output Transition Timing V OH 2x X V TT + 2 x Y mV a ct u a l w a ve t HZ(DQS), t HZ(DQ) fo V TT rm V TT - Y mV V OH - X mV V OH - 2x X mV t LZ(DQS), t LZ(DQ) V TT + Y mV X Y 2x Y V OL + 2x X mV V TT - 2 x Y mV T1 T2 Start driving point = 2 × T1 - T2 V TT V OL + X mV V OL T1 T2 End driving point = 2 × T1 - T2 8. Measured from the point when DQS, /DQS begins driving the signal to the point when DQS, /DQS begins driving the first rising strobe edge. 9. Measured from the last falling strobe edge of DQS, /DQS to the point when DQS, /DQS finishes driving the signal. 10. CKE input setup time is measured from CKE reaching a HIGH/LOW voltage level to CK, /CK crossing. 11. CKE input hold time is measured from CK, /CK crossing to CKE reaching a HIGH/LOW voltage level. 12. Input set-up/hold time for signal (CA[9:0], /CS). 13. To ensure device operation before the device is configured, a number of AC boot-timing parameters are defined in this table. Boot parameter symbols have the letter b appended (for example, tCK during boot is tCKb). 14. The LPDDR device will set some mode register default values upon receiving a RESET (MRW) command as specified in ― Mode Register Definition‖. 15. The output skew parameters are measured with default output impedance settings using the reference load. 16. The minimum tCK column applies only when tCK is greater than 6ns. 17. Timing derating applies for operation at 85°C to 105°C when the requirement to derate is indicated by mode register 4 opcode. 98 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 8/6/2014 IS43/46LD16640A IS43/46LD32320A 18. tDQSCKDS is the absolute value of the difference between any two tDQSCK measurements (within a byte lane) within a contiguous sequence of bursts within a 160ns rolling window. tDQSCKDS is not tested and is guaranteed by design. Temperature drift in the system is 2.0 75 – 175 – 2.0 57 – 170 – 1.5 50 – 167 – 1.0 38 – 163 – 0.9 34 – 162 – 0.8 29 – 161 – 0.7 22 – 159 – 0.6 13 – 155 – 0.5 0 – 150 – 4.0 175 75 4.0 170 57 3.0 167 50 2.0 163 38 1.8 162 34 1.6 161 29 1.4 159 22 1.2 155 13 1.0 150 0 < 1.0 150 0 = Single-Ended Requirements for Differential Signals Each individual component of a differential signal (CK, CK#, DQS, and DQS#) must also comply with certain requirements for single-ended signals. CK and CK# must meet VSEH(AC)min/VSEL(AC)max in every half cycle. DQS, DQS# must meet VSEH(AC)min/VSEL(AC)max in every half cycle preceding and following a valid transition. The applicable AC levels for CA and DQ differ by speed bin. 122 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 8/6/2014 IS43/46LD16640A IS43/46LD32320A Single-Ended Requirements for Differential Signals V DDCA or V DDQ V SEH(AC) Differential Voltage V SEH(AC)min V DDCA /2 or V DDQ /2 CK or DQS V SEL(AC)max V SEL(AC) V SSCA or V SSQ Time Note that while CA and DQ signal requirements are referenced to VREF, the single-ended components of differential signals also have a requirement with respect to VDDQ/2 for DQS, and VDDCA/2 for CK. The transition of single-ended signals through the AC levels is used to measure setup time. For single-ended components of differential signals, the requirement to reach VSEL(AC)max or VSEH(AC)min has no bearing on timing. This requirement does, however, add a restriction on the common mode characteristics of these signals. Single-Ended Levels for CK, CK#, DQS, DQS# LPDDR2-800 to LPDDR2-466 Symbol V SEH(AC) V SEL(AC) Parameter LPDDR2-400 to LPDDR2-200 Min Max Min Max Unit Notes Single-ended HIGH level for strobes (V DDQ /2) + 0.220 Note 1 (V DDQ /2) + 0.300 Note 1 V 2, 3 Single-ended HIGH level for CK, CK# (V DDCA /2) + 0.220 Note 1 (V DDCA /2) + 0.300 Note 1 V 2, 3 Single-ended LOW level for strobes Note 1 (V DDQ /2) - 0.220 Note 1 (V DDQ /2) + 0.300 V 2, 3 Single-ended LOW level for CK, CK# Note 1 (V DDCA /2) - 0.220 Note 1 (V DDCA /2) + 0.300 V 2, 3 Notes: 1. These values are not defined, however the single-ended signals CK, CK#, DQS, and DQS# must be within the respective limits (VIH(DC)max, VIL(DC)min) for single-ended signals and must comply with the specified limitations for overshoot and undershoot. 2. For CK and CK#, use VIH/VIL(AC) of CA and VREFCA; for DQS and DQS#, use VIH/VIL(AC) of DQ and VREFDQ. If a reduced AC HIGH or AC LOW is used for a signal group, the reduced voltage level also applies. 3. Used to define a differential signal slew rate. Integrated Silicon Solution, Inc. — www.issi.com 123 Rev. A 8/6/2014 IS43/46LD16640A IS43/46LD32320A Differential Input Crosspoint Voltage To ensure tight setup and hold times as well as output skew parameters with respect to clock and strobe, each crosspoint voltage of differential input signals (CK, CK#, DQS, and DQS#) must meet the specifications in the table "Single-Ended Levels" (page 124). The differential input crosspoint voltage (VIX) is measured from the actual crosspoint of the true signal and complement to the midlevel between VDD and VSS. VIX Definition V DDCA , V DDQ V DDCA , V DDQ CK#, DQS# CK#, DQS# X V IX V IX V DDCA /2, V DDQ /2 X V DDCA /2, X V DDQ /2 V IX X V IX CK, DQS CK, DQS V SSCA , V SSQ V SSCA , V SSQ Crosspoint Voltage for Differential Input Signals (CK, CK#, DQS, DQS#) LPDDR2-800 to LPDDR2-200 Symbol Parameter Min Max Unit Notes V IXCA(AC) Differential input crosspoint voltage relative to V DDCA /2 for CK and CK# –120 120 mV 1, 2 V IXDQ(AC) Differential input crosspoint voltage relative to V DDQ /2 for DQS and DQ# –120 120 mV 1, 2 Notes: 1. The typical value of VIX(AC) is expected to be about 0.5 × VDD of the transmitting device, and it is expected to track variations in VDD. VIX(AC) indicates the voltage at which differential input signals must cross. 2. For CK and CK#, VREF = VREFCA(DC). For DQS and DQS#, VREF = VREFDQ(DC). 124 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 8/6/2014 IS43/46LD16640A IS43/46LD32320A Input Slew Rate Differential Input Slew Rate Definition Measured Description 1 From To Defined by Differential input slew rate for rising edge (CK/CK# and DQS/DQS#) V IL,diff,max V IH,diff,min [V IH,diff,min - V IL,diff,max ] / ˂TR diff Differential input slew rate for falling edge (CK/CK# and DQS/DQS#) V IH,diff,min V IL,diff,max [V IH,diff,min - V IL,diff,max ] / ˂TF diff Note: The differential signals (CK/CK# and DQS/DQS#) must be linear between these thresholds. Differential Input Slew Rate Definition for CK, CK#, DQS, and DQS# ΔTR diff Differential Input Voltage ΔTF diff V IH,di ff,min 0 V IL,di ff,max Time Output Characteristics and Operating Conditions Single-Ended AC and DC Output Levels Symbol Parameter Value Unit Notes V OH(AC) AC output HIGH measurement level (for output slew rate) V REF + 0.12 V V OL(AC) AC output LOW measurement level (for output slew rate) V REF - 0.12 V V OH(DC) DC output HIGH measurement level (for I-V curve linearity) 0.9 x V DDQ V 1 V OL(DC) DC output LOW measurement level (for I-V curve linearity) 0.1 x V DDQ V 2 I OZ MMpupd Output leakage current (DQ, DM, DQS, DQS#); DQ, DQS, DQS# are disabled; 0V ื V OUT ื V DDQ MIN –5 ˩A MAX +5 ˩A Delta output impedance between pull-up and pulldown for DQ/DM MIN –15 % MAX +15 % Notes: 1. IOH = –0.1mA. 2. IOL = 0.1mA. Integrated Silicon Solution, Inc. — www.issi.com 125 Rev. A 8/6/2014 IS43/46LD16640A IS43/46LD32320A Differential AC and DC Output Levels Symbol Parameter Value Unit V OHdiff(AC) AC differential output HIGH measurement level (for output SR) + 0.2 x V DDQ V V OLdiff(AC) AC differential output LOW measurement level (for output SR) - 0.2 x V DDQ V Single-Ended Output Slew Rate With the reference load for timing measurements, the output slew rate for falling and rising edges is defined and measured between VOL(AC) and VOH(AC) for single-ended signals. Differential Input Slew Rate Definition Measured Description From To Defined by Single-ended output slew rate for rising edge V OL(AC) V OH(AC) [V OH(AC) - V OL(AC) ] / ˂TR SE Single-ended output slew rate for falling edge V OH(AC) V OL(AC) [V OH(AC) - V OL(AC) ] / ˂TF SE Note: Output slew rate is verified by design and characterization and may not be subject to production testing. Single-Ended Output Slew Rate Definition Single-Ended Output Voltage (DQ) ΔTF SE 126 ΔTR SE V OH(AC) V REF V OL(AC) Time Integrated Silicon Solution, Inc. — www.issi.com Rev. A 8/6/2014 IS43/46LD16640A IS43/46LD32320A Single-Ended Output Slew Rate Value Parameter Symbol Min Max Unit Single-ended output slew rate (output impedance = 40 ˖±30%) SRQ SE 1.5 3.5 V/ns Single-ended output slew rate (output impedance = 60 ˖±30%) SRQ SE 1.0 2.5 V/ns 0.7 1.4 – Output slew-rate-matching ratio (pull-up to pull-down) Notes: 1. Definitions: SR = slew rate; Q = output (similar to DQ = data-in, data-out); SE = singleended signals 2. Measured with output reference load. 3. The ratio of pull-up to pull-down slew rate is specified for the same temperature and voltage over the entire temperature and voltage range. For a given output, the ratio represents the maximum difference between pull-up and pull-down drivers due to process variation. 4. The output slew rate for falling and rising edges is defined and measured between VOL(AC) and VOH(AC). 5. Slew rates are measured under typical simultaneous switching output (SSO) conditions, with one-half of DQ signals per data byte driving HIGH and one-half of DQ signals per data byte driving LOW. Differential Output Slew Rate With the reference load for timing measurements, the output slew rate for falling and rising edges is defined and measured between VOL,diff(AC) and VOH,diff(AC) for differential signals. Differential Output Slew Rate Definition Value Parameter Differential output slew rate (output impedance = 40 ˖±30%) Symbol Min Max Unit SRQ diff 3.0 7.0 V/ns Note: Output slew rate is verified by design and characterization and may not be subject to production testing. Differential Output Slew Rate Definition Differential Output Voltage (DQS, DQS#) ΔTF diff ΔTR diff V OH,di ff(AC) 0 V OL,di ff(AC) Time Integrated Silicon Solution, Inc. — www.issi.com 127 Rev. A 8/6/2014 IS43/46LD16640A IS43/46LD32320A Value Parameter Symbol Min Value Max Unit Parameter Differential output slew rate (output impedance = 40 ˖±30%) Symbol SRQ diff Min 3.0 Max 7.0 Unit V/ns Differential output slew rate (output impedance = 60 ˖±30%) SRQ diff 2.0 5.0 V/ns Notes: 1. Definitions: SR = slew rate; Q = output (similar to DQ = data-in, data-out); SE = singleended signals. 2. Measured with output reference load. 3. The output slew rate for falling and rising edges is defined and measured between VOL(AC) and VOH(AC). 4. Slew rates are measured under typical simultaneous switching output (SSO) conditions, with one-half of DQ signals per data byte driving HIGH and one-half of DQ signals per data byte driving LOW. 128 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 8/6/2014 IS43/46LD16640A IS43/46LD32320A AC Overshoot/Undershoot Specification Applies for CA[9:0], CS#, CKE, CK, CK#, DQ, DQS, DQS#, DM Parameter 800 667 533 400 333 Unit Maximum peak amplitude provided for overshoot area 0.35 0.35 0.35 0.35 0.35 V Maximum peak amplitude provided for undershoot area 0.35 0.35 0.35 0.35 0.35 V Maximum area above VDD 1 0.20 0.24 0.30 0.40 0.48 V/ns Maximum area below VSS2 0.20 0.24 0.30 0.40 0.48 V/ns Notes: 1. VDD stands for VDDCA for CA[9:0], CK, CK#, CS#, and CKE. VDD stands for VDDQ for DQ, DM, DQS, and DQS#. 2. VSS stands for VSSCA for CA[9:0], CK, CK#, CS#, and CKE. VSS stands for VSSQ for DQ, DM, DQS, and DQS#. Overshoot and Undershoot Definition Volts (V) Maximum amplitude V DD Overshoot area Time (ns) V SS Maximum amplitude Undershoot area Notes: 1. VDD stands for VDDCA for CA[9:0], CK, CK#, CS#, and CKE. VDD stands for VDDQ for DQ, DM, DQS, and DQS#. 2. VSS stands for VSSCA for CA[9:0], CK, CK#, CS#, and CKE. VSS stands for VSSQ for DQ, DM, DQS, and DQS#. HSUL_12 Driver Output Timing Reference Load The timing reference loads are not intended as a precise representation of any particular system environment or a depiction of the actual load presented by a production tester. System designers should use IBIS or other simulation tools to correlate the timing reference load to a system environment. Manufacturers correlate to their production test conditions, generally with one or more coaxial transmission lines terminated at the tester electronics. Integrated Silicon Solution, Inc. — www.issi.com 129 Rev. A 8/6/2014 IS43/46LD16640A IS43/46LD32320A HSUL_12 Driver Output Reference Load for Timing and Slew Rate LPDDR2 V REF 0.5 × V DDQ 50Ω Output V TT = 0.5 × V DDQ C LOAD = 5pF Note: All output timing parameter values (tDQSCK, tDQSQ, tQHS, tHZ, tRPRE etc.) are reported with respect to this reference load. This reference load is also used to report slew rate. Output Driver Impedance The output driver impedance is selected by a mode register during initialization. The selected value is able to maintain the tight tolerances specified if proper ZQ calibration is performed. Output specifications refer to the default output driver unless specifically stated otherwise. A functional representation of the output buffer is shown in bellow. The output driver impedance RON is defined by the value of the external reference resistor RZQ as follows: RONPU = (VDDQ – VOUT) / ABS(IOUT) When RONPD is turned off. RONPD = VOUT / ABS(IOUT) When RONPU is turned off. Output Driver Chip in drive mode Chip in Drive Mode Output Driver V DDQ To other circuitry (RCV, etc.) I PU R ONPU R ONPD I PD 130 I OUT DQ V OUT V SSQ Integrated Silicon Solution, Inc. — www.issi.com Rev. A 8/6/2014 IS43/46LD16640A IS43/46LD32320A Output Driver Impedance Characteristics with ZQ Calibration Output driver impedance is defined by the value of the external reference resistor RZQ. Typical RZQ is 240 ohms. Output Driver DC Electrical Characteristics with ZQ Calibration R ONnom 34.3˖ 40.0˖ 48.0˖ 60.0˖ 80.0˖ 120.0˖ Mismatch between pull-up and pull-down Resistor V OUT Min Typ Max Unit R ON34PD 0.5 × V DDQ 0.85 1.00 1.15 R ZQ /7 R ON34PU 0.5 × V DDQ 0.85 1.00 1.15 R ZQ /7 R ON40PD 0.5 × V DDQ 0.85 1.00 1.15 R ZQ /6 R ON40PU 0.5 × V DDQ 0.85 1.00 1.15 R ZQ /6 R ON48PD 0.5 × V DDQ 0.85 1.00 1.15 R ZQ /5 R ON48PU 0.5 × V DDQ 0.85 1.00 1.15 R ZQ /5 R ON60PD 0.5 × V DDQ 0.85 1.00 1.15 R ZQ /4 R ON60PU 0.5 × V DDQ 0.85 1.00 1.15 R ZQ /4 R ON80PD 0.5 × V DDQ 0.85 1.00 1.15 R ZQ /3 R ON80PU 0.5 × V DDQ 0.85 1.00 1.15 R ZQ /3 R ON120PD 0.5 × V DDQ 0.85 1.00 1.15 R ZQ /2 R ON120PU 0.5 × V DDQ 0.85 1.00 1.15 R ZQ /2 +15.00 % MM PUPD –15.00 Notes 5 Notes: 1. Applies across entire operating temperature range after calibration. 2. RZQ = 240Ω. 3. The tolerance limits are specified after calibration, with fixed voltage and temperature. For behavior of the tolerance limits if temperature or voltage changes after calibration. 4. Pull-down and pull-up output driver impedances should be calibrated at 0.5 x VDDQ. 5. Measurement definition for mismatch between pull-up and pull-down, MMPUPD: Measure RONPU and RONPD, both at 0.5 × VDDQ: MMPUPD =( ( RONPU – RONPD ) / RON,nom ) × 100 For example, with MMPUPD (MAX) = 15% and RONPD = 0.85, RONPU must be less than 1.0. Integrated Silicon Solution, Inc. — www.issi.com 131 Rev. A 8/6/2014 IS43/46LD16640A IS43/46LD32320A Output Driver Temperature and Voltage Sensitivity If temperature and/or voltage change after calibration, the tolerance limits widen Output Driver Sensitivity Definition Symbol Parameter Min Max Unit R ONPD R ON temperature sensitivity 0.00 0.75 %/˚C R ONPU R ON voltage sensitivity 0.00 0.20 %/mV Notes: 1. ΔT = T - T (at calibration). ΔV = V - V (at calibration). 2. dRONdT and dRONdV are not subject to production testing; they are verified by design and characterization. Output Driver Temperature and Voltage Sensitivity Symbol Parameter Min Max Unit R ONPD R ON temperature sensitivity 0.00 0.75 %/˚C R ONPU R ON voltage sensitivity 0.00 0.20 %/mV Output Impedance Characteristics Without ZQ Calibration Output driver impedance is defined by design and characterization as the default setting. Output Driver DC Electrical Characteristics Without ZQ Calibration RON nom 34.3˖ 40.0˖ 48.0˖ 60.0˖ 80.0˖ 120.0˖ Resistor V OUT Min Typ Max Unit R ON34PD 0.5 × V DDQ 0.70 1.00 1.30 R ZQ /7 R ON34PU 0.5 × V DDQ 0.70 1.00 1.30 R ZQ /7 R ON40PD 0.5 × V DDQ 0.70 1.00 1.30 R ZQ /6 R ON40PU 0.5 × V DDQ 0.70 1.00 1.30 R ZQ /6 R ON48PD 0.5 × V DDQ 0.70 1.00 1.30 R ZQ /5 R ON48PU 0.5 × V DDQ 0.70 1.00 1.30 R ZQ /5 R ON60PD 0.5 × V DDQ 0.70 1.00 1.30 R ZQ /4 R ON60PU 0.5 × V DDQ 0.70 1.00 1.30 R ZQ /4 R ON80PD 0.5 × V DDQ 0.70 1.00 1.30 R ZQ /3 R ON80PU 0.5 × V DDQ 0.70 1.00 1.30 R ZQ /3 R ON120PD 0.5 × V DDQ 0.70 1.00 1.30 R ZQ /2 R ON120PU 0.5 × V DDQ 0.70 1.00 1.30 R ZQ /2 Notes: 1. Applies across entire operating temperature range, without calibration. 2. RZQ = 240Ω 132 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 8/6/2014 IS43/46LD16640A IS43/46LD32320A I-V Curves R ON = 240˖(R ZQ ) Pull-Down Current (mA) / R Default Value after ZQRESET Voltage (V) Min (mA) Max (mA) Pull-Up ON (ohms) Current (mA) / R With Calibration Min (mA) Max (mA) Default Value after ZQRESET Min (mA) Max (mA) ON (ohms) With Calibration Min (mA) Max (mA) 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.05 0.19 0.32 0.21 0.26 –0.19 –0.32 –0.21 –0.26 0.10 0.38 0.64 0.40 0.53 –0.38 –0.64 –0.40 –0.53 0.15 0.56 0.94 0.60 0.78 –0.56 –0.94 –0.60 –0.78 0.20 0.74 1.26 0.79 1.04 –0.74 –1.26 –0.79 –1.04 0.25 0.92 1.57 0.98 1.29 –0.92 –1.57 –0.98 –1.29 0.30 1.08 1.86 1.17 1.53 –1.08 –1.86 –1.17 –1.53 0.35 1.25 2.17 1.35 1.79 –1.25 –2.17 –1.35 –1.79 0.40 1.40 2.46 1.52 2.03 –1.40 –2.46 –1.52 –2.03 0.45 1.54 2.74 1.69 2.26 –1.54 –2.74 –1.69 –2.26 0.50 1.68 3.02 1.86 2.49 –1.68 –3.02 –1.86 –2.49 0.55 1.81 3.30 2.02 2.72 –1.81 –3.30 –2.02 –2.72 0.60 1.92 3.57 2.17 2.94 –1.92 –3.57 –2.17 –2.94 0.65 2.02 3.83 2.32 3.15 –2.02 –3.83 –2.32 –3.15 0.70 2.11 4.08 2.46 3.36 –2.11 –4.08 –2.46 –3.36 0.75 2.19 4.31 2.58 3.55 –2.19 –4.31 –2.58 –3.55 0.80 2.25 4.54 2.70 3.74 –2.25 –4.54 –2.70 –3.74 0.85 2.30 4.74 2.81 3.91 –2.30 –4.74 –2.81 –3.91 0.90 2.34 4.92 2.89 4.05 –2.34 –4.92 –2.89 –4.05 0.95 2.37 5.08 2.97 4.23 –2.37 –5.08 –2.97 –4.23 1.00 2.41 5.20 3.04 4.33 –2.41 –5.20 –3.04 –4.33 1.05 2.43 5.31 3.09 4.44 –2.43 –5.31 –3.09 –4.44 1.10 2.46 5.41 3.14 4.52 –2.46 –5.41 –3.14 –4.52 1.15 2.48 5.48 3.19 4.59 –2.48 –5.48 –3.19 –4.59 1.20 2.50 5.55 3.23 4.65 –2.50 –5.55 –3.23 –4.65 Integrated Silicon Solution, Inc. — www.issi.com 133 Rev. A 8/6/2014 IS43/46LD16640A IS43/46LD32320A Output Impedance = 240 Ohms, I-V Curves After ZQRESET 6 PD (MAX) PD (MIN) PU MAX) 4 PU (MIN) mA 2 0 –2 –4 –6 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 Voltage 134 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 8/6/2014 IS43/46LD16640A IS43/46LD32320A Output Impedance = 240 Ohms, I-V Curves After Calibration 6 PD (MAX) PD (MIN) PU MAX) 4 PU (MIN) mA 2 0 –2 –4 –6 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 Voltage Integrated Silicon Solution, Inc. — www.issi.com 135 Rev. A 8/6/2014 IS43/46LD16640A IS43/46LD32320A Clock Specification The specified clock jitter is a random jitter with Gaussian distribution. Input clocks violating minimum or maximum values may result in device malfunction. Definitions and Calculations Symbol Description t CK(avg) and The average clock period across any consecutive 200-cycle window. Each clock period is calculated from rising clock edge to rising clock edge. nCK Calculation Notes N Σ t CK j /N t CK(avg) = j=1 Where N = 200 Unit t CK(avg) represents the actual clock average t CK(avg)of the input clock under operation. Unit nCK represents one clock cycle of the input clock, counting from actual clock edge to actual clock edge. t CK(avg)can change no more than ±1% within a 100-clock-cycle window, provided that all jitter and timing specifications are met. t CK(abs) The absolute clock period, as measured from one rising clock edge to the next consecutive rising clock edge. t CH(avg) The average HIGH pulse width, as calculated across any 200 consecutive HIGH pulses. 1 N t CH(avg) = Σ t CH j=1 j / ( N × t CK(avg)) Where N = 200 t CL(avg) The average LOW pulse width, as calculated across any 200 consecutive LOW pulses. N t CL(avg) = Σ t CL j=1 j /(N × t CK(avg)) Where N = 200 t JIT(per) The single-period jitter defined as the largest deviation of any signal t CK from t CK(avg). t JIT(per),act The actual clock jitter for a given system. t JIT(per), The specified clock period jitter allowance. t JIT(per) = min/max of t CK – t CK(avg) i Where i = 1 to 200 1 allowed t JIT(cc) t ERR(nper) The absolute difference in clock periods between two consecutive clock cycles. t JIT(cc) defines the cycle-to-cycle jitter. The cumulative error across tive cycles from t CK(avg). t JIT(cc) = max of n multiple consecu- t CK 1 – t CK i i+1 i+n–1 t ERR(nper) = Σ t CK j – ( n × t CK(avg)) 1 j=i t ERR(nper),act The actual cumulative error over given system. t ERR(nper), allowed The specified cumulative error allowance over cycles. t ERR(nper),min The minimum 136 t ERR(nper). n cycles for a n t ERR(nper),min = (1 + 0.68LN(n)) × t JIT(per),min 2 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 8/6/2014 IS43/46LD16640A IS43/46LD32320A Symbol Description Calculation t ERR(nper),max t ERR(nper). The maximum t JIT(duty) Defined with absolute and average specifications for t CH and t CL, respectively. Notes t ERR(nper),max = (1 + 0.68LN(n)) × 2 t JIT(per),max t JIT(duty),min = MIN( ( t CH(abs),min – t CH(avg),min), ( t CL(abs),min – t CL(avg),min)) × t CK(avg) t JIT(duty),max = MAX(( t CH(abs),max – t CH(avg),max), ( t CL(abs),max – t CL(avg),max)) × t CK(avg) Notes: 1. Not subject to production testing. 2. Using these equations, tERR(nper) tables can be generated for each tJIT(per),act value. tCK(abs), tCH(abs), and tCL(abs) These parameters are specified with their average values; however, the relationship between the average timing and the absolute instantaneous timing (defined in the following table) is applicable at all times. tCK(abs), tCH(abs), and tCL(abs) Definitions Parameter Symbol Absolute clock period t CK(abs) t CK(avg),min + Minimum Absolute clock HIGH pulse width t CH(abs) t CH(avg),min + t JIT(duty),min 2 /t CK(avg)min t CK(avg) Absolute clock LOW pulse width t CL(abs) t CL(avg),min + t JIT(duty),min 2 /t CK(avg)min t CK(avg) t JIT(per),min Unit ps 1 Notes: 1. tCK(avg),min is expressed in ps for this table. 2. tJIT(duty),min is a negative value Integrated Silicon Solution, Inc. — www.issi.com 137 Rev. A 8/6/2014 IS43/46LD16640A IS43/46LD32320A Clock Period Jitter LPDDR2 devices can tolerate some clock period jitter without core timing parameter derating. This section describes device timing requirements with clock period jitter (tJIT(per)) in excess of the values found in the AC Timing section. Calculating cycle time derating and clock cycle derating are also described. Clock Period Jitter Effects on Core Timing Parameters Core timing parameters (tRCD, tRP, tRTP, tWR, tWRA, tWTR, tRC, tRAS, tRRD, tFAW) extend across multiple clock cycles. Clock period jitter impacts these parameters when measured in numbers of clock cycles. Within the specification limits, the device is characterized and verified to support tnPARAM = RU[tPARAM/tCK(avg)]. During device operation where clock jitter is outside specification limits, the number of clocks or tCK(avg), may need to be increased based on the values for each core timing parameter. Cycle Time Derating for Core Timing Parameters For a given number of clocks (tnPARAM), when tCK(avg) and tERR(tnPARAM) exceed tERR(tnPARAM),allowed, cycle time derating may be required for core timing parameters. tPARAM + tERR( tnPARAM),act – tERR( tnPARAM),allowed – tCK(avg) , 0 tnPARAM CycleTimeDerating = max Conduct cycle time derating analysis for each core timing parameter. The amount of cycle time derating required is the maximum of the cycle time deratings determined for each individual core timing parameter. Clock Cycle Derating for Core Timing Parameters For each core timing parameter and a given number of clocks (tnPARAM), clock cycle derating should be specified with tJIT(per). For a given number of clocks (tnPARAM), when tCK(avg) and (tERR(tnPARAM),act) exceed the supported cumulative tERR(tnPARAM),allowed, if the equation below results in a positive value for a core timing parameter (tCORE), the required clock cycle derating (in clocks) will be that positive value. ClockCycleDerating = RU tPARAM + tERR( tnPARAM),act – tERR( tnPARAM),allowed tCK(avg) – tnPARAM Conduct cycle-time derating analysis for each core timing parameter. 138 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 8/6/2014 IS43/46LD16640A IS43/46LD32320A Clock Jitter Effects on Command/Address Timing Parameters Command/address timing parameters (tIS, tIH, tISCKE, tIHCKE, tISb, tIHb, tISCKEb, tIHCKEb) are measured from a command/address signal (CKE, CS, or CA[9:0]) transition edge to its respective clock signal (CK/CK#) crossing. The specification values are not affected by the tJIT(per) applied, as the setup and hold times are relative to the clock signal crossing that latches the command/address. Regardless of clock jitter values, these values must be met. Clock Jitter Effects on READ Timing Parameters tRPRE When the device is operated with input clock jitter, tRPRE must be derated by the tJIT(per),act,max of the input clock that exceeds tJIT(per),allowed,max. Output deratings are relative to the input clock. tRPRE(min,derated) = 0.9 – tJIT(per),act,max – tJIT(per),allowed,max tCK(avg) For example, if the measured jitter into a LPDDR2-800 device has tCK(avg) = 2500ps, tJIT(per),act,min = –172ps, and JIT(per),act,max = +193ps, then tRPRE,min, derated = 0.9 (tJIT(per), act,max - tJIT(per), allowed,max)/tCK(avg) = 0.9 - (193 - 100)/2500 = 0.8628 tCK(avg). tLZ(DQ), tHZ(DQ), tDQSCK, tLZ(DQS), tHZ(DQS) These parameters are measured from a specific clock edge to a data signal transition (DMn or DQm, where: n = 0, 1, 2, or 3; and m = DQ[31:0]), and specified timings must be met with respect to that clock edge. Therefore, they are not affected by tJIT(per). tQSH, tQSL These parameters are affected by duty cycle jitter, represented by tCH(abs)min and tCL(abs)min. Therefore tQSH(abs)min and tQSL(abs)min can be specified with tCH(abs)min and tCL(abs)min. tQSH(abs)min = tCH(abs)min - 0.05 tQSL(abs)min = tCL(abs)min - 0.05. These parameters determine the absolute data-valid window at the device pin. The absolute minimum data-valid window at the device pin = min [(tQSH(abs)min × tCK(avg)min - tDQSQmax - tQHSmax), (tQSL(abs)min × tCK(avg)min - tDQSQmax - tQHSmax)]. This minimum data-valid window must be met at the target frequency regardless of clock jitter. Integrated Silicon Solution, Inc. — www.issi.com 139 Rev. A 8/6/2014 IS43/46LD16640A IS43/46LD32320A tRPST tRPST is affected by duty cycle jitter, represented by tCL(abs). Therefore, tRPST(abs)min can be specified by tCL(abs)min. tRPST(abs)min = tCL(abs)min - 0.05 = tQSL(abs)min. Clock Jitter Effects on WRITE Timing Parameters tDS, tDH These parameters are measured from a data signal (DMn or DQm, where n = 0, 1, 2, 3; and m = DQ[31:0]) transition edge to its respective data strobe signal (DQSn, DQSn#: n = 0,1,2,3) crossing. The specification values are not affected by the amount of tJIT(per) applied, because the setup and hold times are relative to the clock signal crossing that latches the command/address. Regardless of clock jitter values, these values must be met. tDSS, tDSH These parameters are measured from a data strobe signal crossing (DQSx, DQSx#) to its clock signal crossing (CK/CK#). The specification values are not affected by the amount of tJIT(per)) applied, because the setup and hold times are relative to the clock signal crossing that latches the command/address. Regardless of clock jitter values, these values must be met. tDQSS This parameter is measured from the clock signal (CK, /CK) crossing to the first latching data strobe signal (DQSx, /DQSx) crossing. When the device is operated with input clock jitter, this parameter must be derated by the actual tJIT(per),act of the input clock in excess of tJIT(per),allowed. tDQSS(min,derated) = 0.75 tDQSS(max,derated) = 1.25 – tJIT(per),act,min – tJIT(per),allowed, min tCK(avg) tJIT(per),act,max – tJIT(per),allowed, max tCK(avg) For example, if the measured jitter into an LPDDR2-800 device has tCK(avg) = 2500ps, tJIT(per),act,min = -172ps, and tJIT(per),act,max = +193ps, then: tDQSS,(min,derated) = 0.75 - (tJIT(per),act,min - tJIT(per),allowed,min)/tCK(avg) = 0.75 - (-172 + 100)/2500 = 0.7788 tCK(avg), and tDQSS,(max,derated) = 1.25 - (tJIT(per),act,max - tJIT(per),allowed,max)/tCK(avg) = 1.25 - (193 - 100)/2500 = 1.2128 tCK(avg). 140 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 8/6/2014 IS43/46LD16640A IS43/46LD32320A ORDERING INFORMATION Commercial Range: Tc = 0°C to +85°C Clock Speed Grade Order Part No. Organization Package 333 MHz -3 IS43LD16640A-3BL 64Mb x 16, LPDDR2-S4 134 ball BGA, lead free IS43LD32320A-3BL 32Mb x 32, LPDDR2-S4 134 ball BGA, lead free IS43LD16640A-25BL 64Mb x 16, LPDDR2-S4 134 ball BGA, lead free IS43LD32320A-25BL 32Mb x 32, LPDDR2-S4 134 ball BGA, lead free 400 MHz -25 Industrial Range: Tc = -40°C to +85°C Clock Speed Grade Order Part No. Organization Package 333 MHz -3 IS43LD16640A-3BLI 64Mb x 16, LPDDR2-S4 134 ball BGA, lead free IS43LD32320A-3BLI 32Mb x 32, LPDDR2-S4 134 ball BGA, lead free 400 MHz -25 IS43LD16640A-25BLI 64Mb x 16, LPDDR2-S4 134 ball BGA, lead free IS43LD32320A-25BLI 32Mb x 32, LPDDR2-S4 134 ball BGA, lead free Automotive, A1 Range: Tc = -40°C to +85°C Clock Speed Grade Order Part No. Organization Package 333 MHz -3 IS46LD16640A-3BLA1 64Mb x 16, LPDDR2-S4 134 ball BGA, lead free IS46LD32320A-3BLA1 32Mb x 32, LPDDR2-S4 134 ball BGA, lead free IS46LD32320A-3BPLA1 32Mb x 32, LPDDR2-S4 168 ball PoP BGA, lead free IS46LD16640A-25BLA1 64Mb x 16, LPDDR2-S4 134 ball BGA, lead free IS46LD32320A -25BLA1 32Mb x 32, LPDDR2-S4 134 ball BGA, lead free 400 MHz -25 IS46LD32320A -25BPLA1 32Mb x 32, LPDDR2-S4 168 ball PoP BGA, lead free Automotive, A2 Range: Tc = -40°C to +105°C Clock Speed Grade Order Part No. Organization Package 333 MHz -3 IS46LD16640A-3BLA2 64Mb x 16, LPDDR2-S4 134 ball BGA, lead free IS46LD32320A-3BLA2 32Mb x 32, LPDDR2-S4 134 ball BGA, lead free IS46LD32320A-3BPLA2 32Mb x 32, LPDDR2-S4 168 ball PoP BGA, lead free IS46LD16640A-25BLA2 64Mb x 16, LPDDR2-S4 134 ball BGA, lead free IS46LD32320A -25BLA2 32Mb x 32, LPDDR2-S4 134 ball BGA, lead free 400 MHz -25 IS46LD32320A -25BPLA2 32Mb x 32, LPDDR2-S4 168 ball PoP BGA, lead free Integrated Silicon Solution, Inc. — www.issi.com 141 Rev. A 8/6/2014 IS43/46LD16640A IS43/46LD32320A 142 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 8/6/2014 IS43/46LD16640A IS43/46LD32320A Integrated Silicon Solution, Inc. — www.issi.com 143 Rev. A 8/6/2014