IS49NLS96400,IS49NLS18320
576Mb (x9, x18) Separate I/O RLDRAM 2 Memory
JANUARY 2020
FEATURES
400MHz DDR operation (800Mb/s/pin data rate)
14.4 Gb/s peak bandwidth (x18 Separate I/O at 400
MHz clock frequency)
Reduced cycle time (15ns at 400MHz)
32ms refresh (16K refresh for each bank; 128K
refresh command must be issued in total each 32ms)
8 internal banks
Non-multiplexed addresses (address multiplexing
option available)
SRAM-type interface
Programmable READ latency (RL), row cycle time,
and burst sequence length
Balanced READ and WRITE latencies in order to
optimize data bus utilization
Data mask signals (DM) to mask signal of WRITE
data; DM is sampled on both edges of DK.
Differential input clocks (CK, CK#)
Differential input data clocks (DKx, DKx#)
On-die DLL generates CK edge-aligned data and
output data clock signals
Data valid signal (QVLD)
HSTL I/O (1.5V or 1.8V nominal)
25-60Ω matched impedance outputs
2.5V VEXT, 1.8V VDD, 1.5V or 1.8V VDDQ I/O
On-die termination (ODT) RTT
IEEE 1149.1 compliant JTAG boundary scan
Operating temperature:
Commercial
(TC = 0° to +95°C; TA = 0°C to +70°C),
Industrial
(TC = -40°C to +95°C; TA = -40°C to +85°C)
OPTIONS
Package:
144-ball WBGA (lead-free)
Configuration:
64Mx9
32Mx18
Clock Cycle Timing:
Speed Grade
-25E
-25
-33
Unit
tRC
15
20
20
ns
tCK
2.5
2.5
3.3
ns
Copyright © 2020 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the
latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can
reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such
applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
RLDRAM is a registered trademark of Micron Technology, Inc.
Integrated Silicon Solution, Inc. – www.issi.com –
Rev. B, 01/22/2020
1
IS49NLS96400,IS49NLS18320
1 Package Ballout and Description
1
2
3
4
5
6
7
8
9
10
11
12
A
VREF
VSS
VEXT
VSS
VSS
VEXT
TMS
TCK
B
VDD
DNU3
DNU3
VSSQ
VSSQ
Q0
D0
VDD
C
VTT
DNU3
DNU3
VDDQ
VDDQ
Q1
D1
VTT
D
1
3
DNU3
VSSQ
VSSQ
QK0#
QK0
VSS
3
3
VDDQ
VDDQ
Q2
D2
A20
3
E
A22
A21
DNU
DNU
3
DNU
F
A5
DNU
DNU
VSSQ
VSSQ
Q3
D3
QVLD
G
A8
A6
A7
VDD
VDD
A2
A1
A0
H
BA2
A9
VSS
VSS
VSS
VSS
A4
A3
2
2
J
NF
VDD
VDD
VDD
VDD
BA0
CK
K
DK
DK#
VDD
VDD
VDD
VDD
BA1
CK#
L
REF#
CS#
VSS
VSS
VSS
VSS
A14
A13
M
WE#
A16
A17
VDD
VDD
A12
A11
A10
N
A18
DNU3
DNU3
VSSQ
VSSQ
Q4
D4
A19
P
A15
3
DNU
3
DNU
VDDQ
VDDQ
Q5
D5
DM
R
VSS
DNU3
DNU3
VSSQ
VSSQ
Q6
D6
VSS
VTT
3
3
VDDQ
VDDQ
Q7
D7
VTT
3
T
NF
DNU
3
DNU
U
VDD
DNU
DNU
VSSQ
VSSQ
Q8
D8
VDD
V
VREF
ZQ
VEXT
VSS
VSS
VEXT
TDO
TDI
Symbol
VDD
VSS
VDDQ
VSSQ
VEXT
VREF
VTT
A*
BA*
D*
Q*
DK*
QK*
CK*
DM
CS#,WE#,REF#
ZQ
QVLD
DNU,NF
T*
Total
Description
Supply voltage
Ground
DQ power supply
DQ Ground
Supply voltage
Reference voltage
Termination voltage
Address - A0-22
Banks - BA0-2
Input data
Output data
Input data clock(Differential inputs)
Output data clocks(outputs)
Input clocks (CK, CK#)
Input data mask
Command control pins
External impedance (25–60Ω)
Data valid
Do not use, No function
JTAG - TCK,TMS,TDO,TDI
Ball count
16
16
8
12
4
2
4
23
3
9
9
2
2
2
1
3
1
1
22
4
144
Notes:
NOTES:
1.
forfor
future
use. This
may
optionally
1)Reserved
Reserved
future
use.
This
may be
connected to GND.
optionally
be
connected
to
GND.
2. No function. This signal is internally connected and
2)
for future of
use.
This
signal
is
hasReserved
parasitic characteristics
a clock
input
signal.
internally
connected
and has
This may optionally
be connected
to parasitic
GND.
3. Do not use. This of
signal
internallyinput
connected
and
characteristics
anisaddress
signal.
has
parasitic
characteristics
a I/O. This may
This
may optionally
beofconnected
to
optionally be connected to GND. Note that if ODT is
GND.
enabled, these pins are High-Z.
3) No function. This signal is internally
connected and has parasitic
characteristics of a clock input signal.
This may optionally be connected to
GND.
4) Do not use. This signal is internally
connected and has parasitic
characteristics of a I/O. This may
optionally be connected to GND. Note
that if ODT is enabled, these pins will be
connected to VTT.
1.1 576Mb (64Mx9) Separate I/O BGA Ball-out (Top View)
Integrated Silicon Solution, Inc. – www.issi.com –
Rev. B, 01/22/2020
2
IS49NLS96400,IS49NLS18320
1.2 576Mb (32Mx18) Separate I/O BGA Ball-out (Top View)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
1
VREF
VDD
VTT
A221
A212
A5
A8
BA2
NF3
DK
REF#
WE#
A18
A15
VSS
VTT
VDD
VREF
Symbol
VDD
VSS
VDDQ
VSSQ
VEXT
VREF
VTT
A*
BA*
D*
Q*
DK*
QK*
CK*
DM
CS#,WE#,REF#
ZQ
QVLD
NF
T*
Total
2
VSS
D4
D5
D6
D7
D8
A6
A9
NF3
DK#
CS#
A16
D14
D15
QK1
D16
D17
ZQ
3
VEXT
Q4
Q5
Q6
Q7
Q8
A7
VSS
VDD
VDD
VSS
A17
Q14
Q15
QK1#
Q16
Q17
VEXT
4
VSS
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
VDD
VSS
VDD
VDD
VSS
VDD
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
VSS
Description
Supply voltage
Ground
DQ power supply
DQ Ground
Supply voltage
Reference voltage
Termination voltage
Address - A0-22
Banks - BA0-2
Input data
Output data
Input data clock(Differential inputs)
Output data clocks(outputs)
Input clocks (CK, CK#)
Input data mask
Command control pins
External impedance (25–60Ω)
Data valid
Do not use, No function
JTAG - TCK,TMS,TDO,TDI
Integrated Silicon Solution, Inc. – www.issi.com –
Rev. B, 01/22/2020
5
6
7
8
Ball count
16
16
8
12
4
2
4
23
3
18
18
2
4
2
1
3
1
1
2
4
144
9
VSS
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
VDD
VSS
VDD
VDD
VSS
VDD
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
VSS
10
VEXT
Q0
Q1
QK0#
Q2
Q3
A2
VSS
VDD
VDD
VSS
A12
Q9
Q10
Q11
Q12
Q13
VEXT
11
TMS
D0
D1
QK0
D2
D3
A1
A4
BA0
BA1
A14
A11
D9
D10
D11
D12
D13
TDO
12
TCK
VDD
VTT
VSS
A20
QVLD
A0
A3
CK
CK#
A13
A10
A19
DM
VSS
VTT
VDD
TDI
Notes:
NOTES:
1.
for future
use. This
mayThis
optionally
1)Reserved
Reserved
for future
use.
may be
connected to GND.
optionally be connected to GND.
2. Reserved for future use. This signal is internally
2) Reserved
forparasitic
futurecharacteristics
use. This signal
is
connected
and has
of an address
internally
connected
and
has
parasitic
input signal. This may optionally be connected to GND.
3.
characteristics
No function. Thisof
signal
an isaddress
internallyinput
connected
signal.
and
has
parasitic
characteristicsbe
ofconnected
a clock input to
signal.
This
This
may optionally
GND.
may
optionally
be
connected
to
GND.
3) No function. This signal is internally
connected and has parasitic characteristics
of a clock input signal. This may optionally
be connected to GND.
4) Do not use. This signal is internally
connected and has parasitic characteristics
of a I/O. This may optionally be connected
to GND. Note that if ODT is enabled, these
pins will be connected to VTT.
3
IS49NLS96400,IS49NLS18320
1.3 Ball Descriptions
Symbol
Type
A*
Input
Address inputs: Defines the row and column addresses for READ and WRITE operations. During a MODE
REGISTER SET, the address inputs define the register settings. They are sampled at the rising edge of CK.
BA*
Input
Bank address inputs: Selects to which internal bank a command is being applied to.
CK, CK#
Input
Input clock: CK and CK# are differential input clocks. Addresses and commands are latched on the rising
edge of CK. CK# is ideally 180 degrees out of phase with CK.
CS#
Input
Chip select: CS# enables the command decoder when LOW and disables it when HIGH. When the command
decoder is disabled, new commands are ignored, but internal operations continue.
D*
Input
Data input: The D signals form the input data bus. During WRITE commands, the data is sampled at both
edges of DK.
DK, DK#
Input
Input data clock: DK* and DK*# are the differential input data clocks. All input data is referenced to both
edges of DK*. DK*# is ideally 180 degrees out of phase with DK*. For both the x9 and x18 devices, all D
signals are referenced to DK and DK#. DK and DK# pins must always be supplied to the device.
DM
Input
Input data mask: The DM signal is the input mask signal for WRITE data. Input data is masked when DM is
sampled HIGH. DM is sampled on both edges of DK. Tie signal to ground if not used.
TCK
Input
IEEE 1149.1 clock input: This ball must be tied to VSS if the JTAG function is not used.
TMS,TDI
Input
IEEE 1149.1 test inputs: These balls may be left as no connects if the JTAG function is not used.
WE#,
REF#
Input
Command inputs: Sampled at the positive edge of CK, WE# and REF# define (together with CS#) the
command to be executed.
VREF
Input
Input reference voltage: Nominally VDDQ/2. Provides a reference voltage for the input buffers.
ZQ
I/O
Q*
Output
Data input: The Q signals form the output data bus. During READ commands, the data is referenced to both
edges of QK*.
QK*,
QK*#
Output
Output data clocks: QK* and QK*# are opposite polarity, output data clocks. They are free running, and
during READs, are edge-aligned with data output from the memory. QK*# is ideally 180 degrees out of
phase with QK*. For the x18 device, QK0 and QK0# are aligned with Q0-Q8, while QK1 and QK1# are aligned
with Q9-Q17. For the x9 device, all Q signals are aligned with QK0 and QK0#.
QVLD
Output
Data valid: The QVLD pin indicates valid output data. QVLD is edge-aligned with QK* and QK*#.
TDO
Output
IEEE 1149.1 test output: JTAG output. This ball may be left as no connect if the JTAG function is not used.
VDD
Supply
Power supply: Nominally, 1.8V.
VDDQ
Supply
DQ power supply: Nominally, 1.5V or 1.8V. Isolated on the device for improved noise immunity.
VEXT
Supply
Power supply: Nominally, 2.5V.
VSS
Supply
Ground.
VSSQ
Supply
DQ ground: Isolated on the device for improved noise immunity.
VTT
A22
Supply
-
Power supply: Isolated termination supply. Nominally, VDDQ/2.
Reserved for future use: This signal is not connected and can be connected to ground.
DNU
-
Do not use: These balls may be connected to ground. Note that if ODT is enabled, these pins are High-Z.
NF
-
No function: These balls can be connected to ground.
Description
External impedance (25–60Ω): This signal is used to tune the device outputs to the system data bus
impedance. Q output impedance is set to 0.2 × RQ, where RQ is a resistor from this signal to ground.
Connecting ZQ to GND invokes the minimum impedance mode.
Integrated Silicon Solution, Inc. – www.issi.com –
Rev. B, 01/22/2020
4
IS49NLS96400,IS49NLS18320
2 Electrical Specifications
2.1 Absolute Maximum Ratings
Item
Min
0.3
0.3
0.3
0.3
I/O Voltage
Voltage on VEXT supply relative to VSS
Voltage on VDD supply relative to VSS
Voltage on VDDQ supply relative to VSS
Max
VDDQ + 0.3
2.8
2.1
2.1
Units
V
V
V
V
Note: Stress greater than those listed in this table may cause permanent damage to the device. This is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability.
2.2 DC Electrical Characteristics and Operating Conditions
Description
Conditions
Supply voltage
Supply voltage
Isolated output buffer supply
Reference voltage
Termination voltage
Input high voltage
Input low voltage
Symbol
Min
Max
Units
VEXT
VDD
VDDQ
VREF
VTT
VIH
VIL
2.38
1.7
1.4
0.49 x VDDQ
0.95 x VREF
VREF + 0.1
VSSQ 0.3
(VDDQ/2)/
(1.15 x RQ/5)
(VDDQ/2)/
(1.15 x RQ/5)
5
5
5
5
2.63
1.9
VDD
0.51 x VDDQ
1.05 x VREF
VDDQ + 0.3
VREF 0.1
(VDDQ/2)/
(0.85 x RQ/5)
(VDDQ/2)/
(0.85 x RQ/5)
5
5
5
5
V
V
V
V
V
V
V
Output high current
VOH = VDDQ/2
IOH
Output low current
VOL = VDDQ/2
IOL
0V ≤ VIN ≤ VDD
0V ≤ VIN ≤ VDD
0V ≤ VIN ≤ VDDQ
ILC
ILI
ILO
IREF
Clock input leakage current
Input leakage current
Output leakage current
Reference voltage current
A
A
Notes
2
2,3
4,5,6
7,8
2
2
9, 10,
11
9, 10,
11
µA
µA
µA
µA
Notes:
1. All voltages referenced to VSS (GND).
2. Overshoot: VIH (AC) ≤ VDD + 0.7V for t ≤ tCK/2. Undershoot: VIL (AC) ≥ –0.5V for t ≤ tCK/2. During normal operation, VDDQ must not exceed VDD. Control input signals
may not have pulse widths less than tCK/2 or operate at frequencies exceeding tCK (MAX).
3. VDDQ can be set to a nominal 1.5V ± 0.1V or 1.8V ± 0.1V supply.
4. Typically the value of VREF is expected to be 0.5 x VDDQ of the transmitting device. VREF is expected to track variations in VDDQ.
5. Peak-to-peak AC noise on VREF must not exceed ±2 percent VREF (DC).
6. VREF is expected to equal VDDQ/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise (non-common mode) on VREF
may not exceed ±2 percent of the DC value. Thus, from VDDQ/2, VREF is allowed ±2 percent VDDQ/2 for DC error and an additional ±2 percent VDDQ/2 for AC noise.
This measurement is to be taken at the nearest VREF bypass capacitor.
7. VTT is expected to be set equal to VREF and must track variations in the DC level of VREF.
8. On-die termination may be selected using mode register A9 (for non-multiplexed address mode) or Ax9 (for multiplexed address mode). A resistance RTT from
each data input signal to the nearest VTT can be enabled. RTT = 125–185Ω at 95°C TC.
9. IOH and IOL are defined as absolute values and are measured at VDDQ /2. IOH flows from the device, IOL flows into the device.
10. If MRS bit A8 or Ax8 is 0, use RQ = 250Ω in the equation in lieu of presence of an external impedance matched resistor.
2.3 Capacitance
(TA = 25 °C, f = 1MHz)
Parameter
Address / Control Input capacitance
I/O, Output, Other capacitance (D, Q, DM, QK, QVLD)
Clock Input capacitance
JTAG pins
Symbol
CIN
CIO
CCLK
CJ
Test Conditions
VIN=0V
VIO=0V
VCLK=0V
VJ=0V
Min
1.5
3.5
2
2
Max
2.5
5
3
5
Units
pF
pF
pF
pF
Note. These parameters are not 100% tested and capacitance is not tested on ZQ pin.
Integrated Silicon Solution, Inc. – www.issi.com –
Rev. B, 01/22/2020
5
IS49NLS96400,IS49NLS18320
2.4 Operating Conditions and Maximum Limits
Description
Condition
Symbol
-25E
-25
-33
units
ISB1(VDD) x9/x18
53
48
48
mA
ISB1(VEXT)
5
5
5
mA
ISB2(VDD) x9/x18
293
288
233
mA
ISB2(VEXT)
5
5
5
mA
IDD1(VDD) x9/x18
380
348
305
mA
IDD1(VEXT)
15
15
13
mA
IDD2(VDD) x9/x18
400
362
319
mA
IDD2(VEXT)
15
15
13
mA
IDD3 (VDD) x9/x18
430
408
368
mA
IDD3(VEXT)
20
20
18
mA
Eight-bank cyclic refresh; Continuous address/data;
Command bus remains in refresh for all eight banks
IREF1(VDD) x9/x18
790
785
615
mA
IREF1(VEXT)
80
80
70
mA
Single-bank refresh; Sequential bank access; Half
address transitions once every tRC, continuous data
IREF2(VDD) x9/x18
330
325
267
mA
IREF2(VEXT)
20
20
18
mA
BL=2; Cyclic bank access; Half of address bits change
every clock cycle; Continuous data; measurement is
taken during continuous WRITE
IDD2W(VDD) x9/x18
980
970
819
mA
IDD2W(VEXT)
50
50
40
mA
BL=4; Cyclic bank access; Half of address bits change
every 2 clock cycles; Continuous data; Measurement is
taken during continuous WRITE
IDD4W(VDD) x9/x18
785
779
609
mA
IDD4W(VEXT)
30
30
25
mA
BL=8; Cyclic bank access; Half of address bits change
every 4 clock cycles; continuous data; Measurement is
taken during continuous WRITE
IDD8W(VDD) x9/x18
675
668
525
mA
IDD8W(VEXT)
30
30
25
mA
BL=2; Cyclic bank access; Half of address bits change
every clock cycle; Measurement is taken during
continuous READ
IDD2R(VDD) x9/x18
865
860
735
mA
IDD2R(VEXT)
50
50
40
mA
BL=4; Cyclic bank access; Half of address bits change
every clock cycle; Measurement is taken during
continuous READ
IDD4R(VDD) x9/x18
685
680
525
mA
IDD4R(VEXT)
30
30
25
mA
BL=8; Cyclic bank access; Half of address bits change
every clock cycle; Measurement is taken during
continuous READ
IDD8R(VDD) x9/x18
575
570
450
mA
IDD8R(VEXT)
30
30
25
mA
Standby
current
tCK = idle; All banks idle; No inputs toggling
Active
standby
current
CS# =1; No commands; Bank address incremented and
half address/data change once every 4 clock cycles
Operational
current
BL=2; Sequential bank access; Bank transitions once
every tRC; Half address transitions once every tRC; Read
followed by write sequence; continuous data during
WRITE commands
BL = 4; Sequential bank access; Bank transitions once
every tRC; Half address transitions once every tRC; Read
followed by write sequence; Continuous data during
WRITE commands
BL = 8; Sequential bank access; Bank transitions once
every tRC; half address transitions once every tRC; Read
followed by write sequence; continuous data during
WRITE commands
Burst
refresh
current
Distributed
refresh
current
Operating
burst write
current
Operating
burst read
current
Integrated Silicon Solution, Inc. – www.issi.com –
Rev. B, 01/22/2020
6
IS49NLS96400,IS49NLS18320
Notes:
1) IDD specifications are tested after the device is properly initialized. +0°C ≤ T C ≤ +95°C; +1.7V ≤ VDD ≤ +1.9V, +2.38V ≤ VEXT ≤ +2.63V, +1.4V ≤ VDDQ ≤ VDD, VREF =
VDDQ/2.
2) tCK = tDK = MIN, tRC = MIN.
3) Definitions for IDD conditions:
a.
LOW is defined as VIN ≤ VIL(AC) MAX.
b. HIGH is defined as VIN ≥ VIH(AC) MIN.
c.
Stable is defined as inputs remaining at a HIGH or LOW level.
d. Floating is defined as inputs at VREF = VDDQ/2.
e. Continuous data is defined as half the D or Q signals changing between HIGH and LOW every half clock cycle (twice per clock).
f.
Continuous address is defined as half the address signals changing between HIGH and LOW every clock cycle (once per clock).
g.
Sequential bank access is defined as the bank address incrementing by one every tRC.
h. Cyclic bank access is defined as the bank address incrementing by one for each command access. For BL = 2 this is every clock, for BL = 4 this is every
other clock, and for BL = 8 this is every fourth clock.
4) CS# is HIGH unless a READ, WRITE, AREF, or MRS command is registered. CS# never transitions more than once per clock cycle.
5) IDD parameters are specified with ODT disabled.
6) Tests for AC timing, IDD, and electrical AC and DC characteristics may be conducted at nominal reference/supply voltage levels, but the related specifications
and device operations are tested for the full voltage range specified.
7) IDD tests may use a VIL-to-VIH swing of up to 1.5V in the test environment, but input timing is still referenced to V REF (or to the crossing point for CK/CK#).
Parameter specifications are tested for the specified AC input levels under normal use conditions. The minimum slew rate for the input signals used to test the
device is 2 V/ns in the range between VIL(AC) and VIH(AC).
2.5 Recommended AC Operating Conditions
(+0°C ≤ TC ≤ +95°C; +1.7V ≤ VDD ≤ +1.9V, unless otherwise noted.)
Parameter
Symbol
Min
Max
Units
Input HIGH voltage
VIH(AC)
VREF + 0.2
-
V
Input LOW voltage
VIL(AC)
-
VREF – 0.2
V
Notes:
1. Overshoot: VIH (AC) ≤ VDDQ + 0.7V for t ≤ tCK/2
2. Undershoot: VIL (AC) ≥ – 0.5V for t ≤ tCK/2
3. Control input signals may not have pulse widths less than tCKH(MIN) or operate at cycle rates less than tCK(MIN.).
2.6 Temperature and Thermal Impedance.
Temperature Limits
Parameter
Reliability junction temperature 1
Operating junction temperature
2
Operating case temperature 3
Symbol
Min
Max
Units
TJ
0
110
°C
TJ
0
100
°C
TC
0
95
°C
Notes:
1. Temperatures greater than 110°C may cause permanent damage to the device. This is a stress rating only and functional operation of the device at or above this
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability of the part.
2. Junction temperature depends upon cycle time, loading, ambient temperature, and airflow.
3. MAX operating case temperature; TC is measured in the center of the package. Device functionality is not guaranteed if the device exceeds maximum TC during
operation.
Thermal Resistance
Package
Substrate
144-ball FBGA
4-layer
Theta-ja
(Airflow = 0m/s)
20.6
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Theta-ja
(Airflow = 1m/s)
19.1
Theta-ja
(Airflow = 2m/s)
17.2
Theta-jc
2.4
Unit
C/W
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IS49NLS96400,IS49NLS18320
2.7 AC Electrical Characteristics (1, 2, 3, 4)
Description
Symbol
-25E (2.5ns
@tRC=15ns)
-25 (2.5ns
@tRC=20ns)
-33 (3.3ns
@tRC=20ns)
Units
Min
Max
Min
Max
Min
Max
tCK
2.5
5.7
2.5
5.7
3.3
5.7
ns
tDK
tCK
–
tCK
–
tCK
–
ns
tJITPER
–150
150
–150
150
–200
200
ps
tJITCC
–
300
–
300
–
400
ps
tCKH/tDKH
0.45
0.55
0.45
0.55
0.45
0.55
tCK
tCKL/tDKL
0.45
0.55
0.45
0.55
0.45
0.55
tCK
tCKDK
–0.45
0.5
–0.45
0.5
–0.45
1.2
ns
tMRSC
6
–
6
–
6
–
tCK
tAS/tCS
0.4
–
0.4
–
0.5
–
ns
tDS
0.25
–
0.25
–
0.3
–
ns
tAH/tCH
0.4
–
0.4
–
0.5
–
ns
tDH
0.25
–
0.25
–
0.3
–
ns
tQKH
0.9
1.1
0.9
1.1
0.9
1.1
tCKH
tQKL
0.9
1.1
0.9
1.1
0.9
1.1
tCKL
tQHP
MIN(tQKH,
tQKL)
–
MIN(tQKH,
tQKL)
–
MIN(tQKH,
tQKL)
–
tCKQK
–0.25
0.25
–0.25
0.25
–0.3
0.3
ns
tQKQ0,
tQKQ1
–0.2
0.2
–0.2
0.2
–0.25
0.25
ns
tQKQ
–0.3
0.3
–0.3
0.3
–0.35
0.35
ns
tQKVLD
–0.3
0.3
–0.3
0.3
–0.35
0.35
ns
Data valid window
tDVW
tQHP (tQKQx
[MAX] +
|tQKQx
[MIN]|)
–
tQHP (tQKQx
[MAX] +
|tQKQx
[MIN]|)
–
tQHP (tQKQx
[MAX] +
|tQKQx
[MIN]|)
–
Average periodic
refresh interval (9)
tREFI
–
0.24
–
0.24
–
0.24
Input clock cycle time
Input data clock cycle
time
Clock jitter: period(5, 6)
Clock jitter: cycle-tocycle
Clock HIGH time
Clock LOW time
Clock to input data
clock
Mode register set
cycle time to any
command
Address/command
and input setup time
Data-in and data mask
to DK setup time
Address/command
and input hold time
Data-in and data mask
to DK hold time
Output data clock
HIGH time
Output data clock
LOW time
Half-clock period
QK edge to clock edge
skew
QK edge to output
data edge (7)
QK edge to any
output data edge (8)
QK edge to QVLD
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μs
8
IS49NLS96400,IS49NLS18320
Notes:
1. All timing parameters are measured relative to the crossing point of CK/CK#, DK/DK# and to the crossing point with V REF of the command, address, and data
signals.
2. Outputs measured with equivalent load:
VTT
50 Ω
Q
Test Point
10 pF
3.
4.
5.
6.
7.
8.
9.
Tests for AC timing, IDD, and electrical AC and DC characteristics may be conducted at nominal reference/supply voltage levels, but the related specifications
and device operations are tested for the full voltage range specified.
AC timing may use a VIL-to-VIH swing of up to 1.5V in the test environment, but input timing is still referenced to V REF (or to the crossing point for CK/CK#), and
parameter specifications are tested for the specified AC input levels under normal use conditions. The minimum slew rate for the input signals used to test the
device is 2 V/ns in the range between VIL(AC) and VIH(AC).
Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.
Frequency drift is not allowed.
For a x18 device, Q0–Q8 is referenced to tQKQ0 and Q9–Q17 is referenced to tQKQ1. For a x9 device, Q0–Q8 is referenced to tQKQ0.
tQKQ takes into account the skew between any QKx and any Q.
To improve efficiency, eight AREF commands (one for each bank) can be posted to the memory on consecutive cycles at periodic intervals of 1.95μs.
2.8 Clock Input Conditions
Differential Input Clock Operating Conditions
Parameter
Clock Input Voltage Level
Clock Input Differential Voltage Level
Clock Input Differential Voltage Level
Clock Input Crossing Point Voltage Level
Symbol
VIN(DC)
VID(DC)
VID(AC)
VIX(AC)
Min
-0.3
0.2
0.4
VDDQ/2-0.15
Max
VDDQ+0.3
VDDQ+0.6
VDDQ+0.6
VDDQ/2+0.15
Units
V
V
V
V
Notes
8
8
9
Clock Input Example
CK#
VDDQ/2+0.15V, VIX(AC) MAX
VDDQ/2
(10)
VID(DC)(11)
VID(AC)(12)
VDDQ/2-0.15V, VIX(AC) MIN
CK
Notes:
1. DKx and DKx# have the same requirements as CK and CK#.
2. All voltages referenced to VSS.
3. Tests for AC timing, IDD and electrical AC and DC characteristics may be conducted at normal reference/supply voltage levels; but the related specifications and
device operations are tested for the full voltage range specified.
4. AC timing and IDD tests may use a VIL to VIH swing of up to 1.5V in the test environment, but input timing is still referenced to VREF (or the crossing point for
CK/CK#), and parameters specifications are tested for the specified AC input levels under normal use conditions. The minimum slew rate for the input signals
used to test the device is 2V/ns in the range between VIL(AC) and VIH(AC).
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IS49NLS96400,IS49NLS18320
5.
7.
8.
The AC and DC input level specifications are as defined in the HSTL Standard (i.e. the receiver will effectively switch as a result of the signal crossing the AC input
level, and will remain in that state as long as the signal does not ring back above[below] the DC input LOW[HIGH] level).
The CK/CK# input reference level (for timing referenced to CK/CK#) is the point at which CK and CK# cross. The input reference level for signal other than CK/CK#
is VREF.
CK and CK# input slew rate must be ≥ 2V/ns (≥ 4V/ns if measured differentially).
VID is the magnitude of the difference between the input level on CK and input level on CK#.
9.
10.
11.
12.
The value of VIX is expected to equal VDDQ/2 of the transmitting device and must track variations in the DC level of the same.
CK and CK# must cross within the region.
CK and CK# must meet at least VID(DC) (MIN.) when static and centered around VDDQ/2.
Minimum peak-to-peak swing.
6.
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IS49NLS96400,IS49NLS18320
3 Functional Descriptions
3.1 Power-up and Initialization (1)
The RLDRAM 2 Memory must be powered-up and initialized using the specific steps listed below:
1. Apply power by ramping up supply voltages V EXT, VDD, VDDQ, VREF, and VTT. Apply VDD and VEXT before or at the same time as VDDQ (2).
Power-up sequence begins when both VDD and VEXT approach their nominal levels. Afterwards, apply VDDQ before or at the same
time as VREF and VTT. Once the supply voltages are stable, clock inputs CK/CK# and DK/DK# can be applied. Register NOP
commands to the control pins to avoid issuing unwanted commands to the device.
2. Keep applying stable conditions for a minimum of 200 µs.
3. Register at least three consecutive MRS commands consisting of two or more dummy MRS commands and one valid MRS
command. Timing parameter tMRSC is not required to be met during these consecutive MRS commands but asserting a LOW logic
to the address signals is recommended.
4. tMRSC timing delay after the valid MRS command, Auto Refresh commands to all 8 banks and 1,024 NOP commands must be
issued prior to normal operation. The Auto Refresh commands to the 8 banks can be issued in any order with respect to the
1,024 NOP commands. Please note that the tRC timing parameter must be met between an Auto Refresh command and a valid
command in the same bank.
5. The device is now ready for normal operation.
Notes:
1. Operational procedure other than the one listed above may result in undefined operations and may permanently damage the device.
2. VDDQ can be applied before VDD but will result in all D and Q data pins, DM, and other pins with an output driver to go logic HIGH (instead of tri-state) and will
remain HIGH until the VDD is the same level as VDDQ. This method is not recommended to avoid bus conflicts during the power-up.
3.2 Power-up and Initialization Flowchart
VDD and VEXT
ramp up (1)
VDDQ ramp up (1)
Issue dummy
2nd MRS command (2)
VREF and VTT
ramp up (1)
Issue valid
3rd MRS command (2)
Apply stable
CK/CK# and DK/DK#
Assert NOP for tMRS
Wait 200µs minimum
Issue AREF
commands to all 8
banks (3)
Issue dummy
1st MRS command (2)
Issue 1,024 NOP
commands (3)
RLDRAM is now ready
for normal operation
Notes:
1. The supply voltages can be ramped up simultaneously.
2. The dummy and valid MRS commands must be issued in consecutive clock cycles. At least two dummy MRS commands are required. It is recommended to
assert a LOW logic on the address signals during the dummy MRS commands.
3. The Auto Refresh commands can be issued in any order with respect to the 1,024 NOP commands. However, timing parameter tRC must be met before issuing
any valid command in a bank after an AREF command to the same bank has been issued.
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IS49NLS96400,IS49NLS18320
3.3 Power-up and Initialization Timing Diagram
NON-Multiplexed Address Mode
VEXT, VDD,
VDDQ, VREF,
VTT
tCKH
tCKL
tCK
CK
~~
~~
~~
~~
CK#
Command
NOP
MRS1,2
NOP
MRS1,2
MRS2
AREFBA0
NOP
tMRSC
200us(Min)
AREFBA7
Refresh all 8 banks
Any5
1024 NOPs
Don’t care
Notes:
1. It is recommended that the address input signals be driven LOW during the dummy MRS commands.
2. A10–A17 must be LOW.
3. DLL must be reset if tCK or VDD are changed.
4. CK and CK# must be separated at all times to prevent invalid commands from being issued.
5. The Auto Refresh commands can be issued in any order with respect to the 1,024 NOP commands. However, timing parameter tRC must be met before issuing
any valid command in a bank after an AREF command to the same bank has been issued.
Multiplexed Address Mode
VEXT, VDD,
VDDQ,
VREF, VTT
CK
tCKH
CK#
Command
tCKL
tCK
~
~
~~
NOP
NOP
ADDRESS
~~
~~
~~
MRS
MRS
MRS
MRS
NOP
AREF
AREF
Any
A1,2
A1,2
A2,3
Ax2,4
Ay
Bank0
Bank7
Any
200us(Min)
tMRSC
tMRSC
Refresh all 8
banks
1024NOPs
6
Don’t care
Notes:
1. It is recommended that the address input signals be driven LOW during the dummy MRS commands.
2. A10–A18 must be LOW.
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IS49NLS96400,IS49NLS18320
3.
4.
5.
6.
Set address A5 HIGH. This enables the part to enter multiplexed address mode when in non-multiplexed mode operation. Multiplexed address mode can also be
entered at some later time by issuing an MRS command with A5 HIGH. Once address bit A5 is set HIGH, tMRSC must be satisfied before the two cycle
multiplexed mode MRS command is issued.
Address A5 must be set HIGH. This and the following step set the desired mode register once the memory is in multiplexed address mode.
CK and CK# must be separated at all times to prevent invalid commands from being issued.
The Auto Refresh commands can be issued in any order with respect to the 1,024 NOP commands. However, timing parameter tRC must be met before issuing
any valid command (Any) in a bank after an AREF command to the same bank has been issued.
3.4 Mode Register Setting and Features
MRS - Non-Multiplexed Mode
MRS - Multiplexed Mode
CK
CK#
CS#
Any
Valid
WE#
Any
Valid
REF#
ADD
Valid
Code
Ax
Valid
Ay
tMRSC
tMRSC
Don’t care
Note: The MRS command can only be issued when all banks are idle and no bursts are in progress.
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IS49NLS96400,IS49NLS18320
The Mode Register Set command stores the data for controlling the various operating modes of the memory using address inputs
A0-A17 as mode registers. During the MRS command, the cycle time and the read/write latency of the memory can be selected from
different configurations. The MRS command also programs the memory to operate in either Multiplexed Address Mode or Nonmultiplexed Address Mode. In addition, several features can be enabled using the MRS command. These are the DLL, Drive
Impedance Matching, and On-Die Termination (ODT). tMRSC must be met before any command can be issued. tMRSC is measured like
the picture above in both Multiplexed and Non-multiplexed mode.
Mode Register Diagram (Non-multiplexed Address Mode)
Address
A9
Mode Register
Field
0
1
1
A10-17 M10-17
0
A9
M9
ODT
A8
M8
IM
A7
M7
DLL
A6
M6
NA2
A5
M5
AM
A4
M4
A3
M3
A2
M2
A1
M1
A0
M0
BL
A2
0
0
0
0
1
1
1
1
A1
0
0
1
1
0
0
1
1
A0
0
1
0
1
0
1
0
1
A8
0
1
Drive Impedance
Internal 50Ω 5 (Default)
External(ZQ)
A7
0
1
DLL Reset
DLL reset4 (Default)
DLL enable
A5
0
1
Address MUX
Non-multiplexed (Default)
Multiplexed
A4
0
0
1
1
Config
On-Die Termination
Off (Default)
On
A3
0
1
0
1
Burst Length(BL)
2
4
8
Reserved
Read/Write Latency and Cycle Time Configuration6
Configuration
tRC(tCK)
tRL(tCK)
tWL(tCK)
3
4
4
5
1 (Default)
3
4
4
5
1
2
6
6
7
3
8
8
9
3
3
4
4 3,7
5
5
5
6
Reserved
n/a
n/a
n/a
Reserved
n/a
n/a
n/a
Valid Frequency Range
(MHz)
266-175
266-175
400-175
533-1758
200-175
333-175
n/a
n/a
Notes:
1. A10-A17 must be set to zero; A18-An are "Don't cares."
2. A6 not used in MRS.
3. BL = 8 is not available.
4. DLL RESET turns the DLL off.
5. ±30 % temperature variation.
6. tRC < 20ns in any configuration is only available with -25E speed grade.
7. The minimum tRC is typically 3 cycles, except in the case of a WRITE followed by a READ to the same bank. In this instance the minimum tRC is 4 cycles.
8. tCK must be met to use this configuration. For tCK values, please refer to AC Electrical Characteristics table.
Mode Register Diagram (Multiplexed Address Mode)
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IS49NLS96400,IS49NLS18320
Ax
Ay
Mode Register
A10-18 A10-18 M10-18
01
A9
M9
ODT
A8
M8
IM
A9
M7
DLL
A8
M6
NA5
A5
M5
AM
A4
M4
A3
M3
BL
A4
M2
A3
M1
A0
A9
0
1
On-Die Termination
Off (Default)
On
A8
0
1
Drive Impedance
Internal 50Ω 6 (Default)
External(ZQ)
A7
0
1
DLL Reset
DLL reset4 (Default)
DLL enable
A5
0
1
Address MUX
Non-multiplexed (Default)
Multiplexed
A4
0
0
1
1
Config
A3
0
1
0
1
Burst Length(BL)
2 (Default)
4
8
Reserved
M0
Ay4
0
0
0
0
1
1
1
1
Ay3
0
0
1
1
0
0
1
1
Ax0
0
1
0
1
0
1
0
1
Read/Write Latency and Cycle Time Configuration8
Configuration
tRC(tCK)
tRL(tCK)
tWL(tCK)
2
4
5
6
1 (Default)
2
4
5
6
1
2
6
7
8
3
8
9
10
3
4
5
4 2,9
5
5
6
7
Reserved
n/a
n/a
n/a
Reserved
n/a
n/a
n/a
Valid Frequency
Range (MHz)
266-175
266-175
400-175
533-17510
200-175
333-175
n/a
n/a
Notes:
1. A10-A18 must be set to zero; A18-An are "Don't cares."
2. BL = 8 is not available.
3. ±30 % temperature variation.
4. DLL RESET turns the DLL off.
5. Ay = 8 is not used in MRS.
6. BA0-BA2 are "Don't care."
7. Addresses A0, A3, A4, A5, A8, and A9 must be set as shown in order to activate the mode register in the multiplexed address mode.
8. tRC< 20ns in any configuration is only available with -25E speed grade.
9. The minimum tRC is typically 3 cycles, except in the case of a WRITE followed by a READ to the same bank. In this instance the minimum tRC is 4 cycles.
10. tCK must be met to use this configuration. For tCK values, please refer to AC Electrical Characteristics table.
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3.5 Mode Register Bit Description
Configuration
The cycle time and read/write latency can be configured from the different options shown in the Mode Register Diagram. In order to
maximize data bus utilization, the WRITE latency is equal to READ latency plus one. The read and write latencies are increased by
one clock cycle during multiplexed address mode compared to non-multiplexed mode.
Burst Length
The burst length of the read and write accesses to memory can be selected from three different options: 2, 4, and 8. Changes in the
burst length affect the width of the address bus and is shown in the Burst Length and Address Width Table. The data written during a
prior burst length setting is not guaranteed to be accurate when the burst length of the device is changed.
Burst Length and Address Width Table
Burst Length
576Mb Address Bus
x9
x18
2
4
A0-A21
A0-A20
A0-A20
A0-A19
8
A0-A19
A0-A18
DLL Reset
The default setting for this option is LOW, whereby the DLL is disabled. Once the mode register for this feature is set HIGH, 1024
cycles (5μs at 200 MHz) are needed before a READ command can be issued. This time allows the internal clock to be synchronized
with the external clock. Failing to wait for synchronization to occur may result in a violation of the tCKQK parameter. A reset of the DLL
is necessary if tCK or VDD is changed after the DLL has already been enabled. To reset the DLL, an MRS command must be issued
where the DLL Reset Mode Register is set LOW. After waiting tMRSC, a subsequent MRS command should be issued whereby the DLL
Reset Mode Register is set HIGH. 1024 clock cycles are then needed before a READ command is issued.
Drive Impedance Matching
The RLDRAM 2 Memory is equipped with programmable impedance output buffers. The purpose of the programmable impedance
output buffers is to allow the user to match the driver impedance to the system. To adjust the impedance, an external precision
resistor (RQ) is connected between the ZQ ball and VSS. The value of the resistor must be five times the desired impedance. For
example, a 300Ω resistor is required for an output impedance of 60Ω. The range of RQ is 125–300Ω, which guarantees output
impedance in the range of 25–60Ω (within 15 percent). Output impedance updates may be required because over time variations
may occur in supply voltage and temperature. When the external drive impedance is enabled in the MRS, the device will periodically
sample the value of RQ. An impedance update is transparent to the system and does not affect device operation. All data sheet
timing and current specifications are met during an update. When the Drive Impedance Mode Register is set LOW during the MRS
command, the memory provides an internal impedance at the output buffer of 50Ω (±30% with temperature variation). This
impedance is also periodically sampled and adjusted to compensate for variation in supply voltage and temperature.
Address Multiplexing
Although the RLDRAM 2 Memory is capable of accepting all the addresses in a single rising clock edge, this memory can be
programmed to operate in multiplexed address mode, which is very similar to a traditional DRAM. In multiplexed address mode, the
address can be sent to the memory in two parts within two consecutive rising clock edges. This minimizes the number of address
signal connections between the controller and the memory by reducing the address bus to a maximum of only 11 lines. Since the
memory requires two clock cycles to read and write the data, data bus efficiency is affected when operating in continuous burst
mode with a burst length of 2 setting. Bank addresses are provided to the memory at the same time as the WRITE and READ
commands together with the first address part, Ax. The second address part, Ay, is then issued to the memory on the next rising
clock edge. AREF commands only require the bank address. Since AREF commands do not need a second consecutive clock for
address latching, they may be issued on consecutive clocks.
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Address Mapping in Multiplexed Address Mode
Data Width
Burst Length
2
X9
4
8
2
X18
4
8
Address
Ball
A0
A3
A4
A5
A8
A9
A10
A13
A14
A17
A18
Ax
Ay
Ax
Ay
Ax
Ay
A0
A20
A0
A20
A0
X
A3
A1
A3
A1
A3
A1
A4
A2
A4
A2
A4
A2
A5
A21
A5
X
A5
X
A8
A6
A8
A6
A8
A6
A9
A7
A9
A7
A9
A7
A10
A19
A10
A19
A10
A19
A13
A11
A13
A11
A13
A11
A14
A12
A14
A12
A14
A12
A17
A16
A17
A16
A17
A16
A18
A15
A18
A15
A18
A15
Ax
Ay
Ax
Ay
Ax
A0
A20
A0
X
A0
A3
A1
A3
A1
A3
A4
A2
A4
A2
A4
A5
X
A5
X
A5
A8
A6
A8
A6
A8
A9
A7
A9
A7
A9
A10
A19
A10
A19
A10
A13
A11
A13
A11
A13
A14
A12
A14
A12
A14
A17
A16
A17
A16
A17
A18
A15
A18
A15
A18
Ay
X
A1
A2
X
A6
A7
X
A11
A12
A16
A15
Note: X = Don’t Care.
On-Die Termination (ODT)
If the ODT is enabled, the Ds, Qs and DM are terminated to VTT with a resistance RTT. The command, address, QVLD, and clock signals
are not terminated. Figure 3.1 shows the equivalent circuit of a D receiver with ODT. The ODT function is dynamically switched off
when a Q begins to drive after a READ command is issued. Similarly, ODT is designed to switch on at the Qs after the memory has
issued the last piece of data. The D and DM pins will always be terminated.
ODT DC Parameters Table
Description
Symbol
Min
Max
Units
Notes
Termination Voltage
VTT
0.95 x VREF
1.05 x VREF
V
1, 2
On-die termination
RTT
125
185
Ω
3
Notes:
1. All voltages referenced to VSS (GND).
2. VTT is expected to be set equal to VREF and must track variations in the DC level of VREF.
3. The RTT value is measured at 95°C TC.
VTT
Switch
RTT
Receiver
D
Figure 3.1 ODT Equivalent Circuit
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3.6 Deselect/No Operation (DESL/NOP)
The Deselect command is used to prevent unwanted operations from being performed in the memory device during wait or idle
states. Operations already registered to the memory prior to the assertion of the Deselect command will not be cancelled.
3.7 Read Operation (READ)
The Read command performs burst-oriented data read accesses in a bank of the memory device. The Read command is initiated by
registering the WE# and REF# signals logic HIGH while the CS# is in logic LOW state. In non-multiplexed address mode, both an
address and a bank address must be provided to the memory during the assertion of the Read command. In multiplexed mode, the
bank address and the first part of the address, Ax, must be supplied together with the Read command. The second part of the
address, Ay, must be latched to the memory on the subsequent rising edge of the CK clock. Data being accessed will be available in
the data bus a certain amount of clock cycles later depending on the Read Latency Configuration setting.
Data driven in the Q signals are edge-aligned to the free-running output data clocks QKx and QKx#. A half clock cycle before the read
data is available on the data bus, the data valid signal, QVLD, will transition from logic LOW to HIGH. The QVLD signal is also edgealigned to the data clock QKx and QKx#.
If no other commands have been registered to the device when the burst read operation is finished, the Q signals will go to High-Z
state. The QVLD signal transition from logic HIGH to logic LOW on the last bit of the READ burst. Please note that if CK/CK# violates
the VID (DC) specification while a READ burst is occurring, QVLD will remain HIGH until a dummy READ command is registered. The
QK clocks are free-running and will continue to cycle after the read burst is complete. Back-to-back READ commands are permitted
which allows for a continuous flow of output data.
CK#
Non-Multiplexed
Mode
CK#
CK
CK
CS#
CS#
WE#
WE#
REF#
REF#
Multiplexed
Mode
ADDRESS
A
ADDRESS
Ax
BANK
ADDRESS
BA*
BANK
ADDRESS
BA*
Ay
Don’t care
Read Command
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0
tCKH
1
2
3
4
5
6
RD
RD
NOP
NOP
NOP
NOP
NOP
BA2, A2
BA3, A3
tCKL
tCK
CK#
CK
Command
Address
Read Latency = 4
tQKVLD
QVLD
tQKVLD
tQKQ
Q
Q2-1
tCKQK
tQKH
tQKQ
Q2-2
Q3-1
Q3-2
tQKL
QKx#
QKx
Don’t Care
Undefined
Basic Read Burst with QVLD: BL=2 & RL=4
Notes:
1. Minimum READ data valid window can be expressed as MIN(tQKH, tQKL) – 2 x MAX(tQKQx).
2. tCKH and tCKL are recommended to have 50% / 50% duty.
3. tQKQ0 is referenced to Q0–Q8 and tQKQ1 is referenced to Q9–Q17 in x18.
4. tQKQ takes into account the skew between any QKx and any Q.
5. tCKQK is specified as CK rising edge to QK rising edge.
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0
1
2
3
4
5
6
7
8
RD
WR
RD
NOP
NOP
NOP
NOP
NOP
NOP
BA2, A2
BA3, A3
CK#
CK
Command
Address BA1, A1
Write Latency = 5
Read Latency = 4
DK#
DK
D
D2-1
Q
Q1-1
Q1-2
Q1-3
Q1-4
D2-2
Q3-1
D2-3
Q3-2
D2-4
Q3-3
Q3-4
QVLD
QK#
QK
Don’t care
Undefined
Read Followed by Write: BL = 4, RL =4 & WL = 5, Configuration 1
3.8 Write Operation (WRITE)
The Write command performs burst-oriented data write accesses in a bank of the memory device. The Write command is initiated
by registering the REF# signal logic HIGH while the CS# and WE# signals are in logic LOW state. In non-multiplexed address mode,
both an address and a bank address must be provided to the memory during the assertion of the Write command. In multiplexed
mode, the bank address and the first part of the address, Ax, must be supplied together with the Write command. The second part
of the address, Ay, must be latched to the memory on the subsequent rising edge of the CK clock. Input data to be written to the
device can be registered several clock cycles later depending on the Write Latency Configuration setting. The write latency is always
one cycle longer than the programmed read latency. The DM signal can mask the input data by setting this signal logic HIGH.
At least one NOP command in between a Read and Write commands is required in order to avoid data bus contention. The setup
and hold times for DM and data signals are tDS and tDH, which are referenced to the DK clocks.
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CK#
Non-Multiplexed
Mode
CK#
CK
CK
CS#
CS#
WE#
WE#
REF#
REF#
Multiplexed
Mode
ADDRESS
A
ADDRESS
Ax
BANK
ADDRESS
BA*
BANK
ADDRESS
BA*
Ay
Don’t care
Write Command
0
1
2
3
4
5
6
7
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CK#
CK
tCKDK
DKx#
DKx
Command
Address
WR
BA1, A1
Write Latency = 5
DM
tDS tDH
D1-0
D
Masked Data
D1-2
D1-3
Don’t Care
D1-4
Undefined
Basic WRITE Burst with DM Timing: BL=4 & WL=5
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0
1
2
3
4
5
6
7
8
9
WR
WR
RD
RD
NOP
NOP
NOP
NOP
NOP
NOP
BA1,A1
BA2,A2
BA3, A3
BA4, A4
CK#
CK
Command
Address
Read Latency = 4
Read Latency = 4
Write Latency = 5
Write Latency = 5
DKx
DKx#
D
D1-1
D1-2
Q
D2-1
D2-2
Q3-1
Q3-2
Q4-1
Q4-2
QVLD
QKx
QKx#
Don’t Care
Undefined
Write Followed by Read: BL=2, RL=4 & WL=5, Configuration 1
3.9 Auto Refresh Command (AREF)
The Auto Refresh command performs a refresh cycle on one row of a specific bank of the memory. Only bank addresses are required
together with the control the pins. Therefore, Auto Refresh commands can be issued on subsequent CK clock cycles on both
multiplexed and non-multiplexed address mode. Any command following an Auto Refresh command must meet a t RC timing delay or
later.
CK#
CK
CS#
WE#
REF#
ADDRESS
BANK
ADDRESS
BA*
Don’t care
Auto Refresh Command
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0
tCKH
tCKL
2
1
3
4
5
6
NOP
NOP
ANYCOMx
ANYCOMy
BAx
BAy
tCK
CK#
CK
QKx#
QKx
Command
tRC
AREFx
AREFy
NOP
tRC
Bank Address
BAx
BAy
Don’t Care
AREF example in tRC(tCK)=5 option: Configuration=5
Command Truth Table
Operation
Code
CS#
WE#
REF#
Ax
BAx
Device DESELECT/No Operation
Mode Register Set
Read
Write
Auto Refresh
DESL/NOP
MRS
READ
WRITE
AREF
H
L
L
L
L
X
L
H
L
H
X
L
H
H
L
X
OPCODE
A
A
X
X
X
BA
BA
BA
Notes:
1. X = "Don't Care;" H = logic HIGH; L = logic LOW; A = Valid Address; BA = Valid Bank Address.
2. During MRS, only address inputs A0-A17 are used.
3. Address width changes with burst length.
4. All input states or sequences not shown are illegal or reserved.
5. All command and address inputs must meet setup and hold times around the rising edge of CK.
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3.11 On-Die Termination (ODT) Timing examples.
Read Operation with ODT: RL=4, BL=4
0
1
2
3
4
5
6
RD
NOP
NOP
NOP
NOP
NOP
NOP
7
CK#
CK
Command
Address
NOP
BA2, A2
Read Latency = 4
tQKVLD
tQKVLD
QVLD
Q ODT
Q ODT on
Q ODT Off
Q ODT on
Q
Q2-0
Q2-1
Q2-2
Q2-3
QKx#
QKx
Undefined
Don’t Care
Read to Write with ODT: RL=4, BL=2
0
1
2
3
RD
WR
NOP
NOP
BA2, A2
BA1, A1
4
5
6
NOP
NOP
NOP
7
CK#
CK
Command
Address
NOP
Read Latency = 4
DKx#
DKx
Write Latency = 5
D
D1-0
tQKVLD
D1-1
tQKVLD
QVLD
Q ODT
Q ODT on
Q
Q ODT Off
Q2-0
Q ODT on
Q2-1
QKx#
QKx
Don’t Care
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4 IEEE 1149.1 TAP and Boundary Scan
RLDRAM 2 Memory devices have a serial boundary-scan test access port (TAP) that allow the use of a limited set of JTAG
instructions to test the interconnection between the memory I/Os and printed circuit board traces or other components. In
conformance with IEEE Standard 1149.1, the memory contains a TAP controller, instruction register, boundary scan register, bypass
register, and ID register. The TAP operates in accordance with IEEE Standard 1149.1-2001 (JTAG) with the exception of the ZQ pin. To
guarantee proper boundary-scan testing of the ZQ pin, MRS bit M8 needs to be set to 0 until the JTAG testing of the pin is complete.
Note that on power up, the default state of MRS bit M8 is logic LOW. The TAP is compliant with IEEE 1149.1-2013 as far as all
mandatory features (BYPASS, EXTEST, PRELOAD, and SAMPLE), and several optional features (CLAMP, HIGHZ, IDCODE, ECIDCODE).
If the memory boundary scan register is to be used upon power up and prior to the initialization of the memory device, the CK and
CK# pins meet VID(DC) or CS# be held HIGH from power up until testing. Not doing so could result in inadvertent MRS commands to
be loaded, and subsequently cause unexpected results from address pins that are dependent upon the state of the mode register. If
these measures cannot be taken, the part must be initialized prior to boundary scan testing. If a full initialization is not practical or
feasible prior to boundary scan testing, a single MRS command with desired settings may be issued instead. After the single MRS
command is issued, the tMRSC parameter must be satisfied prior to boundary scan testing.
4.1 Disabling the JTAG feature
The RLDRAM 2 Memory can operate without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (V SS) to
prevent clocking of the device. TDI and TMS are internally pulled up and may be left disconnected. They may alternately be
connected to VDD through a pull-up resistor. TDO should be left disconnected. On power-up, the device will come up in a reset state,
which will not interfere with device operation.
4.2 Test Access Port Signal List:
Test Clock (TCK)
This signal uses VDD as a power supply. The test clock is used only with the TAP controller. All inputs are captured on the rising edge
of TCK. All outputs are driven from the falling edge of TCK.
Test Mode Select (TMS)
This signal uses VDD as a power supply. The TMS input is used to send commands to the TAP controller and is sampled on the rising
edge of TCK.
Test Data-In (TDI)
This signal uses VDD as a power supply. The TDI input is used to serially input test instructions and information into the registers and
can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded
into the TAP instruction register. TDI is connected to the most significant bit (MSB) of any register. For more information regarding
instruction register loading, please see the TAP Controller State Diagram.
Test Data-Out (TDO)
This signal uses VDDQ as a power supply. The TDO output ball is used to serially clock test instructions and data out from the registers.
The TDO output driver is only active during the Shift-IR and Shift-DR TAP controller states. In all other states, the TDO pin is in a HighZ state. The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register. For more
information, please see the TAP Controller State Diagram.
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4.3 TAP Controller State and Block Diagram
1
Test Logic Reset
0
1
1
Run Test Idle
1
Select DR
0
Select IR
0
0
1
1
Capture DR
Capture IR
0
0
Shift DR
0
Shift IR
1
0
1
1
1
Exit1 DR
Exit1 IR
0
0
Pause DR
0
Pause IR
1
0
1
Exit2 DR
Exit2 IR
0
0
1
1
1
Update DR
0
Update IR
1
0
Note1
TDI
Bypass Register (1 bit)
Identification Register (32 bits)
TDO
Instruction Register (8 bits)
Control Signals
TMS
TAP Controller
TCK
Note: 113 boundary scan registers in RLDRAM 2 Memory
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4.4 Performing a TAP Reset
A Reset is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. RESET may be performed while the SRAM is operating
and does not affect its operation. At power-up, the TAP is internally reset to ensure that TDO comes up in a high-Z state.
4.5 TAP Registers
Registers are connected between the TDI and TDO pins and allow data to be scanned into and out of the SRAM test circuitry. Only
one register can be selected at a time through the instruction registers. Data is serially loaded into the TDI pin on the rising edge of
TCK and output on the TDO pin on the falling edge of TCK.
Instruction Register
This register is loaded during the update-IR state of the TAP controller. At power-up, the instruction register is loaded with the
IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the
previous section. When the TAP controller is in the capture-IR state, the two LSBs are loaded with a binary “01” pattern to allow for
fault isolation of the board-level serial test data path.
Bypass Register
The bypass register is a single-bit register that can be placed between the TDI and TDO balls. This allows data to be shifted through
the memory device with minimal delay. The bypass register is set LOW (VSS) when the BYPASS instruction is executed.
Boundary Scan Register
The boundary scan register is connected to all the input and bidirectional balls on the device. Several balls are also included in the
scan register to reserved balls. The boundary scan register is loaded with the contents of the memory Input and Output ring when
the TAP controller is in the capture-DR state and is then placed between the TDI and TDO balls when the controller is moved to the
shift-DR state. Each bit corresponds to one of the balls on the device package. The MSB of the register is connected to TDI, and the
LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code during the capture-DR state when the IDCODE command is loaded in the
instruction register. The IDCODE is hardwired into the device and can be shifted out when the TAP controller is in the shift-DR state.
4.6 Scan Register Sizes
Register Name
Bit Size
Instruction Register
8
Bypass Register
1
Boundary Scan Register
113
Identification (ID) Register
32
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4.7 TAP Instruction Set
Many instructions are possible with an eight-bit instruction register and all valid combinations are listed in the TAP Instruction Code
Table. All other instruction codes that are not listed on this table are reserved and should not be used. Instructions are loaded into
the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state,
instructions are shifted from the instruction register through the TDI and TDO pins. To execute an instruction once it is shifted in, the
TAP controller must be moved into the Update-IR state.
EXTEST
The EXTEST instruction allows circuitry external to the component package to be tested. Boundary-scan register cells at output balls
are used to apply a test vector, while those at input balls capture test results. Typically, the first test vector to be applied using the
EXTEST instruction will be shifted into the boundary scan register using the PRELOAD instruction. Thus, during the update-IR state of
EXTEST, the output driver is turned on, and the PRELOAD data is driven onto the output balls.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the identification register. It also places the
identification register between the TDI and TDO balls and allows the IDCODE to be shifted out of the device when the TAP controller
enters the shift-DR state. The IDCODE instruction is loaded into the instruction register upon power-up or whenever the TAP
controller is given a test logic reset state.
High-Z
The High-Z instruction causes the bypass register to be connected between the TDI and TDO. This places all RLDRAM 2 Memory
outputs into a High-Z state.
CLAMP
When the CLAMP instruction is loaded into the instruction register, the data driven by the output balls are determined from the
values held in the boundary scan register.
SAMPLE/PRELOAD
When the SAMPLE/PRELOAD instruction is loaded into the instruction register and the TAP controller is in the capture-DR state, a
snapshot of data on the inputs and bidirectional balls is captured in the boundary scan register. The user must be aware that the TAP
controller clock can only operate at a frequency up to 50 MHz, while the memory clock operates significantly faster. Because there is
a large difference between the clock frequencies, it is possible that during the capture-DR state, an input or output will undergo a
transition. The TAP may then try to capture a signal while in transition (metastable state). This will not harm the device, but there is
no guarantee as to the value that will be captured. Repeatable results may not be possible. To ensure that the boundary scan
register will capture the correct value of a signal, the memory signal must be stabilized long enough to meet the TAP controller’s
capture setup plus hold time (tCS plus tCH). The memory clock input might not be captured correctly if there is no way in a design to
stop (or slow) the clock during a SAMPLE/ PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and
simply ignore the value of the CK and CK# captured in the boundary scan register. Once the data is captured, it is possible to shift out
the data by putting the TAP into the shift-DR state. This places the boundary scan register between the TDI and TDO balls.
BYPASS
When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a shift-DR state, the bypass register is
placed between TDI and TDO. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple
devices are connected together on a board.
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4.8 TAP DC Electrical Characteristics and Operating Conditions
(+0°C ≤ TC ≤ +95°C; +1.7V ≤ VDD ≤ +1.9V, unless otherwise noted)
Description
Symbol
Min
Max
Units
Notes
Input high (logic 1) voltage
VIH
VREF + 0.15
VDDQ + 0.3
V
1, 2
Input low (logic 0) voltage
VIL
VSSQ 0.3
VREF 0.15
V
1, 2
0V ≤ VIN ≤ VDD
ILI
5
µA
Output Disabled,
0V ≤ VIN ≤ VDDQ
ILO
5
µA
Output low voltage
IOLC =100 µA
VOL1
-
0.2
V
1
Output low voltage
IOLT = 2mA
VOL2
-
0.4
V
1
Output high voltage
|IOHC| =100 µA
VOH1
VDDQ - 0.2
-
V
1
Output high voltage
|IOHT | = 2mA
VOH2
VDDQ - 0.4
-
V
1
Input leakage current
Output leakage current
Conditions
Notes:
1. All voltages referenced to VSS (GND).
2. Overshoot = VIH(AC) ≤ VDD + 0.7V for t ≤ tCK/2; undershoot = VIL(AC) ≥ –0.5V for t ≤ tCK/2; during normal operation, VDDQ must not exceed VDD.
4.9 TAP AC Electrical Characteristics and Operating Conditions
(+0°C ≤ TC ≤ +95°C; +1.7V ≤ VDD ≤ +1.9V)
Description
Symbol
Min
tTHTH
fTF
tTHTL
tTLTH
20
Max
Units
Clock
Clock Cycle Time
Clock Frequency
Clock HIGH Time
Clock LOW Time
ns
50
MHz
10
ns
10
ns
tTLOX
tTLOV
tDVTH
tTHDX
0
ns
TDI/TDO times
TCK LOW to TDO unknown
TCK LOW to TDO valid
TDI valid to TCK High
TCK HIGH to TDI invalid
10
ns
5
ns
5
ns
tMVTH
tCS
5
ns
5
ns
tTMHX
tCH
5
ns
5
ns
Setup times
TMS Setup
Capture Setup
Hold Times
TMS hold
Capture hold
Note: tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register.
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4.10 TAP Timing
0
1
tTHTL
2
tTLTH
3
4
5
6
7
tTHTH
Test Mode
Clock (CK)
tMVTH
tTHMX
Test Mode
Select (TMS)
tDVTH
tTHDX
Test Data-In
(TDI)
tTLOV
tTLOX
Test Data-Out
(TDO)
Don’t Care
Undefined
4.11 TAP Instruction Codes
Instruction
Code
EXTEST
0000 0000
IDCODE
0010 0001
SAMPLE/PRELOAD
0000 0101
CLAMP
0000 0111
High-Z
0000 0011
BYPASS
1111 1111
Description
Captures Input and Output ring contents. Places the boundary scan register
between TDI and TDO. This operation does not affect device operations
Loads the ID register with the vendor ID code and places the register between TDI
and TDO; This operation does not affect device operations
Captures I/O ring contents; Places the boundary scan register between TDI and TDO
Selects the bypass register to be connected between TDI and TDO; Data driven by
output balls are determined from values held in the boundary scan register
Selects the bypass register to be connected between TDI and TDO; All outputs are
forced into High-Z
Places the bypass register between TDI and TDO; This operation does not affect
device operations
Note: All other remaining instruction codes not mentioned in the above table are reserved and should not be used.
4.12 Identification (ID) Register Definition
Instruction Field
All Devices
Revision number (31:28)
abcd
Device ID (27:12)
00jkidef10100111
Vendor ID code (11:1)
ID register presence indicator (0)
000 1101 0101
1
Description
ab = die revision
cd = 00 for x9, 01 for x18, 10 for x36
def = 000 for 288Mb, 001 for 576Mb
i = 0 for common I/O, 1 for separate I/O
jk = 01 for RLDRAM 2 Memory
Allows unique identification of vendor
Indicates the presence of an ID register
4.13 TAP Input AC Logic Levels
(+0°C ≤ TC ≤ +95°C; +1.7V ≤ VDD ≤ +1.9V, unless otherwise noted)
Description
Input high (logic 1) voltage
Input low (logic 0) voltage
Symbol
VIH
VIL
Min
VREF + 0.3
-
Max
VREF - 0.3
Units
V
V
Note: All voltages referenced to VSS (GND).
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4.14 Boundary Scan Order
Bit#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
Signal name Bump
x9
x18
ID
DK
DK
K1
DK#
DK#
K2
CS#
CS#
L2
REF# REF#
L1
WE# WE#
M1
A17
A17
M3
A16
A16
M2
A18
A18
N1
A15
A15
P1
DNU
Q14
N3
DNU
Q14
N3
DNU
D14
N2
DNU
D14
N2
DNU
Q15
P3
DNU
Q15
P3
DNU
D15
P2
DNU
D15
P2
DNU
QK1
R2
DNU QK1#
R3
DNU
D16
T2
DNU
D16
T2
DNU
Q16
T3
DNU
Q16
T3
DNU
D17
U2
DNU
D17
U2
DNU
Q17
U3
DNU
Q17
U3
ZQ
ZQ
V2
Q8
Q13
U10
Q8
Q13
U10
D8
D13
U11
D8
D13
U11
Q7
Q12
T10
Q7
Q12
T10
D7
D12
T11
D7
D12
T11
Q6
Q11
R10
Q6
Q11
R10
Bit#
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
Signal name Bump
x9
x18
ID
D6
D11
R11
D6
D11
R11
D5
D10
P11
D5
D10
P11
Q5
Q10
P10
Q5
Q10
P10
D4
D9
N11
D4
D9
N11
Q4
Q9
N10
Q4
Q9
N10
DM
DM
P12
A19
A19
N12
A11
A11
M11
A12
A12
M10
A10
A10
M12
A13
A13
L12
A14
A14
L11
BA1
BA1
K11
CK#
CK#
K12
CK
CK
J12
BA0
BA0
J11
A4
A4
H11
A3
A3
H12
A0
A0
G12
A2
A2
G10
A1
A1
G11
A20
A20
E12
QVLD QVLD
F12
Q3
Q3
F10
Q3
Q3
F10
D3
D3
F11
D3
D3
F11
Q2
Q2
E10
Q2
Q2
E10
D2
D2
E11
D2
D2
E11
QK0
QK0
D11
QK0# QK0# D10
Integrated Silicon Solution, Inc. – www.issi.com –
Rev. B, 01/22/2020
Bit#
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
Signal name Bump
x9
x18
ID
D1
D1
C11
D1
D1
C11
Q1
Q1
C10
Q1
Q1
C10
D0
D0
B11
D0
D0
B11
Q0
Q0
B10
Q0
Q0
B10
DNU
Q4
B3
DNU
Q4
B3
DNU
D4
B2
DNU
D4
B2
DNU
Q5
C3
DNU
Q5
C3
DNU
D5
C2
DNU
D5
C2
DNU
Q6
D3
DNU
Q6
D3
DNU
D6
D2
DNU
D6
D2
DNU
D7
E2
DNU
D7
E2
DNU
Q7
E3
DNU
Q7
E3
DNU
D8
F2
DNU
D8
F2
DNU
Q8
F3
DNU
Q8
F3
A21 (A21)
E1
A5
A5
F1
A6
A6
G2
A7
A7
G3
A8
A8
G1
BA2
BA2
H1
A9
A9
H2
NF
NF
J2
NF
NF
J1
31
IS49NLS96400,IS49NLS18320
ORDERING INFORMATION
Commercial Range: TC = 0° to +95°C; TA = 0°C to +70°C
Frequency
Speed
Order Part No.
Organization
Package
400 MHz
IS49NLS96400-25EWB
64M x 9
144 WBGA, Lead-free
IS49NLS18320-25EWBL
32M x 18
144 WBGA, Lead-free
IS49NLS96400-25WB
64M x 9
144 WBGA, Lead-free
IS49NLS18320-25WBL
32M x 18
144 WBGA, Lead-free
IS49NLS96400-33WB
64M x 9
144 WBGA, Lead-free
IS49NLS18320-33WBL
32M x 18
144 WBGA, Lead-free
Industrial Range: TC = 40°C to 95°C; T A = 40°C to +85°C
Frequency
Speed
Order Part No.
Organization
Package
400 MHz
IS49NLS96400-25EWBI
64M x 9
144 WBGA, Lead-free
IS49NLS18320-25EWBLI
32M x 18
144 WBGA, Lead-free
IS49NLS96400-25WBI
64M x 9
144 WBGA, Lead-free
IS49NLS18320-25WBLI
32M x 18
144 WBGA, Lead-free
IS49NLS96400-33WBI
64M x 9
144 WBGA, Lead-free
IS49NLS18320-33WBLI
32M x 18
144 WBGA, Lead-free
400 MHz
300 MHz
400 MHz
300 MHz
2.5ns (tRC=15ns)
2.5ns (tRC=20ns)
3.3ns (tRC=20ns)
2.5ns (tRC=15ns)
2.5ns (tRC=20ns)
3.3ns (tRC=20ns)
Integrated Silicon Solution, Inc. – www.issi.com –
Rev. B, 01/22/2020
32
IS49NLS96400,IS49NLS18320
Ball Grid Array
Package Code: WB (144-ball WBGA)
Integrated Silicon Solution, Inc. – www.issi.com –
Rev. B, 01/22/2020
33
工商网监
湘ICP备2023018690号
