0
登录后你可以
  • 下载海量资料
  • 学习在线课程
  • 观看技术视频
  • 写文章/发帖/加入社区
会员中心
创作中心
发布
  • 发文章

  • 发资料

  • 发帖

  • 提问

  • 发视频

创作活动
IS61C1024-20J

IS61C1024-20J

  • 厂商:

    ISSI(芯成半导体)

  • 封装:

  • 描述:

    IS61C1024-20J - 128K x 8 HIGH-SPEED CMOS STATIC RAM - Integrated Silicon Solution, Inc

  • 数据手册
  • 价格&库存
IS61C1024-20J 数据手册
IS61C1024 IS61C1024L 128K x 8 HIGH-SPEED CMOS STATIC RAM FEATURES • High-speed access time: 12, 15, 20, 25 ns • Low active power: 600 mW (typical) • Low standby power: 500 µW (typical) CMOS standby • Output Enable (OE) and two Chip Enable (CE1 and CE2) inputs for ease in applications • Fully static operation: no clock or refresh required • TTL compatible inputs and outputs • Single 5V (±10%) power supply • Low power version available: IS61C1024L • Commercial and industrial temperature ranges available ISSI MAY 1999 ® DESCRIPTION The ISSI IS61C1024 and IS61C1024L are very high-speed, low power, 131,072-word by 8-bit CMOS static RAMs. They are fabricated using I SSI 's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields higher performance and low power consumption devices. When CE1 is HIGH or CE2 is LOW (deselected), the device assumes a standby mode at which the power dissipation can be reduced by using CMOS input levels. Easy memory expansion is provided by using two Chip Enable inputs, CE1 and CE2. The active LOW Write Enable (WE) controls both writing and reading of the memory. The IS61C1024 and IS61C1024L are available in 32-pin 300-mil SOJ, and TSOP (Type I, 8x20), and sTSOP (Type I, 8 x 13.4) packages. FUNCTIONAL BLOCK DIAGRAM A0-A16 DECODER 512 x 2048 MEMORY ARRAY VCC GND I/O DATA CIRCUIT I/O0-I/O7 COLUMN I/O CE1 CE2 OE WE CONTROL CIRCUIT ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 1999, Integrated Silicon Solution, Inc. 4 SR028-1K 05/12/99 1 IS61C1024 IS61C1024L PIN CONFIGURATION 32-Pin SOJ NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 CE2 WE A13 A8 A9 A11 OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 ISSI PIN CONFIGURATION 32-Pin TSOP (Type 1) (T) and sTSOP (Type 1) (H) A11 A9 A8 A13 WE CE2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3 ® PIN DESCRIPTIONS A0-A16 Address Inputs Chip Enable 1 Input Chip Enable 2 Input Output Enable Input Write Enable Input Input/Output Power Ground CE1 CE2 OE WE I/O0-I/O7 Vcc GND OPERATING RANGE Range Commercial Industrial Ambient Temperature 0°C to +70°C –40°C to +85°C VCC 5V ± 10% 5V ± 10% TRUTH TABLE Mode Not Selected (Power-down) Output Disabled Read Write WE X X H H L CE1 H X L L L CE2 X L H H H OE X X H L X I/O Operation High-Z High-Z High-Z DOUT DIN Vcc Current ISB1, ISB2 ISB1, ISB2 ICC1, ICC2 ICC1, ICC2 ICC1, ICC2 2 SR028-1J 11/03/98 IS61C1024 IS61C1024L ABSOLUTE MAXIMUM RATINGS(1) Symbol VTERM TBIAS TSTG PT IOUT Parameter Terminal Voltage with Respect to GND Temperature Under Bias Storage Temperature Power Dissipation DC Output Current (LOW) Value –0.5 to +7.0 –55 to +125 –65 to +150 1.5 20 Unit V °C °C W mA ISSI ® Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. CAPACITANCE(1,2) Symbol CIN COUT Parameter Input Capacitance Output Capacitance Conditions VIN = 0V VOUT = 0V Max. 5 7 Unit pF pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25°C, f = 1 MHz, Vcc = 5.0V. DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Symbol Parameter VOH VOL VIH VIL ILI ILO Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Output Leakage (1) Test Conditions VCC = Min., IOH = –4.0 mA VCC = Min., IOL = 8.0 mA Min. 2.4 — 2.2 –0.3 Max. — 0.4 VCC + 0.5 0.8 2 5 2 5 Unit V V V V µA µA GND ≤ VIN ≤ VCC GND ≤ VOUT ≤ VCC Outputs Disabled Com. Ind. Com. Ind. –2 –5 –2 –5 Note: 1. VIL = –3.0V for pulse width less than 10 ns. 4 SR028-1K 05/12/99 3 IS61C1024 IS61C1024L IS61C1024 POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter ICC1 ICC2 ISB1 Vcc Operating Supply Current Vcc Dynamic Operating Supply Current TTL Standby Current (TTL Inputs) Test Conditions VCC = VCC MAX., CE = VIL Com. IOUT = 0 mA, f = 0 Ind. VCC = VCC MAX., CE = VIL Com. IOUT = 0 mA, f = fMAX Ind. VCC = VCC MAX., VIN = VIH or VIL CE1 ≥ VIH, f = 0 or CE2 ≤ VIL, f = 0 VCC = VCC MAX., CE1 ≤ VCC – 0.2V, CE2 ≤ 0.2V VIN > VCC – 0.2V, or VIN ≤ 0.2V, f = 0 Com. Ind. -12 ns Min. Max. — — — — — — 85 110 170 180 40 60 -15 ns Min. Max. — — — — — — 85 110 160 170 40 60 -20 ns Min. Max. — — — — — — 85 110 150 160 40 60 ISSI -25 ns Min. Max. — — — — — — 85 110 140 150 40 60 Unit mA mA mA ® ISB2 CMOS Standby Current (CMOS Inputs) Com. Ind. — — 30 40 — — 30 40 — — 30 40 — — 30 40 mA Note: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. IS61C1024L POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter ICC1 ICC2 ISB1 Vcc Operating Supply Current Vcc Dynamic Operating Supply Current TTL Standby Current (TTL Inputs) Test Conditions VCC = VCC MAX., CE = VIL Com. IOUT = 0 mA, f = 0 Ind. VCC = VCC MAX., CE = VIL Com. IOUT = 0 mA, f = fMAX Ind. VCC = VCC MAX, VIN = VIH or VIL CE1 ≥ VIH, f = 0 or CE2 ≤ VIL, f = 0 VCC = VCC MAX., CE1 ≤ VCC – 0.2V, CE2 ≤ 0.2V VIN > VCC – 0.2V, or VIN ≤ 0.2V, f = 0 Com. Ind. -15 ns Min. Max. — — — — — — 85 110 160 170 40 60 -20 ns Min. Max. — — — — — — 85 110 150 160 40 60 -25 ns Min. Max. — — — — — — 85 110 140 150 40 60 Unit mA mA mA ISB2 CMOS Standby Current (CMOS Inputs) Com. Ind. — — 500 750 — — 500 750 — — 500 750 µA Note: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 4 SR028-1J 11/03/98 IS61C1024 IS61C1024L READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter Read Cycle Time Address Access Time Output Hold Time -12(2) Min. Max. 12 — 3 — — — 0 0 2 2 0 0 — — 12 — 12 12 6 — 6 — — 7 — 12 -15 ns Min. Max. 15 — 3 — — — 0 0 2 2 0 0 — — 15 — 15 15 7 — 6 — — 8 — 12 -20 ns Min. Max. 20 — 3 — — — 0 0 3 3 0 0 — — 20 — 20 20 9 — 7 — — 9 — 18 ISSI -25 ns Min. Max. 25 — 3 — — — 0 0 3 3 0 0 — — 25 — 25 25 9 — 10 — — 10 — 20 ns ns ns ns ns ns ns ns ns ns ns ns ns ® Unit tRC tAA tOHA tACE1 tACE2 tDOE tLZOE (3) CE1 Access Time CE2 Access Time OE Access Time OE to Low-Z Output tHZOE(3) OE to High-Z Output tLZCE1(3) CE1 to Low-Z Output tLZCE2 tHZCE tPU(4) tPD(4) (3) CE2 to Low-Z Output (3) CE1 or CE2 to High-Z Output CE1 or CE2 to Power-Up CE1 or CE2 to Power-Down Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1. 2. -12 ns device for IS61C1024 only. 3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 4. Not 100% tested. AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0V to 3.0V 3 ns 1.5V See Figures 1 and 2 AC TEST LOADS 480 Ω 5V 5V 480 Ω OUTPUT 30 pF Including jig and scope 255 Ω OUTPUT 5 pF Including jig and scope 255 Ω Figure 1 Figure 2 5 4 SR028-1K 05/12/99 IS61C1024 IS61C1024L AC WAVEFORMS READ CYCLE NO. 1(1,2) t RC ADDRESS ISSI ® t AA t OHA DOUT PREVIOUS DATA VALID t OHA DATA VALID READ1.eps READ CYCLE NO. 2(1,3) t RC ADDRESS t AA OE t OHA t DOE CE1 t HZOE t LZOE CE2 t LZCE1 t LZCE2 DOUT HIGH-Z t ACE1 t ACE2 DATA VALID t HZCE1 t HZCE2 CE2_RD2.eps Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE1 = VIL, CE2 = VIH. 3. Address is valid prior to or coincident with CE1 LOW and CE2 HIGH transitions. 6 SR028-1J 11/03/98 IS61C1024 IS61C1024L ISSI -12 ns(3) Min. Max. 12 10 10 10 0 0 10 7 0 — 2 — — — — — — — — — 7 — -15 ns Min. Max. 15 12 12 12 0 0 10 8 0 — 2 — — — — — — — — — 7 — -20 ns Min. Max. 20 15 15 15 0 0 12 10 0 — 2 — — — — — — — — — 10 — -25 ns Min. Max. 25 20 20 20 0 0 15 12 0 — 2 — — — — — — — — — 12 — ns ns ns ns ns ns ns ns ns ns ns ® WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range, Standard and Low Power) Symbol Parameter Write Cycle Time Unit tWC tSCE1 tSCE2 tAW tHA tSA tPWE(4) tSD tHD tHZWE (5) CE1 to Write End CE2 to Write End Address Setup Time to Write End Address Hold from Write End Address Setup Time WE Pulse Width Data Setup to Write End Data Hold from Write End WE LOW to High-Z Output tLZWE(5) WE HIGH to Low-Z Output Notes: 1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1. 2. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. 3. -12 ns device for IS61C1024 only. 4. Tested with OE HIGH. 5. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 4 SR028-1K 05/12/99 7 IS61C1024 IS61C1024L AC WAVEFORMS WRITE CYCLE NO. 1 (CE Controlled, OE is HIGH or LOW) (1 ) t WC ADDRESS VALID ADDRESS ISSI t SCE1 t SCE2 ® t SA CE1 t HA CE2 WE t AW t PWE1 t PWE2 t HZWE t LZWE HIGH-Z DOUT DATA UNDEFINED t SD DIN t HD DATAIN VALID CE2_WR1.eps WRITE CYCLE NO. 2 (OE is HIGH During Write Cycle) (1,2) t WC ADDRESS VALID ADDRESS t HA OE CE1 CE2 WE LOW HIGH t AW t PWE1 t SA t HZWE DATA UNDEFINED HIGH-Z t LZWE DOUT t SD DIN t HD DATAIN VALID CE2_WR2.eps Notes: 1. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. 2. I/O will assume the High-Z state if OE = VIH. 8 SR028-1J 11/03/98 IS61C1024 IS61C1024L WRITE CYCLE NO. 3 (OE is LOW During Write Cycle) (1) t WC ADDRESS VALID ADDRESS ISSI ® OE CE1 LOW LOW HIGH t HA CE2 t AW t PWE2 WE t SA DOUT DATA UNDEFINED t HZWE HIGH-Z t LZWE t SD DIN t HD DATAIN VALID CE2_WR3.eps 9 SR028-1K 05/12/99 IS61C1024 IS61C1024L IS61C1024 STANDARD VERSION ORDERING INFORMATION Commercial Range: 0°C to +70°C Speed (ns) 12 12 12 12 15 15 15 15 20 20 20 20 25 25 25 25 Order Part No. IS61C1024-12J IS61C1024-12K IS61C1024-12H IS61C1024-12T IS61C1024-15J IS61C1024-15K IS61C1024-15H IS61C1024-15T IS61C1024-20J IS61C1024-20K IS61C1024-20H IS61C1024-20T IS61C1024-25J IS61C1024-25K IS61C1024-25H IS61C1024-25T Package 300-mil Plastic SOJ 400-mil Plastic SOJ sTSOP (Type I) TSOP (Type I) 300-mil Plastic SOJ 400-mil Plastic SOJ sTSOP (Type I) TSOP (Type I) 300-mil Plastic SOJ 400-mil Plastic SOJ sTSOP (Type I) TSOP (Type I) 300-mil Plastic SOJ 400-mil Plastic SOJ sTSOP (Type I) TSOP (Type I) ISSI IS61C1024 STANDARD VERSION ORDERING INFORMATION Industrial Range: –40°C to +85°C Speed (ns) 12 12 12 12 15 15 15 15 20 20 20 20 25 25 25 25 Order Part No. IS61C1024-12JI IS61C1024-12KI IS61C1024-12HI IS61C1024-12TI IS61C1024-15JI IS61C1024-15KI IS61C1024-15HI IS61C1024-15TI IS61C1024-20JI IS61C1024-20KI IS61C1024-20HI IS61C1024-20TI IS61C1024-25JI IS61C1024-25KI IS61C1024-25HI IS61C1024-25TI Package 300-mil Plastic SOJ 400-mil Plastic SOJ sTSOP (Type I) TSOP (Type I) 300-mil Plastic SOJ 400-mil Plastic SOJ sTSOP (Type I) TSOP (Type I) 300-mil Plastic SOJ 400-mil Plastic SOJ sTSOP (Type I) TSOP (Type I) 300-mil Plastic SOJ 400-mil Plastic SOJ sTSOP (Type I) TSOP (Type I) ® IS61C1024L LOW POWER VERSION ORDERING INFORMATION Commercial Range: 0°C to +70°C Speed (ns) 15 Order Part No. IS61C1024L-15J IS61C1024L-15K IS61C1024L-15H IS61C1024L-15T IS61C1024L-20J IS61C1024L-20K IS61C1024L-20H IS61C1024L-20T IS61C1024L-25J IS61C1024L-25K IS61C1024L-25H IS61C1024L-25T Package 300-mil Plastic SOJ 400-mil Plastic SOJ sTSOP (Type I) TSOP (Type I) 300-mil Plastic SOJ 400-mil Plastic SOJ sTSOP (Type I) TSOP (Type I) 300-mil Plastic SOJ 400-mil Plastic SOJ sTSOP (Type I) TSOP (Type I) IS61C1024L LOW POWER VERSION ORDERING INFORMATION Industrial Range: –40°C to +85°C Speed (ns) 15 Order Part No. IS61C1024L-15JI IS61C1024L-15KI IS61C1024L-12HI IS61C1024L-15TI IS61C1024L-20JI IS61C1024L-20KI IS61C1024L-12HI IS61C1024L-20TI IS61C1024L-25JI IS61C1024L-25KI IS61C1024L-12HI IS61C1024L-25TI Package 300-mil Plastic SOJ 400-mil Plastic SOJ sTSOP (Type I) TSOP (Type I) 300-mil Plastic SOJ 400-mil Plastic SOJ sTSOP (Type I) TSOP (Type I) 300-mil Plastic SOJ 400-mil Plastic SOJ sTSOP (Type I) TSOP (Type I) 20 20 25 25 10 SR028-1J 11/03/98
IS61C1024-20J 价格&库存

很抱歉,暂时无法提供与“IS61C1024-20J”相匹配的价格&库存,您可以联系我们找货

免费人工找货