IS61C1024AL-12TLI

IS61C1024AL IS64C1024AL 128K x 8 HIGH-SPEED CMOS STATIC RAM FEATURES • High-speed access time: 12, 15 ns • Low active power: 160 mW (typical) • Low standby power: 1000 µW (typical) CMOS standby • Output Enable (OE) and two Chip Enable (CE1 and CE2) inputs for ease in applications • Fully static operation: no clock or refresh required • TTL compatible inputs and outputs • Single 5V (±10%) power supply • Commercial, industrial, and automotive temperature ranges available • Lead free available MAY 2022 DESCRIPTION The ISSI IS61C1024AL/IS64C1024AL is a very high- speed, low power, 131,072-word by 8-bit CMOS static RAMs. They are fabricated using ISSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields higher performance and low power consumption devices. When CE1 is HIGH or CE2 is LOW (deselected), the device assumes a standby mode at which the power dissipation can be reduced by using CMOS input levels. Easy memory expansion is provided by using two Chip Enable inputs, CE1 and CE2.The active LOW Write Enable (WE) controls both writing and reading of the memory. The IS61C1024AL/IS64C1024AL is available in 32-pin 300-mil SOJ, 32-pin 400-mil SOJ, 32-pin TSOP (Type I, 8x20), and 32-pin sTSOP (Type I, 8 x 13.4) packages. FUNCTIONAL BLOCK DIAGRAM A0-A16 DECODER 128K x 8 MEMORY ARRAY I/O DATA CIRCUIT COLUMN I/O VDD GND I/O0-I/O7 CE1 CE2 OE WE CONTROL CIRCUIT Copyright © 2022 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 1 Rev. E3 05/20/2022 IS61C1024AL, IS64C1024AL PIN CONFIGURATION PIN CONFIGURATION 32-Pin SOJ 32-Pin TSOP (Type 1) (T) and sTSOP (Type 1) (H) NC 1 32 VDD A16 2 31 A15 A14 3 30 CE2 A12 4 29 WE A7 5 28 A13 A6 6 27 A8 A5 7 26 A9 A4 8 25 A11 A3 9 24 OE A2 10 23 A10 A1 11 22 CE1 A0 12 21 I/O7 I/O0 13 20 I/O6 I/O1 14 19 I/O5 I/O2 15 18 I/O4 GND 16 17 I/O3 A11 A9 A8 A13 WE CE2 A15 VDD NC A16 A14 A12 A7 A6 A5 A4 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3 PIN DESCRIPTIONS A0-A16 Address Inputs CE1 Chip Enable 1 Input CE2 Chip Enable 2 Input OE Output Enable Input WE Write Enable Input I/O0-I/O7 Input/Output Vdd Power GND Ground OPERATING RANGE (IS61C1024AL) Range Ambient Temperature Commercial 0°C to +70°C Industrial -40°C to +85°C Vdd 5V ± 10% 5V ± 10% OPERATING RANGE (IS64C1024AL) Range Automotive Ambient Temperature -40°C to +125°C Vdd 5V ± 10% TRUTH TABLE Mode WE CE1 CE2 OE I/O Operation Vdd Current Not Selected X H X X High-Z Isb1, Isb2 (Power-down) X X L X High-Z Isb1, Isb2 Output Disabled H L H H High-Z Icc1, Icc2 Read H L H L Dout Icc1, Icc2 Write L L H X Din Icc1, Icc2 2 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. E3 05/20/2022 IS61C1024AL, IS64C1024AL ABSOLUTE MAXIMUM RATINGS(1) Symbol Parameter Vterm Terminal Voltage with Respect to GND Tstg Storage Temperature Pt Power Dissipation Iout DC Output Current (LOW) Value –0.5 to +7.0 –65 to +150 1.5 20 Unit V °C W mA Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. CAPACITANCE(1,2) Symbol Parameter Cin Input Capacitance Cout Output Capacitance Conditions Vin = 0V Vout = 0V Max. Unit 5 pF 7 pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: Ta = 25°C, f = 1 MHz, Vdd = 5.0V. DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Symbol Parameter Test Conditions Min. Max. Unit Voh Output HIGH Voltage Vdd = Min., Ioh = –4.0 mA 2.4 — V Vol Output LOW Voltage Vdd = Min., Iol = 8.0 mA — 0.4 V Vih Input HIGH Voltage 2.2 Vdd + 0.5 V (1) Vil Input LOW Voltage –0.3 0.8 V Ili Input Leakage GND ≤ Vin ≤ Vdd Com. –1 1 µA Ind. –2 2 Auto. –5 5 Ilo Output Leakage GND ≤ Vout ≤ Vdd Com. –1 1 µA Outputs Disabled Ind. –2 2 Auto. –5 5 Note: 1. Vil = –3.0V for pulse width less than 10 ns. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 3 Rev. E3 05/22/2022 IS61C1024AL, IS64C1024AL IS61C1024AL/IS64C1024AL POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)          -12 ns     -15 ns Symbol Parameter Test Conditions Min. Max. Min. Max. Unit Icc1 Vdd Operating Vdd = Vdd max., CE1 = Vil Com. — 35 mA Supply Current Iout = 0 mA, f = 0 Ind. — 40 Auto. — 45 Icc2 Vdd Dynamic Operating Vdd = Vdd max., CE1 = Vil Com. — 45 mA Supply Current Iout = 0 mA, f = fmax Ind. — 50 Auto. — 55 typ.(2) — 32 Isb1 TTL Standby Current Vdd = Vdd max., Com. — 1 mA (TTL Inputs) Vin = Vih or Vil Ind. — 1.5 CE1 ≥ Vih, f = 0 or Auto. — 2 CE2 ≤ Vil, f = 0 Isb2 CMOS Standby Vdd = Vdd max., Com. — 400 µA Current (CMOS Inputs) CE1 ≥ Vdd – 0.2V, Ind. — 450 CE2 ≤ 0.2V Auto. — 500 Vin ≥ Vdd – 0.2V, or typ.(2) — 200 Vin ≤ 0.2V, f = 0 Note: 1. At f = fmax, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. Typical Values are measured at Vdd = 5V, Ta = 25oC and not 100% tested. 4 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. E3 05/20/2022 IS61C1024AL, IS64C1024AL READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)     Symbol Parameter trc Read Cycle Time taa Address Access Time toha Output Hold Time tace1 CE1 Access Time tace2 CE2 Access Time tdoe OE Access Time tlzoe(2) OE to Low-Z Output thzoe(2) OE to High-Z Output (2) tlzce1 CE1 to Low-Z Output (2) tlzce2 CE2 to Low-Z Output thzce(2) CE1 or CE2 to High-Z Output tpu(3) CE1 or CE2 to Power-Up (3) tpd CE1 or CE2 to Power-Down -12 Min. Max. 12 — — 12 3 — — 12 — 12 — 6 0 — 0 6 2 — 2 — 0 7 0 — — 12 -15     Min. Max. Unit 15 — ns — 15 ns 3 — ns — 15 ns — 15 ns — 7 ns 0 — ns 0 6 ns 2 — ns 2 — ns 0 8 ns 0 — ns — 12 ns Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3. Not 100% tested. AC TEST CONDITIONS Parameter Unit Input Pulse Level 0V to 3.0V Input Rise and Fall Times 3 ns Input and Output Timing 1.5V and Reference Level Output Load See Figures 1 and 2 AC TEST LOADS 480 Ω 480 Ω 5V 5V OUTPUT OUTPUT 30 pF Including jig and scope 255 Ω Figure 1 5 pF Including jig and scope 255 Ω Figure 2 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 5 Rev. E3 05/22/2022 IS61C1024AL, IS64C1024AL AC WAVEFORMS READ CYCLE NO. 1(1,2) t RC ADDRESS t OHA DOUT t AA t OHA DATA VALID PREVIOUS DATA VALID READ1.eps READ CYCLE NO. 2(1,3) t RC ADDRESS t AA t OHA OE t HZOE t DOE t LZOE CE1 CE2 t LZCE1 t LZCE2 DOUT t ACE1 t ACE2 HIGH-Z t HZCE1 t HZCE2 DATA VALID CE2_RD2.eps Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE1 = Vil, CE2 = Vih. 3. Address is valid prior to or coincident with CE1 LOW and CE2 HIGH transitions. 6 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. E3 05/20/2022 IS61C1024AL, IS64C1024AL WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range, Standard and Low Power)     Symbol Parameter twc Write Cycle Time tsce1 CE1 to Write End tsce2 CE2 to Write End taw Address Setup Time to Write End tha Address Hold from Write End tsa Address Setup Time tpwe(3) WE Pulse Width tsd Data Setup to Write End thd Data Hold from Write End (4) thzwe WE LOW to High-Z Output tlzwe(4) WE HIGH to Low-Z Output -12 ns     -15 ns Min. Max. Min. Max. 12 — 15 — 10 — 12 — 10 — 12 — 10 — 12 — 0 — 0 — 0 — 0 — 10 — 12 — 7 — 10 —­ 0 — 0 —­ — 7 —­ 7 2 — 2 —­ Unit ns ns ns ns ns ns ns ns ns ns ns Notes: 1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1. 2. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. 3. Tested with OE HIGH. 4. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 7 Rev. E3 05/22/2022 IS61C1024AL, IS64C1024AL AC WAVEFORMS WRITE CYCLE NO. 1 (CE1 Controlled, OE is HIGH or LOW) (1 ) t WC VALID ADDRESS ADDRESS t SCE1 t SCE2 t SA t HA CE1 CE2 t AW t PWE1 t PWE2 WE t HZWE DOUT t LZWE HIGH-Z DATA UNDEFINED t SD t HD DATAIN VALID DIN CE2_WR1.eps WRITE CYCLE NO. 2 (OE is HIGH During Write Cycle) (1,2) t WC ADDRESS VALID ADDRESS t HA OE CE1 LOW HIGH CE2 t AW t PWE1 WE t HZWE t SA DOUT DATA UNDEFINED t LZWE HIGH-Z t SD DIN t HD DATAIN VALID CE2_WR2.eps Notes: 1. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. 2. I/O will assume the High-Z state if OE = Vih. 8 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. E3 05/20/2022 IS61C1024AL, IS64C1024AL WRITE CYCLE NO. 3 (OE is LOW During Write Cycle) (1) t WC ADDRESS VALID ADDRESS OE LOW CE1 LOW t HA HIGH CE2 t AW t PWE2 WE t SA DOUT DATA UNDEFINED t HZWE t LZWE HIGH-Z t SD DIN t HD DATAIN VALID CE2_WR3.eps Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 9 Rev. E3 05/22/2022 IS61C1024AL, IS64C1024AL DATA RETENTION SWITCHING CHARACTERISTICS Symbol Parameter Vdr Vdd for Data Retention Idr Data Retention Current tsdr Data Retention Setup Time trdr Recovery Time Note: Test Condition See Data Retention Waveform Vdd = 2.0V, CE1 ≥ Vdd – 0.2V Com. or CE2 ≤ 0.2V Ind. Vin ≥ Vdd – 0.2V, or Vin ≤ Vss + 0.2V Auto. See Data Retention Waveform See Data Retention Waveform Min. Typ.(1) Max. Unit 2.0 5.5 V — 200 400 µA — — 450 — — 500 0 — ns trc — ns 1. Typical Values are measured at Vdd = 5V, Ta = 25oC and not 100% tested. DATA RETENTION WAVEFORM (CE1 Controlled) Data Retention Mode tSDR tRDR VDD 4.5V 2.2V VDR CE1 ≥ VDD - 0.2V CE1 GND DATA RETENTION WAVEFORM (CE2 Controlled) Data Retention Mode 4.5V VDD CE2 2.2V tSDR tRDR VDR 0.4V CE2 ≤ 0.2V GND 10 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. E3 05/20/2022 IS61C1024AL, IS64C1024AL ORDERING INFORMATION: IS61C1024AL Industrial Range: –40°C to +85°C Speed (ns) 12 Order Part No. IS61C1024AL-12JLI IS61C1024AL-12HLI IS61C1024AL-12TLI Package 300-mil Plastic SOJ, Lead-free sTSOP (Type I), Lead-free TSOP (Type I), Lead-free ORDERING INFORMATION: IS64C1024AL Automotive Range: –40°C to +125°C Speed (ns) 15 Order Part No. IS64C1024AL-15TLA3 Package TSOP (Type I), Lead-free Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 11 Rev. E3 05/22/2022 IS61C1024AL, IS64C1024AL 12 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. E3 05/20/2022 Rev. E3 05/22/2022 SEATING PLANE 3. Dimension b2 does not include dambar protrusion/intrusion. 4. Formed leads shall be planar with respect to one another within 0.1mm at the seating plane after final test. 5. Reference document : JEDEC SPEC MS-027. 2. Dimension D and E1 do not include mold protrusion . 1. Controlling dimension : mm NOTE : 12/19/2007 IS61C1024AL, IS64C1024AL Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 13 IS61C1024AL, IS64C1024AL 14 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. E3 05/20/2022 IS61C1024AL, IS64C1024AL Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 15 Rev. E3 05/22/2022