IS61C256AL-12JLI-TR

IS61C256AL 32K x 8 HIGH-SPEED CMOS STATIC RAM JANUARY 2020 FEATURES DESCRIPTION • High-speed access time: 10, 12 ns • CMOS Low Power Operation — 1 mW (typical) CMOS standby — 125 mW (typical) operating • Fully static operation: no clock or refresh required • TTL compatible inputs and outputs • Single 5V power supply • Lead-free available The ISSI IS61C256AL is a very high-speed, low power, 32,768 word by 8-bit static RAMs. It is fabricated using ISSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields access times as fast as 10 ns maximum. When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation can be reduced down to 150 µW (typical) with CMOS input levels. Easy memory expansion is provided by using an active LOW Chip Enable (CE) input and an active LOW Output Enable (OE) input. The active LOW Write Enable (WE) controls both writing and reading of the memory. The IS61C256AL is pin compatible with other 32Kx8 SRAMs and are available in 28-pin SOJ and TSOP (Type I) packages. FUNCTIONAL BLOCK DIAGRAM A0-A14 DECODER 32K X 8 MEMORY ARRAY VDD GND I/O DATA CIRCUIT I/O0-I/O7 COLUMN I/O CE OE CONTROL CIRCUIT WE Copyright © 2020 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. C1 01/17/2020 1 IS61C256AL PIN CONFIGURATION PIN CONFIGURATION 28-Pin SOJ 28-Pin TSOP A14 1 28 VDD A12 2 27 WE A7 3 26 A13 A6 4 25 A8 A5 5 24 A9 A4 6 23 A11 A3 7 22 OE A2 8 21 A10 A1 9 20 CE A0 10 19 I/O7 I/O0 11 18 I/O6 I/O1 12 17 I/O5 I/O2 13 16 I/O4 GND 14 15 I/O3 PIN DESCRIPTIONS OE A11 A9 A8 A13 WE VDD A14 A12 A7 A6 A5 A4 A3 21 20 19 18 17 16 15 14 13 12 11 10 9 8 22 23 24 25 26 27 28 1 2 3 4 5 6 7 A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 TRUTH TABLE A0-A14 Address Inputs Mode CE Chip Enable Input OE Output Enable Input WE Write Enable Input I/O0-I/O7 Bidirectional Ports VDD Power Not Selected X (Power-down) Output Disabled H Read H Write L GND Ground WE WE I/O Operation VDD Current CE CE OE OE H X High-Z ISB1, ISB2 L L L H L X High-Z DOUT DIN ICC ICC ICC ABSOLUTE MAXIMUM RATINGS(1) Symbol VTERM TSTG PT IOUT Parameter Terminal Voltage with Respect to GND Storage Temperature Power Dissipation DC Output Current (LOW) Value –0.5 to +7.0 –65 to +150 1.5 20 Unit V °C W mA Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. C1 01/17/2020 IS61C256AL OPERATING RANGE Range Commercial Commercial Industrial Ambient Temperature 0°C to +70°C 0°C to +70°C –40°C to +85°C Speed (ns) -10 -12 -12 VDD (V) 5V ± 5% 5V ± 10% 5V ± 10% DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Symbol Parameter Test Conditions Min. Max. Unit VOH Output HIGH Voltage VDD = Min., IOH = –4.0 mA 2.4 — V VOL Output LOW Voltage VDD = Min., IOL = 8.0 mA — 0.4 V VIH Input HIGH Voltage 2.2 VDD + 0.5 V VIL Input LOW Voltage(1) –0.3 0.8 V ILI Input Leakage GND ≤ VIN ≤ VDD Com. Ind. –1 –2 1 2 µA ILO Output Leakage GND ≤ VOUT ≤ VDD, Outputs Disabled Com. Ind. –1 –2 1 2 µA Note: 1. VIL = –3.0V for pulse width less than 10 ns. POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) -10 Min. Max. -12 Min. Max. Symbol Parameter Test Conditions Unit ICC1 VDD Operating Supply Current VDD = Max., CE = VIL IOUT = 0 mA, f = 0 Com. Ind. — — 20 — — — 20 25 mA ICC2 VDD Dynamic Operating Supply Current VDD = Max., CE = VIL IOUT = 0 mA, f = fMAX Com. Ind. typ.(2) — — 45 — — — 35 40 mA ISB1 TTL Standby Current (TTL Inputs) VDD = Max., VIN = VIH or VIL CE ≥ VIH, f = 0 Com. Ind. — — 1 — — — 1 2 mA ISB2 CMOS Standby Current (CMOS Inputs) VDD = Max., CE ≥ VDD – 0.2V, VIN ≥ VDD – 0.2V, or VIN ≤ 0.2V, f = 0 Com. Ind. typ.(2) — — 350 — — 350 — 450 200 25 µA Note: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. Typical values are measured at VDD = 5V, TA = 25oC and not 100% tested. CAPACITANCE(1,2) Symbol Parameter CIN Input Capacitance COUT Output Capacitance Conditions Max. Unit VIN = 0V 8 pF VOUT = 0V 10 pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25°C, f = 1 MHz, VDD = 5.0V. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. C1 01/17/2020 3 IS61C256AL READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) Symbol -10 ns Min. Max Parameter -12 ns Min. Max. Unit tRC Read Cycle Time 10 — 12 — ns tAA Address Access Time — 10 — 12 ns tOHA Output Hold Time 2 — 2 — ns tACS CE Access Time — 10 — 12 ns OE Access Time — 6 — 6 ns tLZOE OE to Low-Z Output 0 — 0 — ns tHZOE(2) OE to High-Z Output — 5 — 6 ns tLZCS(2) CE to Low-Z Output 2 — 3 — ns tHZCS CE to High-Z Output — 5 — 7 ns tPU CE to Power-Up 0 — 0 — ns tPD CE to Power-Down — 10 — 12 ns tDOE (2) (2) (3) (3) Notes: 1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3. Not 100% tested. AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Levels Output Load Unit 0V to 3.0V 3 ns 1.5V See Figures 1 and 2 AC TEST LOADS 480 Ω 5V OUTPUT OUTPUT 30 pF Including jig and scope Figure 1 4 480 Ω 5V 255 Ω 5 pF Including jig and scope 255 Ω Figure 2 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. C1 01/17/2020 IS61C256AL AC WAVEFORMS READ CYCLE NO. 1(1,2) t RC ADDRESS t AA t OHA t OHA DOUT DATA VALID PREVIOUS DATA VALID READ1.eps READ CYCLE NO. 2(1,3) t RC ADDRESS t AA t OHA OE t HZOE t DOE CE t LZOE t ACS t HZCS t LZCS DOUT HIGH-Z DATA VALID CE_RD2.eps Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE = VIL. 3. Address is valid prior to or coincident with CE LOW transitions. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. C1 01/17/2020 5 IS61C256AL WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range) Symbol -10 ns Min. Max Parameter -12 ns Min. Max. Unit tWC Write Cycle Time 10 — 12 — ns tSCS CE to Write End 9 — 10 — ns tAW Address Setup Time to Write End 9 — 10 — ns tHA Address Hold from Write End 0 — 0 — ns tSA Address Setup Time 0 — 0 — ns tPWE1 WE Pulse Width (OE LOW) 9 — 9 — ns tPWE2 WE Pulse Width (OE HIGH) 8 — 8 — ns tSD Data Setup to Write End 7 — 7 — ns tHD Data Hold from Write End 0 — 0 — ns (2) tHZWE WE LOW to High-Z Output — 6 — 6 ns tLZWE(2) WE HIGH to Low-Z Output 0 — 0 — ns Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. AC WAVEFORMS WE Controlled)(1,2) WRITE CYCLE NO. 1 (WE t WC VALID ADDRESS ADDRESS t SA t SCS t HA CE t AW t PWE1 t PWE2 WE t HZWE DOUT DATA UNDEFINED t LZWE HIGH-Z t SD DIN t HD DATAIN VALID CE_WR1.eps 6 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. C1 01/17/2020 IS61C256AL WRITE CYCLE NO. 2 (OE is HIGH During Write Cycle) (1,2) t WC ADDRESS VALID ADDRESS t HA OE CE LOW t AW t PWE1 WE t SA DOUT t HZWE t LZWE HIGH-Z DATA UNDEFINED t SD t HD DATAIN VALID DIN CE_WR2.eps WRITE CYCLE NO. 3 (OE is LOW During Write Cycle) (1) t WC ADDRESS OE CE VALID ADDRESS t HA LOW LOW t AW t PWE2 WE t SA DOUT DATA UNDEFINED t HZWE t LZWE HIGH-Z t SD DIN t HD DATAIN VALID CE_WR3.eps Notes: 1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. 2. I/O will assume the High-Z state if OE ≥ VIH. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. C1 01/17/2020 7 IS61C256AL DATA RETENTION SWITCHING CHARACTERISTICS Symbol Parameter Test Condition Min. VDR VDD for Data Retention See Data Retention Waveform 2.0 IDR Data Retention Current VDD = 2.0V, CE ≥ VDD – 0.2V VIN ≥ VDD – 0.2V, or VIN ≤ VSS + 0.2V tSDR Data Retention Setup Time See Data Retention Waveform tRDR Recovery Time See Data Retention Waveform Com. Ind. Typ.(1) Max. Unit 5.5 V 90 100 µA 0 — ns tRC — ns — — 50 Note: 1. Typical Values are measured at VDD = 5V, TA = 25oC and not 100% tested. CE Controlled) DATA RETENTION WAVEFORM (CE tSDR Data Retention Mode tRDR VDD 4.5V 2.2V VDR CE GND 8 CE ≥ VDD - 0.2V Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. C1 01/17/2020 IS61C256AL ORDERING INFORMATION: IS61C256AL Commercial Range: 0°C to +70°C Speed (ns) 10 Order Part Number Package IS61C256AL-10JL IS61C256AL-10TL 300-mil Plastic SOJ, Lead-free TSOP (Type 1), Lead-free 12 IS61C256AL-12JL IS61C256AL-12TL 300-mil Plastic SOJ, Lead-free TSOP (Type 1), Lead-free Industrial Range: –40°C to +85°C Speed (ns) 12 Order Part Number Package IS61C256AL-12JLI IS61C256AL-12TLI 300-mil Plastic SOJ, Lead-free TSOP (Type 1), Lead-free Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. C1 01/17/2020 9 22 1 i[o / I �la' I JR= GAUGE PLANE SEATING PLANE PIN1 Laser dot Dl D 8 I p::l c-- Al A2 ZD e ;; I � f ,� SYMBOL A Al A2 b D D1 E e L L1 ZD e C 0,037 0,047 0,002 0,008 -0,035 - 0,041 0,007 0,009 0,011 0,520 0,528 0,535 0.461 0.465 0.469 0.311 0.315 0.319 0.022 BSC, 0.012 0.020 0.028 0.010 BSC, 0.017 REF, 50 30 0 0.12 0.21 DIMENSION IN MM DIMENSION IN INCH MIN NOM MAX MIN NOM MAX 0,95 1.20 0,05 0,20 0,90 - 1.05 0.17 0,22 0,27 13.20 13.40 13.60 11.70 11.80 11.90 7,90 8.00 8.10 0.55 BSC, 0.30 0.50 0.70 0.25 BSC, 0.425 REF, 30 50 0 0,21 0.12 4. Referedce Document: JEDEC MO-183 28L 8x13.4mm T�OP-1 REV. Package Outline 1 G DATE l10/28/2019 3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION/INTRUSION. 2. DIMENSION D1 AND E DO NOT INCLUDE MOLD PROTRUSION. 1. CONTROLLING DIMENSION : MM NOTE: IA rr i li1 l e DETAIL A DETAIL A C 1� 7, =t � L ff7n Will TITLE 0.1 Y NOTE : 1. Controlling dimension : mm 2. Dimension D1 adn E do not include mold protrusion . 3. Dimension b2 does not include dambar protrusion/intrusion. 4. Formed leads shall be planar with respect to one another within 0.1mm at the seating plane after final test. Package Outline 07/05/2006