IS61C3216AL-12KI

IS61C3216AL 32K x 16 HIGH-SPEED CMOS STATIC RAM FEATURES • High-speed access time: 12 ns • Low Active Power: 175 mW (typical) • Low Standby Power: 1 mW (typical) CMOS standby • TTL compatible interface levels • Single 5V ± 10% power supply • Fully static operation: no clock or refresh required • Available in 44-pin SOJ package and 44-pin TSOP (Type II) • Commercial and Industrial temperature ranges available • Lead-free available ISSI SEPTEMBER 2005 ® DESCRIPTION The ISSI IS61C3216AL is high-speed, 512Kb static RAMs organized as 32,768 words by 16 bits. They are fabricated using ISSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields access times as fast as 12 ns with low power consumption. When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs, CE and OE. The active LOW Write Enable (WE) controls both writing and reading of the memory. A data byte allows Upper Byte (UB) and Lower Byte (LB) access. The IS61C3216AL is packaged in the JEDEC standard 44pin 400-mil SOJ and 44-pin TSOP (Type II). FUNCTIONAL BLOCK DIAGRAM A0-A14 DECODER 32K x 16 MEMORY ARRAY VDD GND I/O0-I/O7 Lower Byte I/O8-I/O15 Upper Byte I/O DATA CIRCUIT COLUMN I/O CE OE WE UB LB CONTROL CIRCUIT Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A 09/26/05 1 IS61C3216AL ISSI 44-Pin TSOP (Type II) 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A0 A1 A2 OE UB LB I/O15 I/O14 I/O13 I/O12 GND VDD I/O11 I/O10 I/O9 I/O8 NC A3 A4 A5 A6 NC ® PIN CONFIGURATIONS 44-Pin SOJ NC A14 A13 A12 A11 CE I/O0 I/O1 I/O2 I/O3 VDD GND I/O4 I/O5 I/O6 I/O7 WE A10 A9 A8 A7 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 NC A14 A13 A12 A11 CE I/O0 I/O1 I/O2 I/O3 VDD GND I/O4 I/O5 I/O6 I/O7 WE A10 A9 A8 A7 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A0 A1 A2 OE UB LB I/O15 I/O14 I/O13 I/O12 GND VDD I/O11 I/O10 I/O9 I/O8 NC A3 A4 A5 A6 NC PIN DESCRIPTIONS A0-A14 I/O0-I/O15 CE OE WE Address Inputs Data Inputs/Outputs Chip Enable Input Output Enable Input Write Enable Input LB UB NC VDD GND Lower-byte Control (I/O0-I/O7) Upper-byte Control (I/O8-I/O15) No Connection Power Ground 2 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A 09/26/05 IS61C3216AL TRUTH TABLE Mode Not Selected Output Disabled Read WE X H X H H H L L L CE H L L L L L L L L OE X H X L L L X X X LB X X H L H L L H L UB X X H H L L H L L I/O PIN I/O0-I/O7 I/O8-I/O15 High-Z High-Z High-Z DOUT High-Z DOUT DIN High-Z DIN High-Z High-Z High-Z High-Z DOUT DOUT High-Z DIN DIN ISSI VDD Current ISB1, ISB2 ICC1, ICC2 ICC1, ICC2 ® Write ICC1, ICC2 ABSOLUTE MAXIMUM RATINGS(1) Symbol VTERM TSTG PT IOUT Parameter Terminal Voltage with Respect to GND Storage Temperature Power Dissipation DC Output Current (LOW) Value –0.5 to +7.0 –65 to +150 1.5 20 Unit V °C W mA Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. OPERATING RANGE (IS61C3216AL) Range Commercial Industrial Ambient Temperature 0°C to +70°C -40°C to +85°C VDD 5V ± 10% 5V ± 10% Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A 09/26/05 3 IS61C3216AL CAPACITANCE(1,2) Symbol CIN COUT Parameter Input Capacitance Output Capacitance Conditions VIN = 0V VOUT = 0V Max. 5 7 Unit pF pF ISSI ® Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25°C, f = 1 MHz, VDD = 5.0V. DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Symbol Parameter VOH VOL VIH VIL ILI ILO Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage(1) Input Leakage Output Leakage GND ≤ VIN ≤ VDD GND ≤ VOUT ≤ VDD Outputs Disabled Com. Ind. Com. Ind. Test Conditions VDD = Min., IOH = –4.0 mA VDD = Min., IOL = 8.0 mA Min. 2.4 — 2.2 –0.3 –1 –2 –1 –2 Max. — 0.4 VDD + 0.5 0.8 1 2 1 2 Unit V V V V µA µA Note: 1. VIL = –3.0V for pulse width less than 10 ns. 4 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A 09/26/05 IS61C3216AL IS61C3216AL POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter ICC1 VDD Operating Supply Current VDD Dynamic Operating Supply Current TTL Standby Current (TTL Inputs) Test Conditions VDD = VDD MAX., CE = VIL IOUT = 0 mA, f = 0 VDD = VDD MAX., CE = VIL IOUT = 0 mA, f = fMAX VDD = VDD MAX., VIN = VIH or VIL CE ≥ VIH, f = 0 VDD = VDD MAX., CE ≤ VDD – 0.2V, VIN ≥ VDD – 0.2V, or VIN ≤ 0.2V, f = 0 Com. Ind. Com. Ind. typ.(2) Com. Ind. -12 ns Min. Max. — — — — 35 — — 1 1 40 45 50 55 ISSI Unit mA ® ICC2 mA ISB1 mA ISB2 CMOS Standby Current (CMOS Inputs) Com. Ind. typ.(2) — — 200 350 400 µA Note: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. Typical values are measured at VDD = 5V, TA = 25oC and not 100% tested. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A 09/26/05 5 IS61C3216AL READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter Read Cycle Time Address Access Time Output Hold Time CE Access Time OE Access Time OE to High-Z Output OE to Low-Z Output CE to High-Z Output CE to Low-Z Output LB, UB Access Time LB, UB to High-Z Output LB, UB to Low-Z Output -12 Min. Max. 12 — — 3 — — 0 0 0 2 — 0 0 12 — 12 6 6 — 7 — 6 6 — Unit ns ns ns ns ns ns ns ns ns ns ns ns ISSI ® tRC tAA tOHA tACE tDOE tHZOE(2) tLZOE(2) tHZCE(2 tLZCE(2) tBA tHZB tLZB Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3. Not 100% tested. AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0V to 3.0V 3 ns 1.5V See Figures 1 and 2 AC TEST LOADS 480 Ω 5V 5V 480 Ω OUTPUT 30 pF Including jig and scope 255 Ω OUTPUT 5 pF Including jig and scope 255 Ω Figure 1 Figure 2 6 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A 09/26/05 IS61C3216AL ISSI t RC ® AC WAVEFORMS READ CYCLE NO. 1(1,2) (Address Controlled) (CE = OE = VIL, UB or LB = VIL) ADDRESS t AA t OHA DOUT PREVIOUS DATA VALID t OHA DATA VALID READ1.eps READ CYCLE NO. 2(1,3) t RC ADDRESS t AA OE t OHA t DOE CE t HZOE t LZOE t ACE t LZCE t HZCE LB, UB DOUT HIGH-Z t LZB t BA DATA VALID t HZB UB_CEDR2.eps Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE, UB, or LB = VIL. 3. Address is valid prior to or coincident with CE LOW transition. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A 09/26/05 7 IS61C3216AL WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range) Symbol Parameter Write Cycle Time CE to Write End Address Setup Time to Write End Address Hold from Write End Address Setup Time LB, UB Valid to End of Write WE Pulse Width (OE =High) WE Pulse Width (OE=Low) Data Setup to Write End Data Hold from Write End WE LOW to High-Z Output WE HIGH to Low-Z Output -12 Min. Max. 12 9 9 0 0 9 9 9 6 0 — 3 — — — — — — — — — — 6 — Unit ns ns ns ns ns ns ns ns ns ns ns ns ISSI ® tWC tSCE tAW tHA tSA tPWB tPWE1 tPWE2 tSD tHD tHZWE(2) tLZWE(2) Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. 8 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A 09/26/05 IS61C3216AL AC WAVEFORMS WRITE CYCLE NO. 1 (WE Controlled)(1,2) t WC ADDRESS VALID ADDRESS ISSI ® t SA CE t SCE t HA WE t AW t PWE1 t PWE2 t PBW UB, LB t HZWE DOUT DATA UNDEFINED HIGH-Z t LZWE t SD DIN t HD DATAIN VALID UB_CEWR1.eps Notes: 1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CE and WE inputs and at least one of the LB and UB inputs being in the LOW state. 2. WRITE = (CE) [ (LB) = (UB) ] (WE). Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A 09/26/05 9 IS61C3216AL WRITE CYCLE NO. 2 (OE is HIGH During Write Cycle) (1,2) t WC ADDRESS VALID ADDRESS ISSI t HA ® OE CE LOW t AW t PWE1 WE t SA UB, LB t PBW t HZWE t LZWE HIGH-Z DOUT DATA UNDEFINED t SD DIN t HD DATAIN VALID UB_CEWR2.eps WRITE CYCLE NO. 3 (OE is LOW During Write Cycle) (1) t WC ADDRESS VALID ADDRESS OE CE LOW t HA LOW t AW t PWE2 WE t SA UB, LB t PBW t HZWE t LZWE HIGH-Z DOUT DATA UNDEFINED t SD DIN t HD DATAIN VALID UB_CEWR3.eps Notes: 1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. 2. I/O will assume the High-Z state if OE ≥ VIH. 10 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A 09/26/05 IS61C3216AL WRITE CYCLE NO. 4 (UB/LB Back to Back Write) t WC ADDRESS ADDRESS 1 ISSI t WC ADDRESS 2 ® OE t SA CE LOW WE t HA t SA t PBW t PBW WORD 2 t HA UB, LB WORD 1 t HZWE DOUT HIGH-Z t LZWE t HD DATAIN VALID DATA UNDEFINED t SD DIN t SD DATAIN VALID t HD UB_CEWR4.eps Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A 09/26/05 11 IS61C3216AL DATA RETENTION SWITCHING CHARACTERISTICS Symbol Parameter VDD for Data Retention Data Retention Current Test Condition See Data Retention Waveform VDD = 2.0V, CE ≥ VDD – 0.2V VIN ≥ VDD – 0.2V, or VIN ≤ VSS + 0.2V See Data Retention Waveform See Data Retention Waveform Com. Ind. typ.(1) Min. 2.0 — — 0 — — 200 Typ. ISSI Max. 5.5 350 400 — — Unit V µA ® VDR IDR tSDR tRDR Note: Data Retention Setup Time Recovery Time ns ns tRC 1. Typical Values are measured at VDD = 5V, TA = 25oC and not 100% tested. DATA RETENTION WAVEFORM (CE Controlled) tSDR VDD 4.5V Data Retention Mode tRDR 2.2V VDR CE ≥ VDD - 0.2V CE GND 12 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A 09/26/05 IS61C3216AL ORDERING INFORMATION: IS61C3216AL Commercial Range: 0°C to +70°C Speed (ns) 12 Order Part No. IS61C3216AL-12K IS61C3216AL-12T Package 400-mil Plastic SOJ 44-pin TSOP-II ISSI ® Industrial Range: –40°C to +85°C Speed (ns) 12 Order Part No. IS61C3216AL-12KI IS61C3216AL-12KLI IS61C3216AL-12TI IS61C3216AL-12TLI Package 400-mil Plastic SOJ 400-mil Plastic SOJ, Lead-free 44-pin TSOP-II 44-pin TSOP-II, Lead-free Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A 09/26/05 13 PACKAGING INFORMATION 400-mil Plastic SOJ Package Code: K ISSI Notes: 1. Controlling dimension: millimeters. 2. BSC = Basic lead spacing between centers. 3. Dimensions D and E1 do not include mold flash protrusions and should be measured from the bottom of the package. 4. Reference document: JEDEC MS-027. ® N N/2+1 E1 E 1 N/2 D A SEATING PLANE b C A2 e B A1 E2 Symbol No. Leads A A1 A2 B b C D E E1 E2 e Millimeters Inches Min Max Min Max (N) 28 3.25 3.75 0.128 0.148 0.64 — 0.025 — 2.08 — 0.082 — 0.38 0.51 0.015 0.020 0.66 0.81 0.026 0.032 0.18 0.33 0.007 0.013 18.29 18.54 0.720 0.730 11.05 11.30 0.435 0.445 10.03 10.29 0.395 0.405 9.40 BSC 0.370 BSC 1.27 BSC 0.050 BSC Millimeters Min Max 32 3.25 3.75 0.64 — 2.08 — 0.38 0.51 0.66 0.81 0.18 0.33 20.82 21.08 11.05 11.30 10.03 10.29 9.40 BSC 1.27 BSC Inches Min Max 0.128 0.148 0.025 — 0.082 — 0.015 0.020 0.026 0.032 0.007 0.013 0.820 0.830 0.435 0.445 0.395 0.405 0.370 BSC 0.050 BSC Millimeters Min Max 36 3.25 3.75 0.64 — 2.08 — 0.38 0.51 0.66 0.81 0.18 0.33 23.37 23.62 11.05 11.30 10.03 10.29 9.40 BSC 1.27 BSC Inches Min Max 0.128 0.148 0.025 — 0.082 — 0.015 0.020 0.026 0.032 0.007 0.013 0.920 0.930 0.435 0.445 0.395 0.405 0.370 BSC 0.050 BSC Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. F 10/29/03 PACKAGING INFORMATION ISSI Millimeters Min Max 42 3.25 3.75 0.64 — 2.08 — 0.38 0.51 0.66 0.81 0.18 0.33 27.18 27.43 11.05 11.30 10.03 10.29 9.40 BSC 1.27 BSC Inches Min Max 0.128 0.148 0.025 — 0.082 — 0.015 0.020 0.026 0.032 0.007 0.013 1.070 1.080 0.435 0.445 0.395 0.405 0.370 BSC 0.050 BSC Millimeters Min Max 44 3.25 3.75 0.64 — 2.08 — 0.38 0.51 0.66 0.81 0.18 0.33 28.45 28.70 11.05 11.30 10.03 10.29 9.40 BSC 1.27 BSC 0.128 0.148 0.025 — 0.082 — 0.015 0.020 0.026 0.032 0.007 0.013 1.120 1.130 0.435 0.445 0.395 0.405 0.370 BSC 0.050 BSC Inches Min Max ® Millimeters Inches Symbol Min Max Min Max No. Leads (N) 40 A 3.25 3.75 0.128 0.148 A1 0.64 — 0.025 — A2 2.08 — 0.082 — B 0.38 0.51 0.015 0.020 b 0.66 0.81 0.026 0.032 C 0.18 0.33 0.007 0.013 D 25.91 26.16 1.020 1.030 E 11.05 11.30 0.435 0.445 E1 10.03 10.29 0.395 0.405 E2 9.40 BSC 0.370 BSC e 1.27 BSC 0.050 BSC Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. 2 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. F 10/29/03 PACKAGING INFORMATION Plastic TSOP Package Code: T (Type II) ISSI Notes: 1. Controlling dimension: millimieters, unless otherwise specified. 2. BSC = Basic lead spacing between centers. 3. Dimensions D and E1 do not include mold flash protrusions and should be measured from the bottom of the package. 4. Formed leads shall be planar with respect to one another within 0.004 inches at the seating plane. ® N N/2+1 E1 E 1 D N/2 SEATING PLANE ZD A . e b L A1 α C Symbol Ref. Std. No. Leads A A1 b C D E1 E e L ZD α Millimeters Min Max Inches Min Max Plastic TSOP (T - Type II) Millimeters Inches Min Max Min Max 44 — 1.20 — 0.047 0.05 0.15 0.002 0.006 0.30 0.45 0.012 0.018 0.12 0.21 0.005 0.008 18.31 18.52 0.721 0.729 10.03 10.29 0.395 0.405 11.56 11.96 0.455 0.471 0.80 BSC 0.032 BSC 0.41 0.60 0.016 0.024 0.81 REF 0.032 REF 0° 5° 0° 5° Millimeters Min Max 50 — 1.20 0.05 0.15 0.30 0.45 0.12 0.21 20.82 21.08 10.03 10.29 11.56 11.96 0.80 BSC 0.40 0.60 0.88 REF 0° 5° Inches Min Max (N) 32 — 1.20 — 0.047 0.05 0.15 0.002 0.006 0.30 0.52 0.012 0.020 0.12 0.21 0.005 0.008 20.82 21.08 0.820 0.830 10.03 10.29 0.391 0.400 11.56 11.96 0.451 0.466 1.27 BSC 0.050 BSC 0.40 0.60 0.016 0.024 0.95 REF 0.037 REF 0° 5° 0° 5° — 0.047 0.002 0.006 0.012 0.018 0.005 0.008 0.820 0.830 0.395 0.405 0.455 0.471 0.031 BSC 0.016 0.024 0.035 REF 0° 5° Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. F 06/18/03