IS61C3216AL-12TLI-TR

IS61C3216AL 32K x 16 HIGH-SPEED CMOS STATIC RAM FEATURES • High-speed access time: 12 ns • Low Active Power: 175 mW (typical) • Low Standby Power: 1 mW (typical) CMOS standby • TTL compatible interface levels • Single 5V ± 10% power supply • Fully static operation: no clock or refresh required • Available in 44-pin SOJ package and 44-pin TSOP (Type II) • Commercial and Industrial temperature ranges available • Lead-free available JANUARY 2020 DESCRIPTION The ISSI IS61C3216AL is high-speed, 512Kb static RAMs organized as 32,768 words by 16 bits. They are fabricated using ISSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields access times as fast as 12 ns with low power consumption. When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs, CE and OE. The active LOW Write Enable (WE) controls both writing and reading of the memory. A data byte allows Upper Byte (UB) and Lower Byte (LB) access. The IS61C3216AL is packaged in the JEDEC standard 44pin 400-mil SOJ and 44-pin TSOP (Type II). FUNCTIONAL BLOCK DIAGRAM A0-A14 DECODER 32K x 16 MEMORY ARRAY I/O DATA CIRCUIT COLUMN I/O VDD GND I/O0-I/O7 Lower Byte I/O8-I/O15 Upper Byte CE OE WE UB LB CONTROL CIRCUIT Copyright © 2020 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A1 01/22/2020 1 IS61C3216AL PIN CONFIGURATIONS 44-Pin SOJ NC 1 44 A0 A14 2 43 A1 A13 3 42 A2 A12 4 41 OE A11 5 40 UB CE 6 39 LB I/O0 7 38 I/O15 I/O1 8 37 I/O14 I/O2 9 36 I/O13 I/O3 10 35 I/O12 VDD 11 34 GND GND 12 33 VDD I/O4 13 32 I/O11 I/O5 14 31 I/O10 I/O6 15 30 I/O9 I/O7 16 29 I/O8 WE 17 28 NC A10 18 27 A3 A9 19 26 A4 A8 20 25 A5 A7 21 24 A6 NC 22 23 NC 44-Pin TSOP (Type II) NC A14 A13 A12 A11 CE I/O0 I/O1 I/O2 I/O3 VDD GND I/O4 I/O5 I/O6 I/O7 WE A10 A9 A8 A7 NC 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 A0 A1 A2 OE UB LB I/O15 I/O14 I/O13 I/O12 GND VDD I/O11 I/O10 I/O9 I/O8 NC A3 A4 A5 A6 NC PIN DESCRIPTIONS 2 A0-A14 Address Inputs LB Lower-byte Control (I/O0-I/O7) I/O0-I/O15 Data Inputs/Outputs UB Upper-byte Control (I/O8-I/O15) CE Chip Enable Input NC No Connection OE Output Enable Input VDD Power WE Write Enable Input GND Ground Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A1 01/22/2020 IS61C3216AL TRUTH TABLE Mode Not Selected Output Disabled Read Write I/O PIN I/O0-I/O7 I/O8-I/O15 WE CE OE LB UB X H X H H H L L L H L L L L L L L L X H X L L L X X X X X H L H L L H L X X H H L L H L L High-Z High-Z High-Z DOUT High-Z DOUT DIN High-Z DIN Value –0.5 to +7.0 –65 to +150 1.5 20 Unit V °C W mA High-Z High-Z High-Z High-Z DOUT DOUT High-Z DIN DIN VDD Current ISB1, ISB2 ICC1, ICC2 ICC1, ICC2 ICC1, ICC2 ABSOLUTE MAXIMUM RATINGS(1) Symbol VTERM TSTG PT IOUT Parameter Terminal Voltage with Respect to GND Storage Temperature Power Dissipation DC Output Current (LOW) Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. OPERATING RANGE (IS61C3216AL) Range Commercial Ambient Temperature 0°C to +70°C VDD 5V ± 10% Industrial -40°C to +85°C 5V ± 10% Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A1 01/22/2020 3 IS61C3216AL CAPACITANCE(1,2) Symbol Parameter CIN Input Capacitance COUT Output Capacitance Conditions Max. Unit VIN = 0V 5 pF VOUT = 0V 7 pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25°C, f = 1 MHz, VDD = 5.0V. DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Symbol Parameter Test Conditions Min. Max. Unit VOH Output HIGH Voltage VDD = Min., IOH = –4.0 mA 2.4 — V VOL Output LOW Voltage VDD = Min., IOL = 8.0 mA — 0.4 V VIH Input HIGH Voltage 2.2 VDD + 0.5 V VIL Input LOW Voltage(1) –0.3 0.8 V ILI Input Leakage GND ≤ VIN ≤ VDD Com. Ind. –1 –2 1 2 µA ILO Output Leakage GND ≤ VOUT ≤ VDD Outputs Disabled Com. Ind. –1 –2 1 2 µA Note: 1. VIL = –3.0V for pulse width less than 10 ns. 4 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A1 01/22/2020 IS61C3216AL IS61C3216AL POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) -12 ns Min. Max. Symbol Parameter Test Conditions Unit ICC1 VDD Operating Supply Current VDD = VDD MAX., CE = VIL IOUT = 0 mA, f = 0 Com. Ind. — — 40 45 mA ICC2 VDD Dynamic Operating Supply Current VDD = VDD MAX., CE = VIL IOUT = 0 mA, f = fMAX Com. Ind. typ.(2) — — 50 55 mA 35 ISB1 TTL Standby Current (TTL Inputs) VDD = VDD MAX., VIN = VIH or VIL CE ≥ VIH, f = 0 Com. Ind. — — 1 1 mA ISB2 CMOS Standby Current (CMOS Inputs) VDD = VDD MAX., CE ≤ VDD – 0.2V, VIN ≥ VDD – 0.2V, or VIN ≤ 0.2V, f = 0 Com. Ind. typ.(2) — — 350 400 µA 200 Note: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. Typical values are measured at VDD = 5V, TA = 25oC and not 100% tested. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A1 01/22/2020 5 IS61C3216AL READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) Symbol tRC tAA tOHA tACE tDOE tHZOE(2) tLZOE(2) tHZCE(2 tLZCE(2) tBA tHZB tLZB -12 Min. Max. 12 — Parameter Read Cycle Time Unit ns Address Access Time — 12 ns Output Hold Time 3 — ns CE Access Time — 12 ns OE Access Time — 6 ns OE to High-Z Output 0 6 ns OE to Low-Z Output 0 — ns CE to High-Z Output 0 7 ns CE to Low-Z Output 2 — ns LB, UB Access Time — 6 ns LB, UB to High-Z Output 0 6 ns LB, UB to Low-Z Output 0 — ns Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3. Not 100% tested. AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0V to 3.0V 3 ns 1.5V See Figures 1 and 2 AC TEST LOADS 480 Ω 480 Ω 5V 5V OUTPUT OUTPUT 30 pF Including jig and scope Figure 1 6 255 Ω 5 pF Including jig and scope 255 Ω Figure 2 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A1 01/22/2020 IS61C3216AL AC WAVEFORMS READ CYCLE NO. 1(1,2) (Address Controlled) (CE = OE = VIL, UB or LB = VIL) t RC ADDRESS t AA t OHA t OHA DOUT DATA VALID PREVIOUS DATA VALID READ1.eps READ CYCLE NO. 2(1,3) t RC ADDRESS t AA t OHA OE t HZOE t DOE t LZOE CE t ACE t HZCE t LZCE LB, UB DOUT HIGH-Z t LZB t BA t HZB DATA VALID UB_CEDR2.eps Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE, UB, or LB = VIL. 3. Address is valid prior to or coincident with CE LOW transition. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A1 01/22/2020 7 IS61C3216AL WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range) Symbol Parameter -12 Min. Max. Unit tWC Write Cycle Time 12 — ns tSCE CE to Write End 9 — ns tAW Address Setup Time to Write End 9 — ns tHA Address Hold from Write End 0 — ns tSA Address Setup Time 0 — ns tPWB LB, UB Valid to End of Write 9 — ns tPWE1 WE Pulse Width (OE =High) 9 — ns tPWE2 WE Pulse Width (OE=Low) 9 — ns tSD Data Setup to Write End 6 — ns tHD Data Hold from Write End 0 — ns tHZWE(2) WE LOW to High-Z Output — 6 ns tLZWE(2) WE HIGH to Low-Z Output 3 — ns Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. 8 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A1 01/22/2020 IS61C3216AL AC WAVEFORMS WE Controlled)(1,2) WRITE CYCLE NO. 1 (WE t WC VALID ADDRESS ADDRESS t SA t SCE t HA CE t AW t PWE1 t PWE2 WE t PBW UB, LB t HZWE DOUT DATA UNDEFINED t LZWE HIGH-Z t SD DIN t HD DATAIN VALID UB_CEWR1.eps Notes: 1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CE and WE inputs and at least one of the LB and UB inputs being in the LOW state. 2. WRITE = (CE) [ (LB) = (UB) ] (WE). Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A1 01/22/2020 9 IS61C3216AL WRITE CYCLE NO. 2 (OE is HIGH During Write Cycle) (1,2) t WC ADDRESS VALID ADDRESS t HA OE CE LOW t AW t PWE1 WE t SA t PBW UB, LB t HZWE DOUT t LZWE HIGH-Z DATA UNDEFINED t SD t HD DATAIN VALID DIN UB_CEWR2.eps WRITE CYCLE NO. 3 (OE is LOW During Write Cycle) (1) t WC ADDRESS VALID ADDRESS OE LOW CE LOW t HA t AW t PWE2 WE t SA t PBW UB, LB t HZWE DOUT DATA UNDEFINED t LZWE HIGH-Z t SD DIN t HD DATAIN VALID UB_CEWR3.eps Notes: 1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. 2. I/O will assume the High-Z state if OE ≥ VIH. 10 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A1 01/22/2020 IS61C3216AL WRITE CYCLE NO. 4 (UB/LB Back to Back Write) t WC ADDRESS t WC ADDRESS 1 ADDRESS 2 OE t SA CE LOW t HA t SA WE UB, LB t HA t PBW t PBW WORD 1 WORD 2 t HZWE DOUT t LZWE HIGH-Z DATA UNDEFINED t HD t SD DIN t HD t SD DATAIN VALID DATAIN VALID UB_CEWR4.eps Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A1 01/22/2020 11 IS61C3216AL DATA RETENTION SWITCHING CHARACTERISTICS Symbol Parameter Test Condition Min. VDR VDD for Data Retention See Data Retention Waveform 2.0 IDR Data Retention Current VDD = 2.0V, CE ≥ VDD – 0.2V VIN ≥ VDD – 0.2V, or VIN ≤ VSS + 0.2V tSDR Data Retention Setup Time See Data Retention Waveform tRDR Recovery Time See Data Retention Waveform Com. Ind. typ.(1) Max. Unit 5.5 V 350 400 µA 0 — ns tRC — ns — — Typ. — — 200 Note: 1. Typical Values are measured at VDD = 5V, TA = 25oC and not 100% tested. CE Controlled) DATA RETENTION WAVEFORM (CE tSDR Data Retention Mode tRDR VDD 4.5V 2.2V VDR CE GND 12 CE ≥ VDD - 0.2V Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A1 01/22/2020 IS61C3216AL ORDERING INFORMATION: IS61C3216AL Industrial Range: –40°C to +85°C Speed (ns) 12 Order Part No. Package IS61C3216AL-12KLI IS61C3216AL-12TLI 400-mil Plastic SOJ, Lead-free 44-pin TSOP-II, Lead-free Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A1 01/22/2020 13 SEATING PLANE 4. Formed leads shall be planar with respect to one another within 0.1mm at the seating plane after final test. 5. Reference document : JEDEC SPEC MS-027. 3. Dimension b2 does not include dambar protrusion/intrusion. 2. Dimension D and E1 do not include mold protrusion . 1. Controlling dimension : mm NOTE : 12/21/2007 Θ Package Outline 06/04/2008 3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION/INTRUSION. 2. DIMENSION D AND E1 DO NOT INCLUDE MOLD PROTRUSION. 1. CONTROLLING DIMENSION : MM NOTE : Θ