IS61C64AL

IS61C64AL 8K x 8 HIGH-SPEED CMOS STATIC RAM FEATURES • High-speed access time: 10 ns • CMOS low power operation — 1 mW (typical) CMOS standby — 125 mW (typical) operating • TTL compatible interface levels • Single 5V power supply • Fully static operation: no clock or refresh required • Lead-free available ISSI OCTOBER 2006 ® DESCRIPTION The ISSI IS61C64AL is a very high-speed, low power, 8192-word by 8-bit static RAM. It is fabricated using ISSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields access times as fast as 10 ns with low power consumption. When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation can be reduced down to 150 µW (typical) with CMOS input levels. Easy memory expansion is provided by using one Chip Enable input, CE. The active LOW Write Enable (WE) controls both writing and reading of the memory. The IS61C64AL is packaged in the JEDEC standard 28pin, 300-mil SOJ, and TSOP. FUNCTIONAL BLOCK DIAGRAM A0-A12 DECODER 8K x 8 MEMORY ARRAY VDD GND I/O DATA CIRCUIT I/O0-I/O7 COLUMN I/O CE OE WE CONTROL CIRCUIT Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. B 10/23/06 1 IS61C64AL TRUTH TABLE Mode Not Selected (Power-down) Output Disabled Read Write WE X H H L CE H L L L OE X H L X I/O Operation High-Z High-Z DOUT DIN VDD Current ISB1, ISB2 ICC ICC ICC ISSI ® PIN CONFIGURATION 28-Pin SOJ NC A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VDD WE NC A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 PIN CONFIGURATION 28-Pin TSOP (Type 1) OE A11 A9 A8 NC WE VDD NC A12 A7 A6 A5 A4 A3 22 23 24 25 26 27 28 1 2 3 4 5 6 7 21 20 19 18 17 16 15 14 13 12 11 10 9 8 A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 PIN DESCRIPTIONS A0-A12 CE OE WE I/O0-I/O7 NC VDD GND Address Inputs Chip Enable 1 Input Output Enable Input Write Enable Input Input/Output No Connect Power Ground 2 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. B 10/23/06 IS61C64AL ABSOLUTE MAXIMUM RATINGS(1) Symbol VTERM TSTG PT IOUT Parameter Terminal Voltage with Respect to GND Storage Temperature Power Dissipation DC Output Current (LOW) Value –0.5 to +7.0 –65 to +150 1.5 20 Unit V °C W mA ISSI ® 1 2 3 4 Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. OPERATING RANGE Range Commercial Industrial Ambient Temperature 0°C to +70°C –40°C to +85°C Speed -10 -10 VDD(1) 5V ± 5% 5V ± 5% 5 6 Min. 2.4 — 2.2 –0.3 Max. — 0.4 VDD + 0.5 0.8 1 2 1 2 Unit V V V V µA µA Note: 1. If operated at 12ns, VDD range is 5V + 10%. DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Symbol Parameter VOH VOL VIH VIL ILI ILO Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage(1) Input Leakage Output Leakage GND ≤ VIN ≤ VDD GND ≤ VOUT ≤ VDD, Outputs Disabled Com. Ind. Com. Ind. Test Conditions VDD = Min., IOH = –4.0 mA VDD = Min., IOL = 8.0 mA 7 8 9 10 11 12 –1 –2 –1 –2 Note: 1. VIL = –3.0V for pulse width less than 10 ns. Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. B 10/23/06 3 IS61C64AL POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) Symbol ICC1 ICC2 Parameter VDD Operating Supply Current VDD Dynamic Operating Supply Current TTL Standby Current (TTL Inputs) CMOS Standby Current (CMOS Inputs) Test Conditions VDD = Max., CE = VIL IOUT = 0 mA, f = 0 VDD = Max., CE = VIL IOUT = 0 mA, f = fMAX VDD = Max., VIN = VIH or VIL CE ≥ VIH, f = 0 VDD = Max., CE ≥ VDD – 0.2V, VIN ≥ VDD – 0.2V, or VIN ≤ 0.2V, f = 0 Com. Ind. Com. Ind. typ.(2) Com. Ind. Com. Ind. typ.(2) -10 Min. Max. — — — — 25 — — 1 2 — — — — 20 25 45 50 ISSI -12 Min. Max. — — — — 25 1 2 350 450 200 mA 20 25 35 45 Unit mA mA ® ISB1 ISB2 — 350 — 450 200 µA Note: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. Typical values are measured at VDD = 5V, TA = 25oC. Not 100% tested. CAPACITANCE(1,2) Symbol CIN COUT Parameter Input Capacitance Output Capacitance Conditions VIN = 0V VOUT = 0V Max. 8 10 Unit pF pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25°C, f = 1 MHz, VDD = 5.0V. 4 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. B 10/23/06 IS61C64AL READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter Read Cycle Time Address Access Time Output Hold Time CE Access Time OE Access Time (2) ISSI -10 ns Min. Max 10 — 2 — — 0 — 2 — 0 — — 10 — 10 6 — 5 — 5 — 10 -12 ns Min. Max. 12 — 2 — — 0 — 3 — 0 — — 12 — 12 6 — 6 — 7 — 12 Unit ns ns ns ns ns ns ns ns ns ns ns ® 1 2 3 4 5 6 7 tRC tAA tOHA tACS tDOE tLZOE tHZOE(2) tLZCS(2) tHZCS tPU(3) tPD(3) (2) OE to Low-Z Output OE to High-Z Output CE to Low-Z Output CE to High-Z Output CE to Power-Up CE to Power-Down Notes: 1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3. Not 100% tested. AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Levels Output Load Unit 0V to 3.0V 3 ns 1.5V See Figures 1 and 2 8 9 480 Ω 5V AC TEST LOADS 480 Ω 5V 10 11 OUTPUT 30 pF Including jig and scope 255 Ω OUTPUT 5 pF Including jig and scope 255 Ω 12 Figure 1 Figure 2 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. B 10/23/06 5 IS61C64AL ISSI t RC ® AC WAVEFORMS READ CYCLE NO. 1(1,2) ADDRESS t AA t OHA DOUT PREVIOUS DATA VALID t OHA DATA VALID READ1.eps READ CYCLE NO. 2(1,3) t RC ADDRESS t AA OE t OHA t DOE CE t HZOE t LZOE t ACS t LZCS t HZCS DATA VALID CE_RD2.eps DOUT HIGH-Z Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE = VIL. 3. Address is valid prior to or coincident with CE LOW transitions. 6 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. B 10/23/06 IS61C64AL WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range) Symbol Parameter Write Cycle Time CE to Write End Address Setup Time to Write End Address Hold from Write End Address Setup Time WE Pulse Width (OE LOW) WE Pulse Width (OE HIGH) Data Setup to Write End Data Hold from Write End (2) ISSI -10 ns Min. Max 10 9 9 0 0 9 8 7 0 — 0 — — — — — — — — — 6 — -12 ns Min. Max. 12 10 10 0 0 9 8 7 0 — 0 — — — — — — — — — 6 — Unit ns ns ns ns ns ns ns ns ns ns ns ® tWC tSCS tAW tHA tSA tPWE1 tPWE2 tSD tHD tHZWE tLZWE (2) 1 2 3 4 5 6 7 8 WE LOW to High-Z Output WE HIGH to Low-Z Output Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. AC WAVEFORMS WRITE CYCLE NO. 1 (WE Controlled)(1,2) t WC ADDRESS VALID ADDRESS t SA CE t SCS t HA 9 10 WE t AW t PWE1 t PWE2 t HZWE t LZWE HIGH-Z 11 12 CE_WR1.eps DOUT DATA UNDEFINED t SD DIN t HD DATAIN VALID Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. B 10/23/06 7 IS61C64AL WRITE CYCLE NO. 2 (OE is HIGH During Write Cycle) (1,2) t WC ADDRESS VALID ADDRESS ISSI t HA ® OE CE LOW t AW t PWE1 WE t SA DOUT DATA UNDEFINED t HZWE HIGH-Z t LZWE t SD DIN t HD DATAIN VALID CE_WR2.eps WRITE CYCLE NO. 3 (OE is LOW During Write Cycle) (1) t WC ADDRESS OE CE VALID ADDRESS LOW t HA LOW t AW t PWE2 WE t SA DOUT DATA UNDEFINED t HZWE HIGH-Z t LZWE t SD DIN t HD DATAIN VALID CE_WR3.eps Notes: 1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. 2. I/O will assume the High-Z state if OE ≥ VIH. 8 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. B 10/23/06 IS61C64AL ISSI Test Condition See Data Retention Waveform VDD = 2.0V, CE ≥ VDD – 0.2V VIN ≥ VDD – 0.2V, or VIN ≤ VSS + 0.2V See Data Retention Waveform See Data Retention Waveform Com. Ind. Min. 2.0 — — 0 50 Typ.(1) Max. 5.5 90 100 — — Unit V µA ns ns ® DATA RETENTION SWITCHING CHARACTERISTICS Symbol Parameter VDD for Data Retention Data Retention Current Data Retention Setup Time Recovery Time VDR IDR 1 2 3 4 tSDR tRDR Note: tRC 1. Typical Values are measured at VDD = 5V, TA = 25oC and not 100% tested. DATA RETENTION WAVEFORM (CE Controlled) tSDR VDD 4.5V Data Retention Mode tRDR 5 6 2.2V VDR CE ≥ VDD - 0.2V CE GND 7 8 9 10 11 12 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. B 10/23/06 9 IS61C64AL ISSI Package 300-mil Plastic SOJ 300-mil Plastic SOJ, Lead-free Plastic TSOP Plastic TSOP, Lead-free ® ORDERING INFORMATION Industrial Range: -40°C to +85°C Speed (ns) 10 Order Part No. IS61C64AL-10JI IS61C64AL-10JLI IS61C64AL-10TI IS61C64AL-10TLI 10 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. B 10/23/06 PACKAGING INFORMATION 300-mil Plastic SOJ Package Code: J N ISSI ® E1 E 1 D A SEATING PLANE B A2 C e b A1 E2 MILLIMETERS Sym. N0. Leads A A1 A2 b B C D E E1 E2 e — 0.64 2.41 0.41 0.66 0.20 17.02 8.26 7.49 6.27 INCHES Min. Typ. Max. Min. Typ. Max. 24/26 — — — — — — — — — — 3.56 — 2.67 0.51 0.81 0.25 17.27 8.76 7.75 7.29 Notes: 1. Controlling dimension: inches, unless otherwise specified. 2. BSC = Basic lead spacing between centers. 3. Dimensions D and E1 do not include mold flash protrusions and should be measured from the bottom of the package. 4. Formed leads shall be planar with respect to one another within 0.004 inches at the seating plane. — 0.025 0.095 0.016 0.026 0.008 0.670 0.325 0.295 0.247 — 0.140 — — — — — — — — — — 0.105 0.020 0.032 0.010 0.680 0.345 0.305 0.287 1.27 BSC 0.050 BSC Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. D 02/25/03 PACKAGING INFORMATION 300-mil Plastic SOJ Package Code: J ISSI ® MILLIMETERS Sym. N0. Leads A A1 A2 b B C D E E1 E2 e — 0.64 2.41 0.41 0.66 0.20 18.29 8.26 7.49 6.27 INCHES Min. Typ. Max. Sym. N0. Leads MILLIMETERS Min. Typ. Max. 32 — 0.64 2.41 0.41 0.66 0.20 20.83 8.26 7.49 6.27 — — — — — — — — — — 3.56 — 2.67 0.51 0.81 0.25 21.08 8.76 7.75 7.29 — INCHES Min. Typ. Max. Min. Typ. Max. 28 — — — — — — — — — — 3.56 — 2.67 0.51 0.81 0.25 18.54 8.76 7.75 7.29 — 0.025 0.095 0.016 0.026 0.008 0.720 0.325 0.295 0.247 — — — — — — — — — — 0.140 — 0.105 0.020 0.032 0.010 0.730 0.345 0.305 0.287 A A1 A2 b B C D E E1 E2 e — — — — — — — — — — 0.140 — 0.105 0.020 0.032 0.010 0.830 0.345 0.305 0.287 0.025 0.095 0.016 0.026 0.008 0.820 0.325 0.295 0.247 1.27 BSC 0.050 BSC 1.27 BSC 0.050 BSC 2 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. D 02/25/03 PACKAGING INFORMATION Plastic TSOP - 28-pins Package Code: T (Type I) 1 ISSI ® E H N D SEATING PLANE S A e B L A1 α C Symbol Ref. Std. No. Leads A A1 B C D E H e L α Plastic TSOP (T—Type I) Millimeters Inches Min Max Min Max 28 1.00 1.20 0.05 0.20 0.16 0.27 0.10 0.20 7.90 8.10 11.70 11.90 13.20 13.60 0.55 BSC 0.30 0.70 0° 5° 0.037 0.047 0.002 0.008 0.006 0.011 0.004 0.008 0.308 0.316 0.456 0.465 0.515 0.531 0.022 BSC 0.011 0.027 0° 5° Notes: 1. Controlling dimension: millimeters, unless otherwise specified. 2. BSC = Basic lead spacing between centers. 3. Dimensions D and E do not include mold flash protrusions and should be measured from the bottom of the package. 4. Formed leads shall be planar with respect to one another within 0.004 inches at the seating plane. Integrated Silicon Solution, Inc. PK13197T28 Rev. B 01/31/97