IS61LF51236A-7.5B3I-TR

IS61LF25672A IS61VF25672A IS61LF51236A IS61VF51236A IS61LF102418A IS61VF102418A 256K x 72, 512K x 36, 1024K x 18 18Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs and data outputs • Auto Power-down during deselect • Single cycle deselect • Snooze MODE for reduced-power standby • JTAG Boundary Scan for PBGA package • Power Supply LF: VDD 3.3V + 5%, VDDQ 3.3V/2.5V + 5% VF: VDD 2.5V + 5%, VDDQ 2.5V + 5% • JEDEC 100-Pin TQFP, 119-pin PBGA, 209-Ball PBGA and 165-pin PBGA packages. • Lead-free available JULY 2010 DESCRIPTION The ISSI IS61LF/VF25672A, IS61LF/VF51236A and IS61LF/VF102418A are high-speed, low-power synchronous static RAMs designed to provide burstable, highperformance memory for communication and networking applications. The IS61LF/VF25672A is organized as 262,144 words by 72 bits. The IS61LF/VF51236A is organized as 524,288 words by 36 bits. The IS61LF/VF102418A is organized as 1,048,576 words by 18 bits. Fabricated with ISSI's advanced CMOS technology, the device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input. Write cycles are internally self-timed and are initiated by the rising edge of the clock input. Write cycles can be one to four bytes wide as controlled by the write control inputs. Separate byte enables allow individual bytes to be written. Byte write operation is performed by using byte write enable (BWE) input combined with one or more individual byte write signals (BWx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the byte write controls. Bursts can be initiated with either ADSP (Address Status Processor) or ADSC (Address Status Cache Controller) input pins. Subsequent burst addresses can be generated internally and controlled by the ADV (burst address advance) input pin. The mode pin is used to select the burst sequence order, Linear burst is achieved when this pin is tied LOW. Interleave burst is achieved when this pin is tied HIGH or left floating. FAST ACCESS TIME Symbol tKQ tKC Parameter Clock Access Time Cycle Time Frequency -6.5 6.5 7.5 133 -7.5 7.5 8.5 117 Units ns ns MHz Copyright © 2010 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc. Rev. K 07/29/2010 1 IS61LF25672A IS61VF25672A IS61LF51236A IS61LF102418A IS61VF51236A IS61VF102418A BLOCK DIAGRAM MODE Q0 CLK CLK A0 A0' BINARY COUNTER CE ADV ADSC ADSP Q1 A1' 256Kx72; 512Kx36; 1024Kx18; MEMORY ARRAY A1 CLR 19/20 17/18 D A 19/20 Q ADDRESS REGISTER CE CLK 36,18 or 72 GW BWE BW(a-h) x18: a,b x36: a-d x72: a-h D 36,18 or 72 Q DQ(a-d) BYTE WRITE REGISTERS CLK CE 36,18 or 72 2/4/8 D CE2 CE2 Q ENABLE REGISTER INPUT REGISTERS CLK DQa - DQd OE CE CLK ZZ POWER DOWN OE 2 Integrated Silicon Solution, Inc. Rev. K 07/29/2010 IS61LF25672A IS61VF25672A IS61LF51236A IS61LF102418A IS61VF51236A IS61VF102418A 165-PIN BGA 119-PIN BGA 165-Ball, 13x15 mm BGA 119-Ball, 14x22 mm BGA BOTTOM VIEW BOTTOM VIEW 209-BALL BGA 209-Ball, 14 mm x 22 mm BGA 1 mm Ball Pitch, 11 x 19 Ball Array BOTTOM VIEW Integrated Silicon Solution, Inc. Rev. K 07/29/2010 3 IS61LF25672A IS61VF25672A IS61LF51236A IS61LF102418A IS61VF51236A IS61VF102418A PIN CONFIGURATION — 256K X 72, 209-Ball PBGA (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 A DQg DQg A CE2 ADSP ADSC ADV CE2 A DQb DQb B DQg DQg BWc BWg NC BWE A BWb BWf DQb DQb C DQg DQg BWh BWd NC CE NC BWe BWa DQb DQb D DQg DQg VSS NC NC OE GW NC VSS DQb DQb E DQPg DQPc VDDQ VDDQ VDD VDD VDD VDDQ VDDQ DQPf DQPb F DQc DQc VSS VSS VSS NC VSS VSS VSS DQf DQf G DQc DQc VDDQ VDDQ VDD NC VDD VDDQ VDDQ DQf DQf H DQc DQc VSS VSS VSS NC VSS VSS VSS DQf DQf J DQc DQc VDDQ VDDQ VDD NC VDD VDDQ VDDQ DQf DQf K NC NC CLK NC VSS NC VSS NC NC NC NC L DQh DQh VDDQ VDDQ VDD NC VDD VDDQ VDDQ DQa DQa M DQh DQh VSS VSS VSS NC VSS VSS VSS DQa DQa N DQh DQh VDDQ VDDQ VDD NC VDD VDDQ VDDQ DQa DQa P DQh DQh VSS VSS VSS ZZ VSS VSS VSS DQa DQa R DQPd DQPh VDDQ VDDQ VDD VDD VDD VDDQ VDDQ DQPa DQPe T DQd DQd VSS NC NC MODE NC NC VSS DQe DQe U DQd DQd NC A A A A A NC DQe DQe V DQd DQd A A A A1 A A A DQe DQe W DQd DQd TMS TDI A A0 A TDO TCK DQe DQe 11 x 19 Ball BGA—14 x 22 mm2 Body—1 mm Ball Pitch PIN DESCRIPTIONS Symbol A Pin Name Address Inputs Symbol Pin Name BWE Byte Write Enable A0, A1 Synchronous Burst Address Inputs ADV OE Output Enable ZZ Power Sleep Mode ADSP Synchronous Burst Address Advance Address Status Processor MODE Burst Sequence Selection ADSC Address Status Controller JTAG Pins GW Global Write Enable CLK Synchronous Clock CE, CE2, CE2 Synchronous Chip Select BWx (x=a,b,c,d e,f,g,h) Synchronous Byte Write Controls TCK, TDO TMS, TDI NC DQx DQPx VDD VDDQ Vss 4 No Connect Data Inputs/Outputs Data Inputs/Outputs 3.3V/2.5V Power Supply Isolated Output Power Supply 3.3V/2.5V Ground Integrated Silicon Solution, Inc. Rev. K 07/29/2010 IS61LF25672A IS61VF25672A IS61LF51236A IS61LF102418A IS61VF51236A IS61VF102418A 119 BGA PACKAGE PIN CONFIGURATION-512K X 36 (TOP VIEW) 1 2 3 4 5 6 7 A B C D E F G H J K VDDQ NC NC DQc DQc VDDQ DQc DQc VDDQ DQd A A A DQPc DQc DQc DQc DQc VDD DQd A A A Vss Vss Vss BWc Vss NC Vss ADSP ADSC VDD NC CE OE ADV GW VDD CLK A A A Vss Vss Vss BWb Vss NC Vss A A A DQPb DQb DQb DQb DQb VDD DQa VDDQ NC NC DQb DQb VDDQ DQb DQb VDDQ DQa L M N P R T U DQd VDDQ DQd DQd NC NC VDDQ DQd DQd DQd DQPd A NC TMS BWd Vss Vss Vss MODE A TDI NC BWE A1 * A0 * VDD A TCK BWa Vss Vss Vss NC A TDO DQa DQa DQa DQPa A NC NC DQa VDDQ DQa DQa NC ZZ VDDQ Note: * A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired. PIN DESCRIPTIONS Pin Name Address Inputs Symbol OE Pin Name Output Enable A0, A1 Synchronous Burst Address Inputs ADV ADSP Synchronous Burst Address Advance. Address Status Processor Power Sleep Mode Burst Sequence Selection JTAG Pins ADSC Address Status Controller GW Global Write Enable CLK Synchronous Clock CE Synchronous Chip Select BWx (x=a-d) Synchronous Byte Write Controls ZZ MODE TCK, TDO TMS, TDI NC DQa-DQd DQPa-Pd VDD VDDQ No Connect Data Inputs/Outputs Data Inputs/Outputs Power Supply Output Power Supply BWE Vss Ground Symbol A Byte Write Enable Integrated Silicon Solution, Inc. Rev. K 07/29/2010 5 IS61LF25672A IS61VF25672A IS61LF51236A IS61LF102418A IS61VF51236A IS61VF102418A 119 BGA PACKAGE PIN CONFIGURATION 1MX18 (TOP VIEW) A B C D E F G H J K L M N P R T U 1 2 3 4 5 6 7 VDDQ NC NC DQb NC VDDQ NC DQb VDDQ NC DQb VDDQ DQb NC NC NC VDDQ A A A NC DQb NC DQb NC VDD DQb NC DQb NC DQPb A A TMS A A A Vss Vss Vss BWb Vss NC Vss Vss Vss Vss Vss MODE A TDI ADSP ADSC VDD NC CE OE ADV GW VDD CLK NC BWE A1 * A0* VDD NC TCK A A A Vss Vss Vss Vss Vss NC Vss BWa Vss Vss Vss NC A TDO A A A DQPa NC DQa NC DQa VDD NC DQa NC DQa NC A A NC VDDQ NC NC NC DQa VDDQ DQa NC VDDQ DQa NC VDDQ NC DQa NC ZZ VDDQ Note: * A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired. PIN DESCRIPTIONS 6 Symbol A Pin Name Address Inputs Symbol OE Pin Name Output Enable A0, A1 Synchronous Burst Address Inputs ADV ADSP Synchronous Burst Address Advance. Address Status Processor ZZ MODE TCK, TDO TMS, TDI Power Sleep Mode Burst Sequence Selection JTAG Pins ADSC Address Status Controller GW Global Write Enable CLK Synchronous Clock CE Synchronous Chip Select BWx (x=a,b) Synchronous Byte Write Controls NC DQa-DQb DQPa-Pb VDD VDDQ No Connect Data Inputs/Outputs Data Inputs/Outputs Power Supply Output Power Supply BWE Vss Ground Byte Write Enable Integrated Silicon Solution, Inc. Rev. K 07/29/2010 IS61LF25672A IS61VF25672A IS61LF51236A IS61LF102418A IS61VF51236A IS61VF102418A 165 PBGA PACKAGE PIN CONFIGURATION 512K X 36 (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 A NC A CE BWc BWb CE2 BWE ADSC ADV A NC B NC A CE2 BWd BWa CLK GW OE ADSP A NC C DQPc NC VDDQ Vss Vss Vss Vss Vss VDDQ NC D DQc DQc VDDQ VDD Vss Vss Vss VDD VDDQ DQb DQb E DQc DQc VDDQ VDD Vss Vss Vss VDD VDDQ DQb DQb F DQc DQc VDDQ VDD Vss Vss Vss VDD VDDQ DQb DQb G DQc DQc VDDQ VDD Vss Vss Vss VDD VDDQ DQb DQb H NC Vss NC VDD Vss Vss Vss VDD NC NC ZZ J DQd DQd VDDQ VDD Vss Vss Vss VDD VDDQ DQa DQa K DQd DQd VDDQ VDD Vss Vss Vss VDD VDDQ DQa DQa L DQd DQd VDDQ VDD Vss Vss Vss VDD VDDQ DQa DQa M DQd DQd VDDQ VDD Vss Vss Vss VDD VDDQ DQa DQa N DQPd NC VDDQ Vss NC A Vss Vss VDDQ NC DQPa P NC NC A A TDI A1* TDO A A A A R MODE NC A A TMS A0* TCK A A A A DQPb Note: * A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired. PIN DESCRIPTIONS Symbol A Pin Name Address Inputs Symbol Pin Name BWE Byte Write Enable A0, A1 Synchronous Burst Address Inputs OE Output Enable ADV ZZ Power Sleep Mode MODE Burst Sequence Selection ADSP Synchronous Burst Address Advance. Address Status Processor JTAG Pins ADSC Address Status Controller GW Global Write Enable CLK Synchronous Clock CE, CE2, CE2 Synchronous Chip Select TCK, TDO TMS, TDI NC DQa-DQd DQPa-Pd VDD VDDQ BWx (x=a,b,c,d) Synchronous Byte Write Controls Vss Integrated Silicon Solution, Inc. Rev. K 07/29/2010 No Connect Data Inputs/Outputs Data Inputs/Outputs Power Supply Output Power Supply Ground 7 IS61LF25672A IS61VF25672A IS61LF51236A IS61LF102418A IS61VF51236A IS61VF102418A 165 PBGA PACKAGE PIN CONFIGURATION 1M X 18 (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 A NC A CE BWb NC CE2 BWE ADSC ADV A A B NC A CE2 NC BWa CLK GW OE ADSP A NC C NC NC VDDQ Vss Vss Vss Vss Vss VDDQ NC DQPa D NC DQb VDDQ VDD Vss Vss Vss VDD VDDQ NC DQa E NC DQb VDDQ VDD Vss Vss Vss VDD VDDQ NC DQa F NC DQb VDDQ VDD Vss Vss Vss VDD VDDQ NC DQa G NC DQb VDDQ VDD Vss Vss Vss VDD VDDQ NC DQa H NC Vss NC VDD Vss Vss Vss VDD NC NC ZZ J DQb NC VDDQ VDD Vss Vss Vss VDD VDDQ DQa NC K DQb NC VDDQ VDD Vss Vss Vss VDD VDDQ DQa NC L DQb NC VDDQ VDD Vss Vss Vss VDD VDDQ DQa NC M DQb NC VDDQ VDD Vss Vss Vss VDD VDDQ DQa NC N DQPb NC VDDQ Vss NC A Vss Vss VDDQ NC NC P NC NC A A TDI A1* TDO A A A A R MODE NC A A TMS A0* TCK A A A A Note: * A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired. PIN DESCRIPTIONS Symbol A Pin Name Address Inputs Symbol BWE Byte Write Enable A0, A1 Synchronous Burst Address Inputs OE Output Enable ADV ZZ Power Sleep Mode MODE Burst Sequence Selection ADSP Synchronous Burst Address Advance. Address Status Processor JTAG Pins ADSC Address Status Controller GW Global Write Enable CLK Synchronous Clock CE, CE2, CE2 Synchronous Chip Select BWx (x=a,b) Synchronous Byte Write Controls TCK, TDO TMS, TDI NC DQa-DQd DQPa-Pd VDD VDDQ Vss 8 Pin Name No Connect Data Inputs/Outputs Data Inputs/Outputs Power Supply Output Power Supply Ground Integrated Silicon Solution, Inc. Rev. K 07/29/2010 IS61LF25672A IS61VF25672A IS61LF51236A IS61LF102418A IS61VF51236A IS61VF102418A PIN CONFIGURATION A A CE CE2 BWd BWc BWb BWa CE2 VDD VSS CLK GW BWE OE ADSC ADSP ADV A A 100-Pin TQFP DQPc DQPb DQb DQb VDDQ VSS DQb DQb DQb DQb VSS VDDQ DQb DQb VSS NC VDD ZZ DQa DQa VDDQ VSS DQa DQa DQa DQa VSS VDDQ DQa DQa DQPa MODE A A A A A1 A0 NC NC VSS VDD A A A A A A A A A DQc DQc VDDQ VSS DQc DQc DQc DQc VSS VDDQ DQc DQc NC VDD NC VSS DQd DQd VDDQ VSS DQd DQd DQd DQd VSS VDDQ DQd DQd DQPd 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 1 79 2 78 3 77 4 76 5 75 6 74 7 73 8 72 9 71 10 70 11 69 12 68 13 67 14 66 15 65 16 64 17 63 18 62 19 61 20 60 21 59 22 58 23 57 24 56 25 55 26 54 27 53 28 52 29 51 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 512K x 36 PIN DESCRIPTIONS A0, A1 Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus. DQPa-DQPd Parity Data Input/Output Vss Ground GW Synchronous Global Write Enable MODE Burst Sequence Mode Selection OE Output Enable A Synchronous Address Inputs ADSC Synchronous Controller Address Status ADSP Synchronous Processor Address Status ADV Synchronous Burst Address Advance TMS, TDI, TCK, TDO JTAG Boundary Scan Pins BWa-BWd Synchronous Byte Write Enable VDD 3.3V/2.5V Power Supply BWE Synchronous Byte Write Enable VDDQ Isolated Output Buffer Supply: 3.3V/2.5V ZZ Snooze Enable CE, CE2, CE2 Synchronous Chip Enable CLK Synchronous Clock DQa-DQd Synchronous Data Input/Output Integrated Silicon Solution, Inc. Rev. K 07/29/2010 9 IS61LF25672A IS61VF25672A IS61LF51236A IS61LF102418A IS61VF51236A IS61VF102418A PIN CONFIGURATION A A CE CE2 NC NC BWb BWa CE2 VDD VSS CLK GW BWE OE ADSC ADSP ADV A A 100-Pin TQFP 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 1 79 2 78 3 77 4 76 5 75 6 74 7 73 8 72 9 71 10 70 11 69 12 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 A NC NC VDDQ VSS NC DQPa DQa DQa VSS VDDQ DQa DQa VSS NC VDD ZZ DQa DQa VDDQ VSS DQa DQa NC NC VSS VDDQ NC NC NC MODE A A A A A1 A0 NC NC VSS VDD A A A A A A A A A NC NC NC VDDQ VSS NC NC DQb DQb VSS VDDQ DQb DQb NC VDD NC VSS DQb DQb VDDQ VSS DQb DQb DQPb NC VSS VDDQ NC NC NC 1024K x 18 PIN DESCRIPTIONS A0, A1 Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus. DQPa-DQPb Parity Data I/O; DQPa is parity for DQa1-8; DQPb is parity for DQb1-8 VSS Ground A Synchronous Address Inputs GW Synchronous Global Write Enable ADSC Synchronous Controller Address Status MODE Burst Sequence Mode Selection ADSP Synchronous Processor Address Status OE Output Enable ADV Synchronous Burst Address Advance Synchronous Byte Write Enable TMS, TDI, TCK, TDO JTAG Boundary Scan Pins BWa-BWb BWE Synchronous Byte Write Enable VDD 3.3V/2.5V Power Supply VDDQ Isolated Output Buffer Supply: 3.3V/2.5V ZZ Snooze Enable CE, CE2, CE2 Synchronous Chip Enable CLK Synchronous Clock DQa-DQb Synchronous Data Input/Output 10 Integrated Silicon Solution, Inc. Rev. K 07/29/2010 IS61LF25672A IS61VF25672A IS61LF51236A IS61LF102418A IS61VF51236A IS61VF102418A TRUTH TABLE(1-8) (3CE option) ADDRESS CE CE2 CE2 ZZ OE CLK DQ Deselect Cycle, Power-Down None H X X L X L X X X L-H High-Z Deselect Cycle, Power-Down None L X L L L X X X X L-H High-Z Deselect Cycle, Power-Down None L H X L L X X X X L-H High-Z Deselect Cycle, Power-Down None L X L L H L X X X L-H High-Z Deselect Cycle, Power-Down None L H X L H L X X X L-H High-Z Snooze Mode, Power-Down None X X X H X X X X X X High-Z Read Cycle, Begin Burst External L L H L L X X X L L-H Q Read Cycle, Begin Burst External L L H L L X X X H L-H High-Z Write Cycle, Begin Burst External L L H L H L X L X L-H D Read Cycle, Begin Burst External L L H L H L X H L L-H Q Read Cycle, Begin Burst External L L H L H L X H H L-H High-Z Read Cycle, Continue Burst Next X X X L H H L H L L-H Q Read Cycle, Continue Burst Next X X X L H H L H H L-H High-Z Read Cycle, Continue Burst Next H X X L X H L H L L-H Q Read Cycle, Continue Burst Next H X X L X H L H H L-H High-Z Write Cycle, Continue Burst Next X X X L H H L L X L-H D Write Cycle, Continue Burst Next H X X L X H L L X L-H D Read Cycle, Suspend Burst Current X X X L H H H H L L-H Q Read Cycle, Suspend Burst Current X X X L H H H H H L-H High-Z Read Cycle, Suspend Burst Current H X X L X H H H L L-H Q Read Cycle, Suspend Burst Current H X X L X H H H H L-H High-Z Write Cycle, Suspend Burst Current X X X L H H H L X L-H D Write Cycle, Suspend Burst Current H X X L X H H L X L-H D OPERATION ADSP ADSC ADV WRITE NOTE: 1. X means “Don’t Care.” H means logic HIGH. L means logic LOW. 2. For WRITE, L means one or more byte write enable signals (BWa-h) and BWE are LOW or GW is LOW. WRITE = H for all BWx, BWE, GW HIGH. 3. BWa enables WRITEs to DQa’s and DQPa. BWb enables WRITEs to DQb’s and DQPb. BWc enables WRITEs to DQc’s and DQPc. BWd enables WRITEs to DQd’s and DQPd. BWe enables WRITEs to DQe’s and DQPe. BWf enables WRITEs to DQf’s and DQPf. BWg enables WRITEs to DQg’s and DQPg. BWh enables WRITEs to DQh’s and DQPh. DQPa-DQPh are available on the x72 version. DQPa and DQPb are available on the x18 version. DQPa-DQPd are available on the x36 version. 4. All inputs except OE and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK. 5. Wait states are inserted by suspending burst. 6. For a WRITE operation following a READ operation, OE must be HIGH before the input data setup time and held HIGH during the input data hold time. 7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up. 8. ADSP LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more byte write enable signals and BWE LOW or GW LOW for the subsequent L-H edge of CLK. See WRITE timing diagram for clarification. Integrated Silicon Solution, Inc. Rev. K 07/29/2010 11 IS61LF25672A IS61VF25672A IS61LF51236A IS61LF102418A IS61VF51236A IS61VF102418A TRUTH TABLE(1-8) (1CE option) ADDRESS CE NEXT CYCLE Deselected ADSP ADSC ADV WRITE OE DQ None H X L X X X High-Z Read, Begin Burst External L L X X X L Q Read, Begin Burst External L L X X X H High-Z Write, Begin Burst External L H L X L X D Read, Begin Burst External L H L X H L Q Read, Begin Burst External L H L X H H High-Z Read, Continue Burst Next X H H L H L Q Read, Continue Burst Next X H H L H H High-Z Read, Continue Burst Next H X H L H L Q Read, Continue Burst Next H X H L H H High-Z Write, Continue Burst Next X H H L L X D Write, Continue Burst Next H X H L L X D Read, Suspend Burst Current X H H H H L Q Read, Suspend Burst Current X H H H H H High-Z Read, Suspend Burst Current H X H H H L Q Read, Suspend Burst Current H X H H H H High-Z Write, Suspend Burst Current X H H H L X D Write, Suspend Burst Current H X H H L X D NOTE: 1. X means “Don’t Care.” H means logic HIGH. L means logic LOW. 2. For WRITE, L means one or more byte write enable signals (BWa-h) and BWE are LOW or GW is LOW. WRITE = H for all BWx, BWE, GW HIGH. 3. BWa enables WRITEs to DQa’s and DQPa. BWb enables WRITEs to DQb’s and DQPb. BWc enables WRITEs to DQc’s and DQPc. BWd enables WRITEs to DQd’s and DQPd. BWe enables WRITEs to DQe’s and DQPe. BWf enables WRITEs to DQf’s and DQPf. BWg enables WRITEs to DQg’s and DQPg. BWh enables WRITEs to DQh’s and DQPh. DQPa-DQPh are available on the x72 version. DQPa and DQPb are available on the x18 version. DQPa-DQPd are available on the x36 version. 4. All inputs except OE and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK. 5. Wait states are inserted by suspending burst. 6. For a WRITE operation following a READ operation, OE must be HIGH before the input data setup time and held HIGH during the input data hold time. 7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up. 8. ADSP LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more byte write enable signals and BWE LOW or GW LOW for the subsequent L-H edge of CLK. See WRITE timing diagram for clarification. PARTIAL TRUTH TABLE Function Read Read Write Byte 1 Write All Bytes Write All Bytes 12 GW BWE BWa BWb BWc BWd BWe BWf BWg BWh H H H H L H L L L X X H L L X X H H L X X H H L X X H H L X X H H L X X H H L X X H H L X X H H L X Integrated Silicon Solution, Inc. Rev. K 07/29/2010 IS61LF25672A IS61VF25672A IS61LF51236A IS61LF102418A IS61VF51236A IS61VF102418A INTERLEAVED BURST ADDRESS TABLE (MODE = VDD or No Connect) External Address A1 A0 1st Burst Address A1 A0 2nd Burst Address A1 A0 3rd Burst Address A1 A0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 LINEAR BURST ADDRESS TABLE (MODE = VSS) 0,0 A1', A0' = 1,1 0,1 1,0 ABSOLUTE MAXIMUM RATINGS(1) Symbol TSTG PD IOUT VIN, VOUT VIN Parameter Storage Temperature Power Dissipation Output Current (per I/O) Voltage Relative to Vss for I/O Pins Voltage Relative to Vss for for Address and Control Inputs VDD Voltage on VDD Supply Relative to Vss Value Unit –55 to +150 °C 1.6 W 100 mA –0.5 to VDDQ + 0.5 V –0.5 to VDD + 0.5 V –0.5 to 4.6 V Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. This device contains circuity to protect the inputs against damage due to high static voltages or electric fields; however, precautions may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. 3. This device contains circuitry that will ensure the output devices are in High-Z at power up. Integrated Silicon Solution, Inc. Rev. K 07/29/2010 13 IS61LF25672A IS61VF25672A IS61LF51236A IS61LF102418A IS61VF51236A IS61VF102418A OPERATING RANGE (IS61LFxxxxx) Range Commercial Industrial Ambient Temperature 0°C to +70°C -40°C to +85°C VDD 3.3V ± 5% 3.3V ± 5% VDDQ 3.3V/2.5V ± 5% 3.3V/2.5V ± 5% VDD 2.5V ± 5% 2.5V ± 5% VDDQ 2.5V ± 5% 2.5V ± 5% OPERATING RANGE (IS61VFxxxxx) Range Commercial Industrial Ambient Temperature 0°C to +70°C -40°C to +85°C DC ELECTRICAL CHARACTERISTICS (Over Operating Range) 3.3V 2.5V Symbol Parameter Test Conditions Min. Max. Min. Max. Unit VOH Output HIGH Voltage IOH = –4.0 mA (3.3V) IOH = –1.0 mA (2.5V) 2.4 — 2.0 — V VOL Output LOW Voltage IOL = 8.0 mA (3.3V) IOL = 1.0 mA (2.5V) — 0.4 — 0.4 V VIH Input HIGH Voltage 2.0 VDD + 0.3 1.7 VDD + 0.3 V VIL Input LOW Voltage –0.3 0.8 –0.3 0.7 V ILI Input Leakage Current VSS ≤ VIN ≤ VDD(1) –5 5 –5 5 µA ILO Output Leakage Current VSS ≤ VOUT ≤ VDDQ, OE = VIH –5 5 –5 5 µA Note: 1. VIL (min.) = –2.0V AC (pulse width - 2.0 ns). Not 100% tested. VIH (max.) = VDD + 2.0V AC (pulse width - 2.0 ns). Not 100% tested. POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter Test Conditions Temp. range x18 6.5 MAX x36 x72 7.5 MAX x18 x36 Unit ICC AC Operating Supply Current Device Selected, Com. OE = VIH, ZZ ≤ VIL, Ind. All Inputs ≤ 0.2V or ≥ VDD – 0.2V, Cycle Time ≥ tKC min. 250 275 250 275 300 350 240 250 240 250 mA ISB Standby Current TTL Input Device Deselected, VDD = Max., All Inputs ≤ VIL or ≥ VIH, ZZ ≤ VIL, f = Max. Com. Ind. 140 150 140 150 140 150 140 150 140 150 mA ISBI Standby Current CMOS Input Device Deselected, VDD = Max., VIN ≤ VSS + 0.2V or ≥VDD – 0.2V f=0 Com. Ind. 110 125 110 125 110 125 110 125 110 125 mA ISB2 Sleep Mode ZZ>VIH Com. Ind. 60 75 60 75 60 75 60 75 60 75 mA Note: 1. MODE pin has an internal pullup and should be tied to VDD or VSS. It exhibits ±100 µA maximum leakage current when tied to ≤ VSS + 0.2V or ≥ VDD – 0.2V. 14 Integrated Silicon Solution, Inc. Rev. K 07/29/2010 IS61LF25672A IS61VF25672A IS61LF51236A IS61LF102418A IS61VF51236A IS61VF102418A CAPACITANCE(1,2) Symbol Parameter CIN Input Capacitance COUT Input/Output Capacitance Conditions Max. Unit VIN = 0V 6 pF VOUT = 0V 8 pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25°C, f = 1 MHz, VDD = 3.3V. 3.3V I/O AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0V to 3.0V 1.5 ns 1.5V See Figures 1 and 2 AC TEST LOADS 317 Ω 3.3V ZO = 50Ω OUTPUT 50Ω 1.5V Figure 1 Integrated Silicon Solution, Inc. Rev. K 07/29/2010 OUTPUT 5 pF Including jig and scope 351 Ω Figure 2 15 IS61LF25672A IS61VF25672A IS61LF51236A IS61LF102418A IS61VF51236A IS61VF102418A 2.5V I/O AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0V to 2.5V 1.5 ns 1.25V See Figures 3 and 4 2.5V I/O OUTPUT LOAD EQUIVALENT 1,667 Ω +2.5V ZO = 50Ω OUTPUT OUTPUT 50Ω 5 pF Including jig and scope 1,538 Ω 1.25V Figure 3 16 Figure 4 Integrated Silicon Solution, Inc. Rev. K 07/29/2010 IS61LF25672A IS61VF25672A IS61LF51236A IS61LF102418A IS61VF51236A IS61VF102418A READ/WRITE CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) 6.5 Min. Max. 7.5 Min. Max. Symbol Parameter fmax Clock Frequency — 133 — 117 MHz tKC Cycle Time 7.5 — 8.5 — ns tKH Clock High Time 2.2 — 2.5 — ns tKL Clock Low Time 2.2 — 2.5 — ns Clock Access Time — 6.5 — 7.5 ns tKQ (2) tKQX tKQLZ Unit Clock High to Output Invalid 2.5 — 2.5 — ns (2,3) Clock High to Output Low-Z 2.5 — 2.5 — ns (2,3) Clock High to Output High-Z — 3.8 — 4.0 ns tKQHZ tOEQ Output Enable to Output Valid — 3.2 — 3.4 ns (2,3) Output Enable to Output Low-Z 0 — 0 — ns (2,3) Output Disable to Output High-Z — 3.5 — 3.5 ns tAS Address Setup Time 1.5 — 1.5 — ns tWS Read/Write Setup Time 1.5 — 1.5 — ns tCES Chip Enable Setup Time 1.5 — 1.5 — ns tAVS Address Advance Setup Time 1.5 — 1.5 — ns tDS Data Setup Time 1.5 — 1.5 — ns tAH Address Hold Time 0.5 — 0.5 — ns tWH Write Hold Time 0.5 — 0.5 — ns tCEH Chip Enable Hold Time 0.5 — 0.5 — ns tAVH Address Advance Hold Time 0.5 — 0.5 — ns tDH Data Hold Time 0.5 — 0.5 — ns tPDS ZZ High to Power Down — 2 — 2 cyc tPUS ZZ Low to Power Down — 2 — 2 cyc tOELZ tOEHZ Notes: 1. Configuration signal MODE is static and must not change during normal operation. 2. Guaranteed but not 100% tested. This parameter is periodically sampled. 3. Tested with load in Figure 2. Integrated Silicon Solution, Inc. Rev. K 07/29/2010 17 IS61LF25672A IS61VF25672A IS61LF51236A IS61LF102418A IS61VF51236A IS61VF102418A READ/WRITE CYCLE TIMING tKC CLK tSS tSH tKH tKL ADSP is blocked by CE inactive ADSP tSS tSH ADSC ADV tAS Address tAH RD1 RD2 WR1 tWS tWH tWS tWH RD3 GW BWE tWS tWH WR1 BWd-BWa tCES tCEH tCES tCEH tCES tCEH CE Masks ADSP CE CE2 and CE2 only sampled with ADSP or ADSC CE2 Unselected with CE2 CE2 tOEHZ OE tKQX tOEQX DATAOUT High-Z tKQX tKQ DATAIN High-Z tKQLZ tKQ 1a tKQLZ 2b 2c 2d tKQHZ tKQHZ High-Z 1a tDS Single Read Flow-through 18 2a tDH Single Write Burst Read Unselected Integrated Silicon Solution, Inc. Rev. K 07/29/2010 IS61LF25672A IS61VF25672A IS61LF51236A IS61LF102418A IS61VF51236A IS61VF102418A WRITE CYCLE TIMING tKC CLK tSS tSH tKH tKL ADSP is blocked by CE1 inactive ADSP ADSC initiate Write ADSC ADV must be inactive for ADSP Write tAVS tAVH ADV tAS Address tAH WR1 WR3 WR2 tWS tWH tWS tWH tWS tWH GW BWE BWd-BWa WR1 tCES tCEH tCES tCEH tCES tCEH tWS tWH WR2 WR3 CE1 Masks ADSP CE Unselected with CE2 CE2 and CE3 only sampled with ADSP or ADSC CE2 CE2 OE DATAOUT High-Z tDS DATAIN High-Z tDH 1a Single Write Integrated Silicon Solution, Inc. Rev. K 07/29/2010 BW4-BW1 only are applied to first cycle of WR2 2a 2b 2c 2d Burst Write 3a Write Unselected 19 IS61LF25672A IS61VF25672A IS61LF51236A IS61LF102418A IS61VF51236A IS61VF102418A SNOOZE MODE ELECTRICAL CHARACTERISTICS Symbol Parameter Conditions Min. Max. Unit ISB2 Current during SNOOZE MODE ZZ ≥ Vih — 60 mA tPDS ZZ active to input ignored — 2 cycle tPUS ZZ inactive to input sampled 2 — cycle tZZI ZZ active to SNOOZE current — 2 cycle tRZZI ZZ inactive to exit SNOOZE current 0 — ns SNOOZE MODE TIMING CLK tPDS ZZ setup cycle tPUS ZZ recovery cycle ZZ tZZI Isupply ISB2 tRZZI All Inputs (except ZZ) Deselect or Read Only Deselect or Read Only Normal operation cycle Outputs (Q) High-Z Don't Care 20 Integrated Silicon Solution, Inc. Rev. K 07/29/2010 IS61LF25672A IS61VF25672A IS61LF51236A IS61LF102418A IS61VF51236A IS61VF102418A IEEE 1149.1 SERIAL BOUNDARY SCAN (JTAG) TEST ACCESS PORT (TAP) - TEST CLOCK The IS61LF/VF51236A and IS61LF/VF102418A have a serial boundary scan Test Access Port (TAP) in the PBGA package only. This port operates in accordance with IEEE Standard 1149.1-1900, but does not include all functions required for full 1149.1 compliance. These functions from the IEEE specification are excluded because they place added delay in the critical speed path of the SRAM. The TAP controller operates in a manner that does not conflict with the performance of other devices using 1149.1 fully compliant TAPs. The TAP operates using JEDEC standard 2.5V I/O logic levels. The test clock is only used with the TAP controller. All inputs are captured on the rising edge of TCK and outputs are driven from the falling edge of TCK. DISABLING THE JTAG FEATURE The SRAM can operate without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (Vss) to prevent clocking of the device. TDI and TMS are internally pulled up and may be disconnected. They may alternately be connected to VDD through a pull-up resistor. TDO should be left disconnected. On power-up, the device will start in a reset state which will not interfere with the device operation. TEST MODE SELECT (TMS) The TMS input is used to send commands to the TAP controller and is sampled on the rising edge of TCK. This pin may be left disconnected if the TAP is not used. The pin is internally pulled up, resulting in a logic HIGH level. TEST DATA-IN (TDI) The TDI pin is used to serially input information to the registers and can be connected to the input of any register. The register between TDI and TDO is chosen by the instruction loaded into the TAP instruction register. For information on instruction register loading, see the TAP Controller State Diagram. TDI is internally pulled up and can be disconnected if the TAP is unused in an application. TDI is connected to the Most Significant Bit (MSB) on any register. TAP CONTROLLER BLOCK DIAGRAM 0 Bypass Register 2 1 0 Instruction Register TDI Selection Circuitry Selection Circuitry 31 30 29 . . . 2 1 0 2 1 0 TDO Identification Register x . . . . . Boundary Scan Register* TCK TMS TAP CONTROLLER Integrated Silicon Solution, Inc. Rev. K 07/29/2010 21 IS61LF25672A IS61VF25672A IS61LF51236A IS61LF102418A IS61VF51236A IS61VF102418A TEST DATA OUT (TDO) The TDO output pin is used to serially clock data-out from the registers. The output is active depending on the current state of the TAP state machine (see TAP Controller State Diagram). The output changes on the falling edge of TCK and TDO is connected to the Least Significant Bit (LSB) of any register. PERFORMING A TAP RESET A Reset is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. RESET may be performed while the SRAM is operating and does not affect its operation. At power-up, the TAP is internally reset to ensure that TDO comes up in a high-Z state. TAP REGISTERS Registers are connected between the TDI and TDO pins and allow data to be scanned into and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction registers. Data is serially loaded into the TDI pin on the rising edge of TCK and output on the TDO pin on the falling edge of TCK. Instruction Register Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO pins. (See TAP Controller Block Diagram) At power-up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as previously described. When the TAP controller is in the CaptureIR state, the two least significant bits are loaded with a binary “01” pattern to allow for fault isolation of the board level serial test path. Bypass Register To save time when serially shifting data through registers, it is sometimes advantageous to skip certain states. The bypass register is a single-bit register that can be placed between TDI and TDO pins. This allows data to be shifted through the SRAM with minimal delay. The bypass register is set LOW (Vss) when the BYPASS instruction is executed. Boundary Scan Register The boundary scan register is connected to all input and output pins on the SRAM. Several no connect (NC) pins are also included in the scan register to reserve pins for higher density devices. The x36 configuration has a 75-bit-long register and the x18 configuration also has a 75-bit-long register. The boundary scan register is loaded with the contents of the RAM Input and Output ring when the TAP controller is in the Capture-DR state and then placed between the TDI and TDO pins when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD and SAMPLE-Z instructions can be used to capture the contents of the Input and Output ring. The Boundary Scan Order tables show the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI, and the LSB is connected to TDO. Scan Register Sizes Register Name Bit Size (x18) Bit Size (x36) Bit Size (x72) Instruction 3 3 3 Bypass 1 1 1 ID 32 32 32 Boundary Scan 75 75 TBD Identification (ID) Register The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded to the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has vendor code and other information described in the Identification Register Definitions table. IDENTIFICATION REGISTER DEFINITIONS Instruction Field Description 256Kx72 512K x 36 1M x 18 Revision Number (31:28) Reserved for version number. xxxx xxxx xxxx Device Depth (27:23) Defines depth of SRAM. 512K or 1M 00110 00111 01000 Device Width (22:18) Defines with of the SRAM. x36 or x18 00101 00100 00011 ISSI Device ID (17:12) Reserved for future use. xxxxx xxxxx xxxxx ISSI JEDEC ID (11:1) Allows unique identification of SRAM vendor. ID Register Presence (0) Indicate the presence of an ID register. 22 00011010101 1 00011010101 00011010101 1 1 Integrated Silicon Solution, Inc. Rev. K 07/29/2010 IS61LF25672A IS61VF25672A IS61LF51236A IS61LF102418A IS61VF51236A IS61VF102418A TAP INSTRUCTION SET SAMPLE/PRELOAD Eight instructions are possible with the three-bit instruction register and all combinations are listed in the Instruction Code table. Three instructions are listed as RESERVED and should not be used and the other five instructions are described below. The TAP controller used in this SRAM is not fully compliant with the 1149.1 convention because some mandatory instructions are not fully implemented. The TAP controller cannot be used to load address, data or control signals and cannot preload the Input or Output buffers. The SRAM does not implement the 1149.1 commands EXTEST or INTEST or the PRELOAD portion of SAMPLE/PRELOAD; instead it performs a capture of the Inputs and Output ring when these instructions are executed. Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted from the instruction register through the TDI and TDO pins. To execute an instruction once it is shifted in, the TAP controller must be moved into the Update-IR state. SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The PRELOAD portion of this instruction is not implemented, so the TAP controller is not fully 1149.1 compliant. When the SAMPLE/PRELOAD instruction is loaded to the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the inputs and output pins is captured in the boundary scan register. It is important to realize that the TAP controller clock operates at a frequency up to 10 MHz, while the SRAM clock runs more than an order of magnitude faster. Because of the clock frequency differences, it is possible that during the Capture-DR state, an input or output will undergo a transition. The TAP may attempt a signal capture while in transition (metastable state). The device will not be harmed, but there is no guarantee of the value that will be captured or repeatable results. To guarantee that the boundary scan register will capture the correct signal value, the SRAM signal must be stabilized long enough to meet the TAP controller’s capture setup plus hold times (tCS and tCH). To insure that the SRAM clock input is captured correctly, designs need a way to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is not an issue, it is possible to capture all other signals and simply ignore the value of the CLK and CLK captured in the boundary scan register. Once the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins. Note that since the PRELOAD part of the command is not implemented, putting the TAP into the Update to the Update-DR state while performing a SAMPLE/PRELOAD instruction will have the same effect as the Pause-DR command. EXTEST EXTEST is a mandatory 1149.1 instruction which is to be executed whenever the instruction register is loaded with all 0s. Because EXTEST is not implemented in the TAP controller, this device is not 1149.1 standard compliant. The TAP controller recognizes an all-0 instruction. When an EXTEST instruction is loaded into the instruction register, the SRAM responds as if a SAMPLE/PRELOAD instruction has been loaded. There is a difference between the instructions, unlike the SAMPLE/PRELOAD instruction, EXTEST places the SRAM outputs in a High-Z state. IDCODE The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO pins and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction is loaded into the instruction register upon power-up or whenever the TAP controller is given a test logic reset state. SAMPLE-Z The SAMPLE-Z instruction causes the boundary scan register to be connected between the TDI and TDO pins when the TAP controller is in a Shift-DR state. It also places all SRAM outputs into a High-Z state. Integrated Silicon Solution, Inc. Rev. K 07/29/2010 BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO pins. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. RESERVED These instructions are not implemented but are reserved for future use. Do not use these instructions. 23 IS61LF25672A IS61VF25672A IS61LF51236A IS61LF102418A IS61VF51236A IS61VF102418A INSTRUCTION CODES Code Instruction Description 000 EXTEST Captures the Input/Output ring contents. Places the boundary scan register between the TDI and TDO. Forces all SRAM outputs to High-Z state. This instruction is not 1149.1 compliant. 001 IDCODE Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operation. 010 SAMPLE-Z Captures the Input/Output contents. Places the boundary scan register between TDI and TDO. Forces all SRAM output drivers to a High-Z state. 011 RESERVED Do Not Use: This instruction is reserved for future use. 100 SAMPLE/PRELOAD 101 RESERVED Do Not Use: This instruction is reserved for future use. 110 RESERVED Do Not Use: This instruction is reserved for future use. 111 BYPASS Captures the Input/Output ring contents. Places the boundary scan register between TDI and TDO. Does not affect the SRAM operation. This instruction does not implement 1149.1 preload function and is therefore not 1149.1 compliant. Places the bypass register between TDI and TDO. This operation does not affect SRAM operation. TAP CONTROLLER STATE DIAGRAM Test Logic Reset 1 0 Run Test/Idle 1 Select DR 0 0 1 1 1 Capture DR 0 Shift DR 1 Exit1 DR 0 Select IR 0 1 Exit1 IR 0 Pause DR 0 1 0 1 24 Exit2 DR 1 Update DR 0 Capture IR 0 Shift IR 1 0 Pause IR 1 0 1 1 0 1 0 Exit2 IR 1 Update IR 0 Integrated Silicon Solution, Inc. Rev. K 07/29/2010 IS61LF25672A IS61VF25672A IS61LF51236A IS61LF102418A IS61VF51236A IS61VF102418A TAP Electrical Characteristics Over the Operating Range(1,2) Symbol Parameter Test Conditions Min. Max. Units VOH1 Output HIGH Voltage IOH = –2.0 mA 1.7 — V VOH2 Output HIGH Voltage IOH = –100 μA 2.1 — V VOL1 Output LOW Voltage IOL = 2.0 mA — 0.7 V VOL2 Output LOW Voltage IOL = 100 μA — 0.2 V VIH Input HIGH Voltage 1.7 VDD +0.3 V VIL Input LOW Voltage IOLT = 2mA –0.3 0.7 V IX Input Load Current Vss ≤ V I ≤ VDDQ –5 5 mA Notes: 1. All Voltage referenced to Ground. 2. Overshoot: VIH (AC) ≤ VDD +1.5V for t ≤ tTCYC/2, Undershoot: Vil (AC) ≤ 0.5V for t ≤ tTCYC/2, Power-up: VIH < 2.6V and VDD < 2.4V and VDDQ < 1.4V for t < 200 ms. TAP AC ELECTRICAL CHARACTERISTICS(1,2) (OVER OPERATING RANGE) Symbol Parameter Min. Max. Unit tTCYC TCK Clock cycle time 100 — ns fTF TCK Clock frequency — 10 MHz tTH TCK Clock HIGH 40 — ns tTL TCK Clock LOW 40 — ns tTMSS TMS setup to TCK Clock Rise 10 — ns tTDIS TDI setup to TCK Clock Rise 10 — ns tCS Capture setup to TCK Rise 10 — ns tTMSH TMS hold after TCK Clock Rise 10 — ns tTDIH TDI Hold after Clock Rise 10 — ns tCH Capture hold after Clock Rise 10 — ns tTDOV TCK LOW to TDO valid — 20 ns tTDOX TCK LOW to TDO invalid 0 — ns Notes: 1. Both tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register. 2. Test conditions are specified using the load in TAP AC test conditions. tR/tF = 1 ns. Integrated Silicon Solution, Inc. Rev. K 07/29/2010 25 IS61LF25672A IS61VF25672A IS61LF51236A IS61LF102418A IS61VF51236A IS61VF102418A TAP AC TEST CONDITIONS Input pulse levels TAP Output Load Equivalent 0 to 2.5V/0 to 3.0V Input rise and fall times 1ns Input timing reference levels 1.25V/1.5V Output reference levels 1.25V/1.5V Test load termination supply voltage 1.25V/1.5V 50Ω 1.25V/1.5V TDO 20 pF Z0 = 50Ω GND TAP TIMING 1 2 tTHTH 3 4 5 6 tTLTH TCK tTHTL tMVTH tTHMX TMS tDVTH tTHDX TDI tTLOV TDO tTLOX DON'T CARE UNDEFINED 26 Integrated Silicon Solution, Inc. Rev. K 07/29/2010 IS61LF25672A IS61VF25672A IS61LF51236A IS61LF102418A IS61VF51236A IS61VF102418A 165 PBGA BOUNDARY SCAN ORDER (512K x 36) Bit # Signal Bump Name ID Bit # Signal Bump Name ID Bit # Signal Name Bump ID Bit # Signal Name Bump ID 1 MODE 1R 21 DQb 11G 41 NC 1A 61 DQd 1J 2 A 6N 22 DQb 11F 42 CE2 6A 62 DQd 1K 3 A 11P 23 DQb 11E 43 BWa 5B 63 DQd 1L 4 A 8P 24 DQb 11D 44 BWb 5A 64 DQd 1M 5 A 8R 25 DQb 10G 45 BWc 4A 65 DQd 2J 6 A 9R 26 DQb 10F 46 BWd 4B 66 DQd 2K 7 A 9P 27 DQb 10E 47 CE2 3B 67 DQd 2L 8 A 10P 28 DQb 10D 48 CE 3A 68 DQd 2M 9 A 10R 29 DQb 11C 49 A 2A 69 DQd 1N 10 A 11R 30 NC 11A 50 A 2B 70 A 3P 11 ZZ 11H 31 A 10A 51 NC 1B 71 A 3R 12 DQa 11N 32 A 10B 52 DQc 1C 72 A 4R 13 DQa 11M 33 ADV 9A 53 DQc 1D 73 A 4P 14 DQa 11L 34 ADSP 9B 54 DQc 1E 74 A1 6P 15 DQa 11K 35 ADSC 8A 55 DQc 1F 75 A0 6R 16 DQa 11J 36 OE 8B 56 DQc 1G 17 DQa 10M 37 BWE 7A 57 DQc 2D 18 DQa 10L 38 GW 7B 58 DQc 2E 19 DQa 10K 39 CLK 6B 59 DQc 2F 20 DQa 10J 40 NC 11B 60 DQc 2G Integrated Silicon Solution, Inc. Rev. K 07/29/2010 27 IS61LF25672A IS61VF25672A IS61LF51236A IS61LF102418A IS61VF51236A IS61VF102418A 165 PBGA BOUNDARY SCAN ORDER (1M x 18) Bit # Signal Bump Name ID Bit # Signal Bump Name ID Bit # Signal Name Bump ID Bit # Signal Name Bump ID 1 MODE 1R 21 DQa 11G 41 NC 1A 61 DQb 1J 2 A 6N 22 DQa 11F 42 CE2 6A 62 DQb 1K 3 A 11P 23 DQa 11E 43 BWa 5B 63 DQb 1L 4 A 8P 24 DQa 11D 44 NC 5A 64 DQb 1M 5 A 8R 25 DQa 11C 45 BWb 4A 65 DQb 1N 6 A 9R 26 NC 10F 46 NC 4B 66 NC 2K 7 A 9P 27 NC 10E 47 CE2 3B 67 NC 2L 8 A 10P 28 NC 10D 48 CE 3A 68 NC 2M 9 A 10R 29 NC 10G 49 A 2A 69 NC 2J 10 A 11R 30 A 11A 50 A 2B 70 A 3P 11 ZZ 11H 31 A 10A 51 NC 1B 71 A 3R 12 NC 11N 32 A 10B 52 NC 1C 72 A 4R 13 NC 11M 33 ADV 9A 53 NC 1D 73 A 4P 14 NC 11L 34 ADSP 9B 54 NC 1E 74 A1 6P 15 NC 11K 35 ADSC 8A 55 NC 1F 75 A0 6R 16 NC 11J 36 OE 8B 56 NC 1G 17 DQa 10M 37 BWE 7A 57 DQb 2D 18 DQa 10L 38 GW 7B 58 DQb 2E 19 DQa 10K 39 CLK 6B 59 DQb 2F 20 DQa 10J 40 NC 11B 60 DQb 2G 28 Integrated Silicon Solution, Inc. Rev. K 07/29/2010 IS61LF25672A IS61VF25672A IS61LF51236A IS61LF102418A IS61VF51236A IS61VF102418A 209 BOUNDARY SCAN ORDER (256K X 72) Integrated Silicon Solution, Inc. Rev. K 07/29/2010 29 IS61LF25672A IS61VF25672A IS61LF51236A IS61LF102418A IS61VF51236A IS61VF102418A ORDERING INFORMATION (VDD = 3.3V/VDDQ = 2.5V/3.3V) Commercial Range: 0°C to +70°C Configuration Access Time Order Part Number Package 256Kx72 6.5 IS61LF25672A-6.5B1 209 PBGA 512Kx36 6.5 IS61LF51236A-6.5TQ IS61LF51236A-6.5B2 100 TQFP 119 PBGA IS61LF51236A-6.5B3 165 PBGA 512Kx36 7.5 IS61LF51236A-7.5TQ IS61LF51236A-7.5B2 IS61LF51236A-7.5B3 100 TQFP 119 PBGA 165 PBGA 1Mx18 6.5 IS61LF102418A-6.5TQ IS61LF102418A-6.5TQL IS61LF102418A-6.5B2 IS61LF102418A-6.5B3 100 TQFP 100 TQFP, Lead-free 119 PBGA 165 PBGA 1Mx18 7.5 IS61LF102418A-7.5TQ IS61LF102418A-7.5B2 IS61LF102418A-7.5B3 100 TQFP 119 PBGA 165 PBGA Order Part Number Package Industrial Range: -40°C to +85°C Configuration Access Time 256Kx72 6.5 IS61LF25672A-6.5B1I 209 PBGA 512Kx36 6.5 IS61LF51236A-6.5TQI IS61LF51236A-6.5TQLI IS61LF51236A-6.5B2I IS61LF51236A-6.5B2LI IS61LF51236A-6.5B3I 100 TQFP 100 TQFP, Lead-free 119 PBGA 119 PBGA, Lead-free 165 PBGA 512Kx36 7.5 IS61LF51236A-7.5TQI IS61LF51236A-7.5TQLI IS61LF51236A-7.5B2I IS61LF51236A-7.5B3I IS61LF51236A-7.5B3LI 100 TQFP 100 TQFP, Lead-free 119 PBGA 165 PBGA 165 PBGA, Lead-free 1Mx18 6.5 IS61LF102418A-6.5TQI IS61LF102418A-6.5B2I IS61LF102418A-6.5B3I 100 TQFP 119 PBGA 165 PBGA 1Mx18 7.5 IS61LF102418A-7.5TQI IS61LF102418A-7.5TQLI IS61LF102418A-7.5B2I IS61LF102418A-7.5B3I IS61LF102418A-7.5B3LI 100 TQFP 100 TQFP, Lead-free 119 PBGA 165 PBGA 165 PBGA, Lead-free 30 Integrated Silicon Solution, Inc. Rev. K 07/29/2010 IS61LF25672A IS61VF25672A IS61LF51236A IS61LF102418A IS61VF51236A IS61VF102418A ORDERING INFORMATION (VDD = 2.5V /VDDQ = 2.5V) Commercial Range: 0°C to +70°C Configuration Access Time Order Part Number Package 256Kx72 6.5 IS61VF25672A-6.5B1 209 PBGA 512Kx36 6.5 IS61VF51236A-6.5TQ IS61VF51236A-6.5B2 100 TQFP 119 PBGA IS61VF51236A-6.5B3 165 PBGA 512Kx36 7.5 IS61VF51236A-7.5TQ IS61VF51236A-7.5B2 IS61VF51236A-7.5B3 100 TQFP 119 PBGA 165 PBGA 1Mx18 6.5 IS61VF102418A-6.5TQ IS61VF102418A-6.5B2 100 TQFP 119 PBGA IS61VF102418A-6.5B3 165 PBGA IS61VF102418A-7.5TQ IS61VF102418A-7.5B2 IS61VF102418A-7.5B3 100 TQFP 119 PBGA 165 PBGA Order Part Number Package 1Mx18 7.5 Industrial Range: -40°C to +85°C Configuration Access Time 256Kx72 6.5 IS61VF25672A-6.5B1I 209 PBGA 512Kx36 6.5 IS61VF51236A-6.5TQI IS61VF51236A-6.5B2I IS61VF51236A-6.5B3I 100 TQFP 119 PBGA 165 PBGA 512Kx36 7.5 IS61VF51236A-7.5TQI IS61VF51236A-7.5TQLI IS61VF51236A-7.5B2I IS61VF51236A-7.5B3I 100 TQFP 100 TQFP, Lead-free 119 PBGA 165 PBGA 1Mx18 6.5 IS61VF102418A-6.5TQI IS61VF102418A-6.5B2I IS61VF102418A-6.5B3I 100 TQFP 119 PBGA 165 PBGA 1Mx18 7.5 IS61VF102418A-7.5TQI IS61VF102418A-7.5B2I IS61VF102418A-7.5B3I 100 TQFP 119 PBGA 165 PBGA Integrated Silicon Solution, Inc. Rev. K 07/29/2010 31 12/10/2007 Package Outline 1. Controlling dimension : mm IS61LF51236A IS61LF102418A IS61VF51236A IS61VF102418A NOTE : IS61LF25672A IS61VF25672A 32 Integrated Silicon Solution, Inc. Rev. K 07/29/2010 IS61LF25672A IS61VF25672A IS61LF51236A IS61LF102418A IS61VF51236A IS61VF102418A Integrated Silicon Solution, Inc. Rev. K 07/29/2010 33 IS61LF51236A IS61LF102418A IS61VF51236A IS61VF102418A 34 1. CONTROLLING DIMENSION : MM . 2. Reference document : JEDEC MS-028 NOTE : Package Outline 10/02/2008 IS61LF25672A IS61VF25672A Integrated Silicon Solution, Inc. Rev. K 07/29/2010 IS61LF51236A IS61LF102418A IS61VF51236A IS61VF102418A Integrated Silicon Solution, Inc. Rev. K 07/29/2010 Package Outline 1. CONTROLLING DIMENSION : MM . NOTE : 08/28/2008 IS61LF25672A IS61VF25672A 35