IS61LF6436A-8.5TQLI

® IS61LF6436A IS61LF6432A Long-term Support World Class Quality 64Kx32, 64Kx36 SYNCHRONOUS FLOW-THROUGH STATIC RAM MAY 2017 DESCRIPTION FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control using MODE input • Three chip enables for simple depth expansion and address pipelining • Common data inputs and data outputs • Power-down control by ZZ input • JEDEC 100-Pin TQFP package • Power Supply: +3.3V Vdd +3.3V or 2.5V Vddq • Control pins mode upon power-up: – MODE in interleave burst mode – ZZ in normal operation mode • Industrial Temperature Available: (-40oC to +85oC) • Lead-free available The ISSI IS61LF6432A and IS61LF6436A are high-speed, low-power synchronous static RAM designed to provide a burstable, high-performance, memory. IS61LF6432A is organized as 65,536 words by 32 bits. IS61LF6436A is organized as 65,536 words by 36 bits. They are fabricated with ISSI's advanced CMOS technology. The device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input. Write cycles are internally self-timed and are initiated by the rising edge of the clock input. Write cycles can be from one to four bytes wide as controlled by the write control inputs. Separate byte enables allow individual bytes to be written. BWa controls DQa, BWb controls DQb, BWc controls DQc, BWd controls DQd, conditioned by BWE being LOW. A LOW on GW input would cause all bytes to be written. Bursts can be initiated with either ADSP (Address Status Processor) or ADSC (Address Status Cache Controller) input pins. Subsequent burst addresses can be generated internally by the IS61LF6432A/36A and controlled by the ADV (burst address advance) input pin. The mode pin is used to select the burst sequence order. Linear burst is achieved when this pin is tied LOW. Interleave burst is achieved when this pin is tied HIGH or left floating. FAST ACCESS TIME Symbol tkq tkc Parameter Clock Access Time Cycle Time Frequency 8.5 Unit 8.5 ns 11 ns 90 MHz Copyright © 2017 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc. — www.issi.com 1 Rev. B1 05/08/2017 IS61LF6436A IS61LF6432A ® Long-term Support World Class Quality BLOCK DIAGRAM MODE A0' Q0 CLK CLK BINARY COUNTER CE ADV ADSC ADSP A1' Q1 64Kx32; 64Kx36 MEMORY ARRAY CLR A0, A1 A 17/18 D Q 14 16 ADDRESS REGISTER CE CLK 32, 36 GW BWE BW(a-d) x32/x36: a-d D 32, 36 Q DQ(a-d) BYTE WRITE REGISTERS CLK CE 4 Q CE2 D CE2 ENABLE REGISTER INPUT REGISTERS CLK 32, 36 DQa - DQd OE CE CLK OE 2 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev.  B1 05/08/2017 IS61LF6436A IS61LF6432A ® Long-term Support World Class Quality PIN CONFIGURATION A A CE CE2 BWd BWc BWb BWa CE2 VDD Vss CLK GW BWE OE ADSC ADSP ADV A A 100-Pin TQFP 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 10 71 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 NC DQb DQb VDDQ Vss DQb DQb DQb DQb Vss VDDQ DQb DQb Vss NC VDD ZZ DQa DQa VDDQ Vss DQa DQa DQa DQa Vss VDDQ DQa DQa NC MODE A A A A A1 A0 NC NC Vss VDD NC NC A A A A A A NC NC DQc DQc VDDQ Vss DQc DQc DQc DQc Vss VDDQ DQc DQc NC VDD NC Vss DQd DQd VDDQ Vss DQd DQd DQd DQd Vss VDDQ DQd DQd NC 64K x 32 PIN DESCRIPTIONS A0, A1 ADV Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus. Synchronous Address Inputs Synchronous Clock Synchronous Processor Address Status Synchronous Controller Address Status Synchronous Burst Address Advance BWa-BWd BWE Individual Byte Write Enable Synchronous Byte Write Enable A CLK ADSP ADSC Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. B1 05/08/2017 GW Synchronous Global Write Enable CE, CE2, CE2 Synchronous Chip Enable OE Output Enable DQa-DQd Synchronous Data Input/Output MODE Burst Sequence Mode Selection Vdd +3.3V Power Supply Vss Ground Vddq Isolated Output Buffer Supply: +3.3V or 2.5V ZZ Snooze Enable 3 IS61LF6436A IS61LF6432A ® Long-term Support World Class Quality PIN CONFIGURATION A A CE CE2 BWd BWc BWb BWa CE2 VDD Vss CLK GW BWE OE ADSC ADSP ADV A A 100-Pin TQFP DQPc DQPb DQb DQb VDDQ Vss DQb DQb DQb DQb Vss VDDQ DQb DQb Vss NC VDD ZZ DQa DQa VDDQ Vss DQa DQa DQa DQa Vss VDDQ DQa DQa DQPa MODE A A A A A1 A0 NC NC Vss VDD NC NC A A A A A A NC DQc DQc VDDQ Vss DQc DQc DQc DQc Vss VDDQ DQc DQc NC VDD NC Vss DQd DQd VDDQ Vss DQd DQd DQd DQd Vss VDDQ DQd DQd DQPd 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 10 71 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 64K x 36 PIN DESCRIPTIONS A0, A1 ADV Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus. Synchronous Address Inputs Synchronous Clock Synchronous Processor Address Status Synchronous Controller Address Status Synchronous Burst Address Advance BWa-BWd BWE Individual Byte Write Enable Synchronous Byte Write Enable A CLK ADSP ADSC 4 GW Synchronous Global Write Enable CE, CE2, CE2 Synchronous Chip Enable OE Output Enable DQa-DQd Synchronous Data Input/Output MODE Burst Sequence Mode Selection Vdd +3.3V Power Supply Vss Ground Vddq Isolated Output Buffer Supply: +3.3V or 2.5V ZZ Snooze Enable DQPa-DQPd Parity Data I/O Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev.  B1 05/08/2017 IS61LF6436A IS61LF6432A ® Long-term Support World Class Quality TRUTH TABLE Address Operation Used CE CE2 CE2 ADSP ADSC ADV WRITE OE DQ Deselected, Power-down None H X X X L X X X High-Z Deselected, Power-down None L X H L X X X X High-Z Deselected, Power-down None L L X L X X X X High-Z Deselected, Power-down None X X H H L X X X High-Z Deselected, Power-down None X L X H L X X X High-Z Read Cycle, Begin Burst External L H L L X X X X Q Read Cycle, Begin Burst External L H L H L X Read X Q Write Cycle, Begin Burst External L H L H L X Write X D Read Cycle, Continue Burst Next X X X H H L Read L Q Read Cycle, Continue Burst Next X X X H H L Read H High-Z Read Cycle, Continue Burst Next H X X X H L Read L Q Read Cycle, Continue Burst Next H X X X H L Read H High-Z Write Cycle, Continue Burst Next X X X H H L Write X D Write Cycle, Continue Burst Next H X X X H L Write X D Read Cycle, Suspend Burst Current X X X H H H Read L Q Read Cycle, Suspend Burst Current X X X H H H Read H High-Z Read Cycle, Suspend Burst Current H X X X H H Read L Q Read Cycle, Suspend Burst Current H X X X H H Read H High-Z Write Cycle, Suspend Burst Current X X X H H H Write X D Write Cycle, Suspend Burst Current H X X X H H Write X D PARTIAL TRUTH TABLE Function Read Read Write Byte 1 Write All Bytes Write All Bytes GW BWE BWa BWb BWc BWd H H X X X X H L H H H H H L L H H H H L L L L L L X X X X X Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. B1 05/08/2017 5 IS61LF6436A IS61LF6432A ® Long-term Support World Class Quality INTERLEAVED BURST ADDRESS TABLE (MODE = Vdd or No Connect) External Address A1 A0 00 01 10 11 1st Burst Address A1 A0 01 00 11 10 2nd Burst Address A1 A0 10 11 00 01 3rd Burst Address A1 A0 11 10 01 00 0,0 A1', A0' = 1,1 0,1 1,0 ABSOLUTE MAXIMUM RATINGS(1) Symbol Parameter Tstg Storage Temperature Pd Power Dissipation Iout Output Current (per I/O) Vin, Vout Voltage Relative to Vss for I/O Pins Value Unit –55 to +150 °C 1.6 W 100 mA –0.5 to Vddq + 0.3 V Vin Vdd –0.5 to Vdd + 0.5 V –0.5 to 4.6 V Voltage Relative to Vss for for Address and Control Inputs Voltage on Vdd Supply Relative to Vss Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, precautions may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. 3. This device contains circuitry that will ensure the output devices are in High-Z at power up. 6 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev.  B1 05/08/2017 IS61LF6436A IS61LF6432A ® Long-term Support World Class Quality OPERATING RANGE Range Ambient Temperature Vdd Industrial –40°C to +85°C 3.3V (I/O) Vddq 3.3V, +10%, –5% 2.5V (I/O) Vddq 3.3V, +10%, –5% 2.5V + 5% DC ELECTRICAL CHARACTERISTICS(1) (Over Operating Range) 2.5V (I/O) Symbol Parameter Test Conditions Min. Max. Voh Output HIGH Voltage Ioh = –4.0 mA (3.3V) 2.0 — Ioh = 1.0 mA (2.5V) Vol Output LOW Voltage Vih Input HIGH Voltage Vil V Ili Input Leakage Current Ilo Output Leakage Current Iol = 8.0 mA (3.3V) Iol = 1.0 mA (2.5V) Input LOW Voltage Vss ≤ Vin ≤ Vdd Vss ≤ Vout ≤ Vddq, OE = Vi 3.3V (I/O) Min. Max. Unit 2.4 — V — 0.4 — 0.4 V 1.7 Vdd + 0.3 –0.3 2.0 0.7 Vdd + 0.3 –0.3 V 0.8 –5 –5 5 5 –5 –5 5 5 µA µA POWER SUPPLY CHARACTERISTICS (Over Operating Range) 8.5 Symbol Parameter Test Conditions Max. Unit Icc AC Operating Device Selected, Ind. 150 mA Supply Current OE = Vih, ZZ ≤ Vil, All Inputs ≤ 0.2V or ≥ Vdd – 0.2V, Cycle Time ≥ tkc min. Isb1 Standby Current Device Deselected, Ind. 75 mA CMOS Input Vdd = Max., Vin ≤ Vss + 0.2V or ≥Vdd – 0.2V f = 0 Izz Sleep Mode ZZ>Vih Ind. 35 mA Notes: 1. The MODE pin has an internal pullup. This pin may be a No Connect, tied to Vss, or tied to Vdd. 2. The MODE pin should be tied to Vdd or Vss. It exhibits ±10 µA maximum leakage current when tied to ≤ Vss + 0.2V or ≥ Vdd – 0.2V. Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. B1 05/08/2017 7 IS61LF6436A IS61LF6432A ® Long-term Support World Class Quality CAPACITANCE(1,2) Symbol Cin Cout Parameter Input Capacitance Input/Output Capacitance Conditions Vin = 0V Vout = 0V Max. 6 8 Unit pF pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: Ta = 25°C, f = 1 MHz, Vdd = 3.3V. 3.3V I/O AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0V to 3.0V 1.5 ns 1.5V See Figures 1 and 2 3.3V I/O Output Load Equivalent 317 Ω ZO = 50Ω +3.3V Output 50Ω OUTPUT 351 Ω 1.5V 5 pF Including jig and scope Figure 1 Figure 2 8 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev.  B1 05/08/2017 IS61LF6436A IS61LF6432A ® Long-term Support World Class Quality 2.5V I/O AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0V to 2.5V 1ns 1.25V See Figures 3 and 4 2.5V I/O Output Load Equivalent 1,667 Ω ZO = 50Ω +2.5V Output OUTPUT 50Ω 1538 Ω 1.25V Figure 3 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. B1 05/08/2017 5 pF Including jig and scope Figure 4 9 IS61LF6436A IS61LF6432A ® Long-term Support World Class Quality READ/WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range) Symbol fmax(3) tkc(3) tkh tkl(3) tkq(3) tkqx(1) tkqlz(1,2) tkqhz(1,2) toeq(3) toeqx(1) toelz(1,2) toehz(1,2) tas tss(3) tws(3) tces(3) tavs(3) tah(3) tsh(3) twh(3) tceh(3) tavh(3) (3) Parameter Clock Frequency Cycle Time Clock High Time Clock Low Time Clock Access Time Clock High to Output Invalid Clock High to Output Low-Z Clock High to Output High-Z Output Enable to Output Valid Output Enable to Output Invalid Output Enable to Output Low-Z 8.5 Min. Max. Unit — 90 MHz 11 — ns 4.5 — ns 4.5 — ns — 8.5 ns 2 — ns 0 — ns 2 3.5 ns — 4.0 ns 2 — 0 — Output Disable to Output High-Z Address Setup Time Address Status Setup Time Write Setup Time Chip Enable Setup Time Address Advance Setup Time Address Hold Time Address Status Hold Time Write Hold Time Chip Enable Hold Time Address Advance Hold Time — 2 2 2 2 2 1 0.5 0.5 0.5 0.5 5.0 — — — — — — — — — — ns ns ns ns ns ns ns ns ns ns ns ns ns Notes: 1.  Guaranteed but not 100% tested. This parameter is periodically sampled. 2.  Tested with load in Figure 2. 3.  Tested with load in Figure 1. 10 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev.  B1 05/08/2017 IS61LF6436A IS61LF6432A ® Long-term Support World Class Quality READ/WRITE CYCLE TIMING tKC CLK tSS tSH tKH tKL ADSP is blocked by CE inactive ADSP tSS tSH ADSC ADV tAS Address tAH RD1 WR1 tWS tWH tWS tWH RD2 RD3 GW BWE tWS tWH WR1 BWd-BWa tCES tCEH tCES tCEH tCES tCEH CE Masks ADSP CE CE2 and CE2 only sampled with ADSP or ADSC CE2 Unselected with CE2 CE2 tOEHZ OE tKQ tOEQX DATAOUT High-Z 2c 2d tKQHZ tKQHZ 1a High-Z tDS Single Read Flow-through tDH Single Write Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. B1 05/08/2017 2b tKQX tKQX tKQX tKQ DATAIN 2a 1a tKQLZ tKQ Burst Read Unselected 11 IS61LF6436A IS61LF6432A ® Long-term Support World Class Quality WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range) Symbol tkc(1) tkh(1) tkl(1) tas(1) tss(1) tws(1) tds(1) tces(1) tavs(1) tah(1) tsh(1) tdh(1) twh tceh(1) tavh(1) (1) Parameter Cycle Time Clock High Time Clock Low Time Address Setup Time Address Status Setup Time Write Setup Time Data In Setup Time Chip Enable Setup Time Address Advance Setup Time Address Hold Time Address Status Hold Time 8.5 Min. Max. 11 — 4.5 — 4.5 — 2 — 2 — 2 — 3 — 2 — 2 — 1 — 0.5 — Data In Hold Time Write Hold Time Chip Enable Hold Time Address Advance Hold Time 1 0.5 0.5 0.5 — — — — Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Notes: 1.  Tested with load in Figure 1. 12 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev.  B1 05/08/2017 IS61LF6436A IS61LF6432A ® Long-term Support World Class Quality WRITE CYCLE TIMING tKC CLK tSS tSH tKH tKL ADSP is blocked by CE inactive ADSP ADSC initiate Write ADSC ADV must be inactive for ADSP Write tAVS tAVH ADV tAS A tAH WR1 WR3 WR2 tWS tWH tWS tWH tWS tWH GW BWE WR1 BWd-BWa tCES tCEH tCES tCEH tCES tCEH tWS tWH WR2 WR3 CE Masks ADSP CE Unselected with CE2 CE2 and CE2 only sampled with ADSP or ADSC CE2 CE2 OE DATAOUT High-Z tDS DATAIN High-Z Single Write tDH 1a BW4-BW1 only are applied to first cycle of WR2 2a 2b 2c 2d Burst Write Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. B1 05/08/2017 3a Write Unselected 13 IS61LF6436A IS61LF6432A ® Long-term Support World Class Quality SNOOZE MODE ELECTRICAL CHARACTERISTICS Symbol Parameter Isb2 Current during SNOOZE MODE tpds ZZ active to input ignored tpus ZZ inactive to input sampled tzzi ZZ active to SNOOZE current trzzi ZZ inactive to exit SNOOZE current Conditions ZZ ≥ Vih Min. — — 2 — 0 Max. 35 2 — 2 — Unit mA cycle cycle cycle ns SNOOZE MODE TIMING CLK tPDS ZZ setup cycle tPUS ZZ recovery cycle ZZ tZZI Isupply ISB2 tRZZI All Inputs (except ZZ) Deselect or Read Only Deselect or Read Only Normal operation cycle Outputs (Q) High-Z Don't Care 14 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev.  B1 05/08/2017 IS61LF6436A IS61LF6432A ® Long-term Support World Class Quality ORDERING INFORMATION 3.3V I/O or 2.5V I/O Industrial Range: -40°C to +85°C Speed (ns) 8.5 8.5 Order Part No. IS61LF6432A-8.5TQLI IS61LF6436A-8.5TQLI Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. B1 05/08/2017 Package TQFP, Lead-free TQFP, Lead-free 15 IS61LF6436A IS61LF6432A ® Long-term Support World Class Quality PACKAGE OUTLINE DRAWING 16 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev.  B1 05/08/2017