IS61LP6436A-133TQ

® IS61LP6436A IS61LP6432A 64K x 32, 64K x 36 SYNCHRONOUS PIPELINED STATIC RAM FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Pentium™ or linear burst sequence control using MODE input • Three chip enables for simple depth expansion and address pipelining • Common data inputs and data outputs • JEDEC 100-Pin TQFP package • Power-down snooze mode • Power Supply: +3.3V Vdd +3.3V or 2.5V Vddq (I/O) • Lead-free available Long-term Support World Class Quality MAY 2017 DESCRIPTION The ISSI IS61LP6432A/36A is a high-speed synchronous static RAM designed to provide a burstable, high-performance memory for high speed networking and communication applications. The IS61LP6432A is organized as 64K words by 32 bits and the IS61LP6436A is organized as 64K words by 36 bits. Fabricated with ISSI's advanced CMOS technology, the device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input. Write cycles are internally self-timed and are initiated by the rising edge of the clock input. Write cycles can be from one to four bytes wide as controlled by the write control inputs. Separate byte enables allow individual bytes to be written. BW1 controls DQa, BW2 controls DQb, BW3 controls DQc, BW4 controls DQd, conditioned by BWE being LOW. A LOW on GW input would cause all bytes to be written. Bursts can be initiated with either ADSP (Address Status Processor) or ADSC (Address Status Cache Controller) input pins. Subsequent burst addresses can be generated internally and controlled by the ADV (burst address advance) input pin. The mode pin is used to select the burst sequence order, Linear burst is achieved when this pin is tied LOW. Interleave burst is achieved when this pin is tied HIGH or left floating. FAST ACCESS TIME Symbol Parameter tkq Clock Access Time tkc Cycle Time Frequency -166 3.5 6 166 -133 4 7.5 133 Units ns ns MHz Copyright © 2017 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc. 1 Rev. C1 05/22/2017 IS61LP6436A IS61LP6432A ® Long-term Support World Class Quality BLOCK DIAGRAM MODE Q0 CLK CLK A0' A0 BINARY COUNTER ADSC ADSP A15-A0 Q1 CE ADV A1' A1 64K x 32 64K x 36 MEMORY ARRAY CLR 16 D Q 14 16 ADDRESS REGISTER CE CLK GW BWE BW4 D x32/x36 x32/x36 Q DQd BYTE WRITE REGISTERS CLK BW3 D DQc Q BYTE WRITE REGISTERS CLK D BW2 Q DQb BYTE WRITE REGISTERS CLK BW1 D DQa Q BYTE WRITE REGISTERS CLK CE CE2 CE2 4 D Q ENABLE REGISTER INPUT REGISTERS CLK OUTPUT REGISTERS CLK x32/x36 OE DQ[31:0] DQ[35:0] CE CLK D Q ENABLE DELAY REGISTER CLK OE 2 Integrated Silicon Solution, Inc. Rev. C1 05/22/2017 IS61LP6436A IS61LP6432A ® Long-term Support World Class Quality PIN CONFIGURATION A6 A7 CE CE2 BW4 BW3 BW2 BW1 CE2 VDD VSS CLK GW BWE OE ADSC ADSP ADV A8 A9 100-Pin TQFP 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 10 71 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 DQPb DQb8 DQb7 VDDQ VSS DQb6 DQb5 DQb4 DQb3 VSS VDDQ DQb2 DQb1 VSS NC VDD ZZ DQa8 DQa7 VDDQ VSS DQa6 DQa5 DQa4 DQa3 VSS VDDQ DQa2 DQa1 DQPa MODE A5 A4 A3 A2 A1 A0 NC NC VSS VDD NC NC A10 A11 A12 A13 A14 A15 NC DQPc DQc1 DQc2 VDDQ VSS DQc3 DQc4 DQc5 DQc6 VSS VDDQ DQc7 DQc8 NC VDD NC VSS DQd1 DQd2 VDDQ VSS DQd3 DQd4 DQd5 DQd6 VSS VDDQ DQd7 DQd8 DQPd 64K x 36 PIN DESCRIPTIONS A0, A1 A2-A15 CLK ADSP ADSC ADV BW1-BW4 BWE Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus. Synchronous Address Inputs Synchronous Clock Synchronous Processor Address Status Synchronous Controller Address Status Synchronous Burst Address Advance Individual Byte Write Enable Synchronous Byte Write Enable GW Synchronous Global Write Enable CE, CE2, CE2 Synchronous Chip Enable OE Output Enable DQa-DQd Synchronous Data Input/Output MODE Burst Sequence Mode Selection Vdd +3.3V Power Supply Vss Ground Vddq Isolated Output Buffer Supply: +3.3V/2.5V ZZ Snooze Enable DQPa-DQPd Parity Data I/O Integrated Silicon Solution, Inc. 3 Rev. C1 05/22/2017 IS61LP6436A IS61LP6432A ® Long-term Support World Class Quality PIN CONFIGURATION A6 A7 CE CE2 BW4 BW3 BW2 BW1 CE2 VDD VSS CLK GW BWE OE ADSC ADSP ADV A8 A9 100-Pin TQFP 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 10 71 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 NC DQb8 DQb7 VDDQ VSS DQb6 DQb5 DQb4 DQb3 VSS VDDQ DQb2 DQb1 VSS NC VDD ZZ DQa8 DQa7 VDDQ VSS DQa6 DQa5 DQa4 DQa3 VSS VDDQ DQa2 DQa1 NC MODE A5 A4 A3 A2 A1 A0 NC NC VSS VDD NC NC A10 A11 A12 A13 A14 A15 NC NC DQc1 DQc2 VDDQ VSS DQc3 DQc4 DQc5 DQc6 VSS VDDQ DQc7 DQc8 NC VDD NC VSS DQd1 DQd2 VDDQ VSS DQd3 DQd4 DQd5 DQd6 VSS VDDQ DQd7 DQd8 NC 64K x 32 PIN DESCRIPTIONS A0, A1 A2-A15 CLK ADSP ADSC ADV BW1-BW4 BWE 4 Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus. Synchronous Address Inputs Synchronous Clock Synchronous Processor Address Status Synchronous Controller Address Status Synchronous Burst Address Advance Individual Byte Write Enable Synchronous Byte Write Enable GW Synchronous Global Write Enable CE, CE2, CE2 Synchronous Chip Enable OE Output Enable DQa-DQd Synchronous Data Input/Output MODE Burst Sequence Mode Selection Vdd +3.3V Power Supply Vss Ground Vddq Isolated Output Buffer Supply: +3.3V/2.5V ZZ Snooze Enable Integrated Silicon Solution, Inc. Rev. C1 05/22/2017 IS61LP6436A IS61LP6432A ® Long-term Support World Class Quality TRUTH TABLE(1-8)  OPERATION ADDRESS CE CE2 CE2 ZZ ADSP ADSC ADV Deselect Cycle, Power-Down None H X X L X L X Deselect Cycle, Power-Down None L X L L L X X Deselect Cycle, Power-Down None L H X L L X X Deselect Cycle, Power-Down None L X L L H L X Deselect Cycle, Power-Down None L H X L H L X Snooze Mode, Power-Down None X X X H X X X Read Cycle, Begin Burst External L L H L L X X Read Cycle, Begin Burst External L L H L L X X Write Cycle, Begin Burst External L L H L H L X Read Cycle, Begin Burst External L L H L H L X Read Cycle, Begin Burst External L L H L H L X Read Cycle, Continue Burst Next X X X L H H L Read Cycle, Continue Burst Next X X X L H H L Read Cycle, Continue Burst Next H X X L X H L Read Cycle, Continue Burst Next H X X L X H L Write Cycle, Continue Burst Next X X X L H H L Write Cycle, Continue Burst Next H X X L X H L Read Cycle, Suspend Burst Current X X X L H H H Read Cycle, Suspend Burst Current X X X L H H H Read Cycle, Suspend Burst Current H X X L X H H Read Cycle, Suspend Burst Current H X X L X H H Write Cycle, Suspend Burst Current X X X L H H H Write Cycle, Suspend Burst Current H X X L X H H WRITE OE CLK DQ X X L-H High-Z X X L-H High-Z X X L-H High-Z X X L-H High-Z X X L-H High-Z X X X High-Z X L L-H Q X H L-H High-Z L X L-H D H L L-H Q H H L-H High-Z H L L-H Q H H L-H High-Z H L L-H Q H H L-H High-Z L X L-H D L X L-H D H L L-H Q H H L-H High-Z H L L-H Q H H L-H High-Z L X L-H D L X L-H D NOTE: 1. X means “Don’t Care.” H means logic HIGH. L means logic LOW. 2. For WRITE, L means one or more byte write enable signals (BWa-d) and BWE are LOW or GW is LOW. WRITE = H for all BWx, BWE, GW HIGH. 3. BWa enables WRITEs to DQa’s and DQPa. BWb enables WRITEs to DQb’s and DQPb. BWc enables WRITEs to DQc’s  and DQPc. BWd enables WRITEs to DQd’s and DQPd. DQPa and DQPb are available on the x18 version.  DQPa-DQPd are available on the x36 version. 4. All inputs except OE and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK. 5. Wait states are inserted by suspending burst. 6. For a WRITE operation following a READ operation, OE must be HIGH before the input data setup time and held HIGH during the input data hold time. 7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up. 8. ADSP LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more byte write enable signals and BWE LOW or GW LOW for the subsequent L-H edge of CLK. See WRITE timing diagram for clarification. PARTIAL TRUTH TABLE Function Read Read Write Byte 1 Write All Bytes Write All Bytes GW BWE BWa BWb BWc BWd H H X X X X H L H H H H H L L H H H H L L L L L L X X X X X Integrated Silicon Solution, Inc. 5 Rev. C1 05/22/2017 IS61LP6436A IS61LP6432A ® Long-term Support World Class Quality INTERLEAVED BURST ADDRESS TABLE (MODE = Vdd or No Connect) External Address 1st Burst Address 2nd Burst Address 3rd Burst Address A1 A0 A1 A0 A1 A0 A1 A0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 LINEAR BURST ADDRESS TABLE (MODE = Vss) 0,0 A1', A0' = 1,1 0,1 1,0 ABSOLUTE MAXIMUM RATINGS(1) Symbol Parameter Tstg Storage Temperature Pd Power Dissipation Iout Output Current (per I/O) Vin, Vout Voltage Relative to Vss for I/O Pins Vin Voltage Relative to Vss for for Address and Control Inputs Vdd Voltage on Vdd Supply Relative to Vss Value Unit –55 to +150 °C 1.6 W 100 mA –0.5 to Vddq + 0.3 V –0.5 to Vdd + 0.5 V –0.5 to 4.6 V Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, precautions may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. 3. This device contains circuitry that will ensure the output devices are in High-Z at power up. 6 Integrated Silicon Solution, Inc. Rev. C1 05/22/2017 IS61LP6436A IS61LP6432A ® Long-term Support World Class Quality OPERATING RANGE Range Ambient Temperature Vdd Vddq Commercial 0°C to +70°C 3.3V + 5% 3.3V + 5% 2.5V + 5% Industrial –40°C to +85°C 3.3V + 5% 3.3V + 5% 2.5V + 5% DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Symbol Parameter Voh Output HIGH Voltage Vol Output LOW Voltage Vih Input HIGH Voltage Vil Input LOW Voltage Ili Input Leakage Current Ilo Output Leakage Current 2.5V (I/O) 3.3V (I/O) Test Conditions Min. Max. Min. Max. Ioh = –4.0 mA  (3.3V) 2.0 — 2.4 — Ioh = 1.0 mA  (2.5V) Iol = 8.0 mA  (3.3V) — 0.4 — 0.4 Iol = 1.0 mA  (2.5V) 1.7 Vdd + 0.3 2.0 Vdd + 0.3 –0.3 0.7 –0.3 0.8 (1) Vss ≤ Vin ≤ Vdd –5 5 –5 5 Vss ≤ Vout ≤ Vddq, OE = Vi –5 5 –5 5 Unit V V V V µA µA POWER SUPPLY CHARACTERISTICS (Over Operating Range) Symbol Parameter Test Conditions Icc AC Operating Device Selected, Com. Supply Current All Inputs = Vil or Vih Ind. OE = Vih, Vdd = Max. Cycle Time ≥ tkc min. Isb1 Standby Current Device Deselected, Com. Vdd = Max., Ind. All Inputs = Vih or Vil CLK Cycle Time ≥ tkc min. Izz Power-down Mode ZZ = Vdd Com. Current Clock Running Ind. All Inputs ≤ Vss + 0.2V or ≥ Vdd – 0.2V -166 -133 Max. Max. 190 180 200 190 Unit mA mA 70 80 70 80 mA mA 35 40 35 mA 40 mA Notes: 1. The MODE pin has an internal pullup. This pin may be a No Connect, tied to Vss, or tied to Vdd. 2. The MODE pin should be tied to Vdd or Vss. It exhibits ±10 µA maximum leakage current when tied to ≤ Vss + 0.2V or ≥ Vdd – 0.2V. Integrated Silicon Solution, Inc. 7 Rev. C1 05/22/2017 IS61LP6436A IS61LP6432A ® Long-term Support World Class Quality CAPACITANCE(1,2) Symbol Cin Cout Parameter Input Capacitance Input/Output Capacitance Conditions Vin = 0V Vout = 0V Max. 6 8 Unit pF pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: Ta = 25°C, f = 1 MHz, Vdd = 3.3V. 3.3V I/O AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0V to 3.0V 1ns 1.5V See Figures 1 and 2 3.3V I/O OUTPUT LOAD EQUIVALENT 317 Ω ZO = 50Ω +3.3V OUTPUT OUTPUT 50Ω 351 Ω 5 pF Including jig and scope 1.5V Figure 1 8 Figure 2 Integrated Silicon Solution, Inc. Rev. C1 05/22/2017 IS61LP6436A IS61LP6432A ® Long-term Support World Class Quality 2.5V I/O AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0V to 2.5V 1 ns 1.25V See Figures 3 and 4 2.5V I/O OUTPUT LOAD EQUIVALENT 1,667 Ω +2.5V ZO = 50Ω OUTPUT OUTPUT 50Ω 1,538 Ω 5 pF Including jig and scope 1.25V Figure 3 Figure 4 Integrated Silicon Solution, Inc. 9 Rev. C1 05/22/2017 IS61LP6436A IS61LP6432A ® Long-term Support World Class Quality READ/WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)    Symbol Parameter fmax(3) Clock Frequency tkc(3) Cycle Time tkh Clock High Time (3) tkl Clock Low Time (3) tkq Clock Access Time tkqx(1) Clock High to Output Invalid tkqlz(1,2) Clock High to Output Low-Z (1,2) tkqhz Clock High to Output High-Z (3) toeq Output Enable to Output Valid toeqx(1) Output Disable to Output Invalid toelz(1,2) Output Enable to Output Low-Z toehz tas(3) tss(3) tws(3) tces(3) tavs(3) tah(3) tsh(3) twh(3) tceh(3) tavh(3) (1,2) -166 -133 Min. Max. Min. Max. — 166 — 133 6 — 7.5 — 2.4 — 2.8 — 2.4 — 2.8 — — 3.5 — 4 3 — 3 — 0 — 0 — 1.5 3.5 1.5 3.5 — 3.5 — 3.8 0 — 0 — 0 Output Disable to Output High-Z 2 Address Setup Time 2.1 Address Status Setup Time 1.5 Write Setup Time 1.5 Chip Enable Setup Time 1.5 Address Advance Setup Time 1.5 Address Hold Time 1.0 Address Status Hold Time 0.5 Write Hold Time 0.5 Chip Enable Hold Time 0.5 Address Advance Hold Time 0.5 — 4.5 — — — — — — — — — — 0 — 2 5 2.1 — 1.5 — 1.5 — 1.5 — 1.5 — 1.0 — 0.5 — 0.5 — 0.5 — 0.5 — Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Note: 1. Guaranteed but not 100% tested. This parameter is periodically sampled. 2. Tested with load in Figure 2. 3. Tested with load in Figure 1. 10 Integrated Silicon Solution, Inc. Rev. C1 05/22/2017 IS61LP6436A IS61LP6432A ® Long-term Support World Class Quality READ/WRITE CYCLE TIMING tKC CLK tSS tSH tKH tKL ADSP is blocked by CE inactive ADSP tSS tSH ADSC initiate read ADSC tAVH tAVS Suspend Burst ADV tAS A15-A0 tAH RD1 RD2 tWS tWH tWS tWH RD3 GW BWE BW4-BW1 tCES tCEH tCES tCEH tCES tCEH CE Masks ADSP CE Unselected with CE2 CE2 and CE2 only sampled with ADSP or ADSC CE2 CE2 tOEHZ tOEQ OE DATAOUT tKQX tOEQX tOELZ High-Z 1a 2a 2b 2c 2d tKQLZ 3a tKQHZ tKQ DATAIN High-Z Pipelined Read Single Read Burst Read Unselected Integrated Silicon Solution, Inc. 11 Rev. C1 05/22/2017 IS61LP6436A IS61LP6432A ® Long-term Support World Class Quality WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)     -166 -133 Symbol Parameter Min. Max. Min. Max. Unit (1) tkc Cycle Time 6 — 7.5 — ns (1) tkh Clock High Time 2.4 — 2.8 — ns tkl(1) Clock Low Time 2.4 — 2.8 — ns tas(1) Address Setup Time 2.1 — 2.1 — ns (1) tss Address Status Setup Time 1.5 — 1.5 — ns (1) tws Write Setup Time 1.5 — 1.5 — ns tds(1) Data In Setup Time 1.5 — 1.5 — ns tces(1) Chip Enable Setup Time 1.5 — 1.5 — ns (1) tavs Address Advance Setup Time 1.5 — 1.5 — ns (1) tah Address Hold Time 1.0 — 1.0 — ns tsh(1) Address Status Hold Time 0.5 — 0.5 — ns tdh(1) twh(1) tceh(1) tavh(1) Data In Hold Time Write Hold Time Chip Enable Hold Time Address Advance Hold Time 1.0 0.5 0.5 0.5 — — — — 1.0 0.5 0.5 0.5 — — — — ns ns ns ns Note: 1. Tested with load in Figure 1. 12 Integrated Silicon Solution, Inc. Rev. C1 05/22/2017 IS61LP6436A IS61LP6432A ® Long-term Support World Class Quality WRITE CYCLE TIMING tKC CLK tSS tSH tKH tKL ADSP is blocked by CE inactive ADSP ADSC initiate Write ADSC ADV must be inactive for ADSP Write tAVS tAVH ADV tAS A15-A0 tAH WR1 WR3 WR2 tWS tWH tWS tWH tWS tWH GW BWE WR1 BW4-BW1 tCES tCEH tCES tCEH tCES tCEH tWS tWH WR2 WR3 CE Masks ADSP CE Unselected with CE2 CE2 and CE2 only sampled with ADSP or ADSC CE2 CE2 OE DATAOUT High-Z tDS DATAIN High-Z Single Write tDH 1a BW4-BW1 only are applied to first cycle of WR2 2a 2b 2c 2d Burst Write 3a Write Unselected Integrated Silicon Solution, Inc. 13 Rev. C1 05/22/2017 IS61LP6436A IS61LP6432A ® Long-term Support World Class Quality SNOOZE AND RECOVERY CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)     Symbol Parameter tkc(3) Cycle Time (3) tkh Clock High Time tkl(3) Clock Low Time tkq(3) Clock Access Time (1) tkqx Clock High to Output Invalid (1,2) tkqlz Clock High to Output Low-Z tkqhz(1,2) Clock High to Output High-Z toeq(3) Output Enable to Output Valid (1) toeqx Output Disable to Output Invalid (1,2) toelz Output Enable to Output Low-Z toehz(1,2) Output Disable to Output High-Z tas tss(3) tces(3) tah(3) tsh(3) tceh(3) tzzs tzzrec (3) Address Setup Time Address Status Setup Time Chip Enable Setup Time Address Hold Time Address Status Hold Time Chip Enable Hold Time ZZ Standby ZZ Recovery -166 Min. Max. 6 — 2.4 — 2.4 — — 3.5 1.5 — 0 — 1.5 3.5 — 3.5 0 — 0 — -133 Min. Max. Unit 7.5 — ns 2.8 — ns 2.8 — ns — 4 ns 1.5 — ns 0 — ns 1.5 3.5 ns — 3.9 ns 0 — ns 0 — ns 2 2.1 1.5 1.5 1.0 0.5 0.5 2 2 2 2.1 1.5 1.5 1.0 0.5 0.5 2 2 4.5 — — — — — — — — 5.0 — — — — — — — — ns ns ns ns ns ns ns cyc cyc Notes: 1. Guaranteed but not 100% tested. This parameter is periodically sampled. 2. Tested with load in Figure 2. 3. Tested with load in Figure 1. 14 Integrated Silicon Solution, Inc. Rev. C1 05/22/2017 IS61LP6436A IS61LP6432A ® Long-term Support World Class Quality SNOOZE AND RECOVERY CYCLE TIMING tKC CLK tSS tSH tAS tAH tKH tKL ADSP ADSC ADV A15-A0 RD2 RD1 GW BWE BW4-BW1 tCES tCEH tCES tCEH tCES tCEH CE CE2 CE2 tOEHZ tOEQ OE tOEQX tOELZ DATAOUT High-Z 1a tKQLZ tKQ DATAIN tKQX tKQHZ High-Z tZZS tZZREC ZZ Single Read Snooze with Data Retention Read Integrated Silicon Solution, Inc. 15 Rev. C1 05/22/2017 IS61LP6436A IS61LP6432A ® Long-term Support World Class Quality ORDERING INFORMATION: IS61LP6432A Industrial Range: –40°C to +85°C Speed 133 MHz Order Part Number IS61LP6432A-133TQLI Package TQFP, Lead-free ORDERING INFORMATION: IS61LP6436A Industrial Range: –40°C to +85°C Speed 166 MHz 133 MHz 16 Order Part Number IS61LP6436A-166TQLI IS61LP6436A-133TQLI Package TQFP, Lead-free TQFP, Lead-free Integrated Silicon Solution, Inc. Rev. C1 05/22/2017 IS61LP6436A IS61LP6432A ® Long-term Support World Class Quality Integrated Silicon Solution, Inc. 17 Rev. C1 05/22/2017