IS61LPS25636B-200TQLI

IS61LPS51218B, IS61LPS25636B, IS61LPS25632B, IS64LPS25636B, IS61VPS/VVPS51218B, IS61VPS/VVPS25636B 256K x 36, 256K x 32, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, Single CYCLE DESELECT STATIC RAM MAY 2017 FEATURES DESCRIPTION • Internal self-timed write cycle The 9Mb product family features  high-speed, low-power synchronous static RAMs designed to provide burstable, high-performance memory for communication and networking applications. The IS61LPS/VPS25636B and IS64LPS25636B are organized as 262,144 words by 36 bits. The IS61LPS25632B is organized as 262,144 words by 32 bits. The IS61LPS/VPS51218B is organized as 524,288 words by 18 bits. Fabricated with ISSI's advanced CMOS technology, the device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input. • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs and data outputs • Auto Power-down during deselect • Single cycle deselect • Snooze MODE for reduced-power standby • JTAG Boundary Scan for BGA package • Power Supply LPS: Vdd 3.3V (+ 5%), Vddq 3.3V/2.5V (+ 5%) VPS: Vdd 2.5V (+ 5%), Vddq 2.5V (+ 5%) VVPS: Vdd 1.8V (+ 5%), Vddq 1.8V (+ 5%) • JEDEC 100-Pin QFP, 119-ball BGA, and 165ball BGA packages • Lead-free available FAST ACCESS TIME Symbol tkq tkc Parameter Clock Access Time Cycle Time Frequency Write cycles are internally self-timed and are initiated by the rising edge of the clock input. Write cycles can be one to four bytes wide as controlled by the write control inputs. Separate byte enables allow individual bytes to be written. The byte write operation is performed by using the byte write enable (BWE) input combined with one or more individual byte write signals (BWx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the byte write controls. Bursts can be initiated with either ADSP (Address Status Processor) or ADSC (Address Status Cache Controller) input pins. Subsequent burst addresses can be generated internally and controlled by the ADV (burst address advance) input pin. The mode pin is used to select the burst sequence order, Linear burst is achieved when this pin is tied LOW. Interleave burst is achieved when this pin is tied HIGH or left floating. 250 200 166 2.6 3.1 3.8 4 5 6 250 200 166 Units ns ns MHz Copyright © 2017 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 1 Rev. B3 05/26/2017 IS61LPS51218B, IS61LPS25636B, IS61LPS25632B, IS64LPS25636B, IS61VPS/VVPS51218B, IS61VPS/VVPS25636B BLOCK DIAGRAM MODE A0 CLK Q0 /CKE BINARY COUNTER /ADV /CE /ADSC /ADSP /CLR D A0-x x18: x=18 x36: x=17 Q1 A1 A0` A1` 256Kx36; 512Kx18 Memory Array Q ADDRESS REGISTER /CE CLK /GW /BWE /BW(a-x) x18:x=b, x32,x36:x=d D Q DQ(a-d) BYTE WRITE REGISTERS CLK INPUT REGISTER /CE CE2 D /CE2 ENABLE REGISTERS Q CLK OUTPUT REGISTER CLK ZZ Power Down DQ(a-x) x18:x=b, x32,x36:x=d CLK D Q ENABLE DELAY REGISTERS CLK /OE 2 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B3 05/26/2017 IS61LPS51218B, IS61LPS25636B, IS61LPS25632B, IS64LPS25636B, IS61VPS/VVPS51218B, IS61VPS/VVPS25636B 165-pin BGA 119-pin BGA 165-Ball, 13x15 mm BGA 119-Ball, 14x22 mm BGA Bottom view Bottom View Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 3 Rev. B3 05/26/2017 IS61LPS51218B, IS61LPS25636B, IS61LPS25632B, IS64LPS25636B, IS61VPS/VVPS51218B, IS61VPS/VVPS25636B 119 BGA PACKAGE PIN CONFIGURATION-256K x 36 (TOP VIEW) 1 2 3 4 5 6 7 A VDDQ A A ADSP A A VDDQ B NC CE2 A ADSC A A NC C NC A A VDD A A NC D DQc DQPc Vss NC Vss DQPb DQb E DQc DQc Vss CE Vss DQb DQb F VDDQ DQc Vss OE Vss DQb VDDQ G DQc DQc BWc ADV BWb DQb DQb H DQc DQc Vss GW Vss DQb DQb J VDDQ VDD NC VDD NC VDD VDDQ K DQd DQd Vss CLK Vss DQa DQa L DQd DQd BWd NC BWa DQa DQa M VDDQ DQd Vss BWE Vss DQa VDDQ N DQd DQd Vss A1* Vss DQa DQa P DQd DQPd Vss A0* Vss DQPa DQa R NC A MODE VDD NC A NC T NC NC A A A NC ZZ U VDDQ TMS TDI TCK TDO NC VDDQ Note: * A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired. PIN DESCRIPTIONS Symbol A Pin Name Address Inputs Symbol OE Pin Name Output Enable A0, A1 ADV ADSP Synchronous Burst Address Inputs Synchronous Burst Address Advance Address Status Processor ZZ Power Sleep Mode MODE Burst Sequence Selection TCK, TDO JTAG Pins ADSC GW Address Status Controller Global Write Enable CLK CE, CE2 Synchronous Clock Synchronous Chip Select BWx (x=a-d) Synchronous Byte Write Controls BWE 4 Byte Write Enable TMS, TDI NC No Connect DQa-DQd Data Inputs/Outputs DQPa-Pd Output Power Supply Vdd Power Supply Vddq I/O Power Supply Vss Ground Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B3 05/26/2017 IS61LPS51218B, IS61LPS25636B, IS61LPS25632B, IS64LPS25636B, IS61VPS/VVPS51218B, IS61VPS/VVPS25636B 119 BGA PACKAGE PIN CONFIGURATION 512Kx18 (TOP VIEW) 1 2 3 4 5 6 7 A VDDQ A A ADSP A A VDDQ B NC CE2 A ADSC A A NC NC C NC A A VDD A A D DQb NC Vss NC Vss DQPa E NC DQb Vss CE Vss NC DQa F VDDQ NC Vss OE Vss DQa VDDQ G NC DQb BWb ADV Vss NC DQa H DQb NC Vss GW Vss DQa NC J VDDQ VDD NC VDD NC VDD VDDQ K NC DQb Vss CLK Vss NC DQa L DQb NC Vss NC BWa DQa NC M VDDQ DQb Vss BWE Vss NC VDDQ N DQb NC Vss A 1* Vss DQa NC P NC DQPb Vss A 0* Vss NC DQa R NC A MODE VDD NC A NC T NC A A NC A A ZZ U VDDQ TMS TDI TCK TDO NC VDDQ NC Note: * A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired. PIN DESCRIPTIONS Symbol A Pin Name Address Inputs Symbol OE Pin Name Output Enable A0, A1 ADV ADSP Synchronous Burst Address Inputs Synchronous Burst Address Advance Address Status Processor ZZ Power Sleep Mode MODE Burst Sequence Selection TCK, TDO JTAG Pins ADSC GW Address Status Controller Global Write Enable CLK CE, CE2 Synchronous Clock Synchronous Chip Select BWx (x=a,b) Synchronous Byte Write Controls BWE Byte Write Enable TMS, TDI NC No Connect DQa-DQb Data Inputs/Outputs DQPa-Pb Output Power Supply Vdd Power Supply Vddq I/O Power Supply Vss Ground Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 5 Rev. B3 05/26/2017 IS61LPS51218B, IS61LPS25636B, IS61LPS25632B, IS64LPS25636B, IS61VPS/VVPS51218B, IS61VPS/VVPS25636B 165 BGA PACKAGE PIN CONFIGURATION 256K x 36 (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 A NC A CE BWc BWb CE2 BWE ADSC ADV A NC B NC A CE2 BWd BWa CLK GW OE ADSP A NC C DQPc NC Vddq Vss Vss Vss Vss Vss Vddq NC DQPb D DQc DQc Vddq Vdd Vss Vss Vss Vdd Vddq DQb DQb DQb E DQc DQc Vddq Vdd Vss Vss Vss Vdd Vddq DQb F DQc DQc Vddq Vdd Vss Vss Vss Vdd Vddq DQb DQb G DQc DQc Vddq Vdd Vss Vss Vss Vdd Vddq DQb DQb H NC Vss NC Vdd Vss Vss Vss Vdd NC NC ZZ J DQd DQd Vddq Vdd Vss Vss Vss Vdd Vddq DQa DQa K DQd DQd Vddq Vdd Vss Vss Vss Vdd Vddq DQa DQa L DQd DQd Vddq Vdd Vss Vss Vss Vdd Vddq DQa DQa M DQd DQd Vddq Vdd Vss Vss Vss Vdd Vddq DQa DQa N DQPd NC Vddq Vss NC NC NC Vss Vddq P NC NC A A TDI A1* TDO A A A A R MODE NC A A TMS A0* TCK A A A A NC DQPa Note: * A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired. PIN DESCRIPTIONS Symbol A Pin Name Address Inputs Symbol Pin Name BWE Byte Write Enable A0, A1 ADV ADSP Synchronous Burst Address Inputs Synchronous Burst Address Advance Address Status Processor OE Output Enable ZZ Power Sleep Mode MODE Burst Sequence Selection ADSC GW Address Status Controller Global Write Enable JTAG Pins CLK CE, CE2, CE2 Synchronous Clock Synchronous Chip Select TCK, TDO TMS, TDI NC DQx DQPx Vdd Vddq BWx (x=a,b,c,d) Synchronous Byte Write Controls Vss 6 No Connect Data Inputs/Outputs Data Inputs/Outputs Power Supply I/O Power Supply Ground Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B3 05/26/2017 IS61LPS51218B, IS61LPS25636B, IS61LPS25632B, IS64LPS25636B, IS61VPS/VVPS51218B, IS61VPS/VVPS25636B 165 BGA PACKAGE PIN CONFIGURATION 512K x 18 (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 A NC A CE BWb NC CE2 BWE ADSC ADV A A B NC A CE2 NC BWa CLK GW OE ADSP A NC C NC NC Vddq Vss Vss Vss Vss Vss Vddq NC DQPa D NC DQb Vddq Vdd Vss Vss Vss Vdd Vddq NC DQa E NC DQb Vddq Vdd Vss Vss Vss Vdd Vddq NC DQa F NC DQb Vddq Vdd Vss Vss Vss Vdd Vddq NC DQa G NC DQb Vddq Vdd Vss Vss Vss Vdd Vddq NC DQa H NC Vss NC Vdd Vss Vss Vss Vdd NC NC ZZ J DQb NC Vddq Vdd Vss Vss Vss Vdd Vddq DQa NC K DQb NC Vddq Vdd Vss Vss Vss Vdd Vddq DQa NC L DQb NC Vddq Vdd Vss Vss Vss Vdd Vddq DQa NC M DQb NC Vddq Vdd Vss Vss Vss Vdd Vddq DQa NC N DQPb NC Vddq Vss NC NC NC Vss Vddq NC NC P NC NC A A TDI A1* TDO A A A A R MODE NC A A TMS A0* TCK A A A A Note: * A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired. PIN DESCRIPTIONS Symbol A Pin Name Address Inputs Symbol BWE Byte Write Enable A0, A1 ADV ADSP Synchronous Burst Address Inputs Synchronous Burst Address Advance Address Status Processor OE Output Enable ZZ Power Sleep Mode MODE Burst Sequence Selection ADSC GW Address Status Controller Global Write Enable JTAG Pins CLK CE, CE2, CE2 Synchronous Clock Synchronous Chip Select BWx (x=a,b) Synchronous Byte Write Controls TCK, TDO TMS, TDI NC DQx DQPx Vdd Vddq Vss Pin Name No Connect Data Inputs/Outputs Data Inputs/Outputs 3.3V/2.5V Power Supply I/O Power Supply Ground Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 7 Rev. B3 05/26/2017 IS61LPS51218B, IS61LPS25636B, IS61LPS25632B, IS64LPS25636B, IS61VPS/VVPS51218B, IS61VPS/VVPS25636B PIN CONFIGURATION DQPc 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 10 71 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 DQPb DQb DQb VDDQ VSS DQb DQb DQb DQb VSS VDDQ DQb DQb VSS NC VDD ZZ DQa DQa VDDQ VSS DQa DQa DQa DQa VSS VDDQ DQa DQa DQPa DQPc DQc DQc VDDQ VSS DQc DQc DQc DQc VSS VDDQ DQc DQc NC VDD NC VSS DQd DQd VDDQ VSS DQd DQd DQd DQd VSS VDDQ DQd DQd DQPd 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 10 71 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 DQPb DQb DQb VDDQ VSS DQb DQb DQb DQb VSS VDDQ DQb DQb VSS NC VDD ZZ DQa DQa VDDQ VSS DQa DQa DQa DQa VSS VDDQ DQa DQa DQPa MODE A A A A A1 A0 NC NC VSS VDD NC NC A A A A A A A MODE A A A A A1 A0 NC NC VSS VDD NC A A A A A A A A DQc DQc VDDQ VSS DQc DQc DQc DQc VSS VDDQ DQc DQc NC VDD NC VSS DQd DQd VDDQ VSS DQd DQd DQd DQd VSS VDDQ DQd DQd DQPd A A CE CE2 BWd BWc BWb BWa A VDD VSS CLK GW BWE OE ADSC ADSP ADV A A A A CE CE2 BWd BWc BWb BWa CE2 VDD VSS CLK GW BWE OE ADSC ADSP ADV A A 100-Pin QFP (256K x 36) (2 Chip-Enable option) (3 Chip-Enable option) PIN DESCRIPTIONS A0, A1 A Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus. Synchronous Address Inputs ADSC Synchronous Controller Address Status ADSP Synchronous Processor Address Status ADV Synchronous Burst Address Advance BWa-BWd Synchronous Byte Write Enable BWE Synchronous Byte Write Enable CE, CE2, CE2 Synchronous Chip Enable CLK 8 DQa-DQd Synchronous Data Input/Output DQPa-DQPd Parity Data Input/Output GW MODE Synchronous Global Write Enable Burst Sequence Mode Selection OE Output Enable Vdd Power Supply Vddq Vss ZZ I/O Power Supply Ground Snooze Enable Synchronous Clock Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B3 05/26/2017 IS61LPS51218B, IS61LPS25636B, IS61LPS25632B, IS64LPS25636B, IS61VPS/VVPS51218B, IS61VPS/VVPS25636B PIN CONFIGURATION A A CE CE2 BWd BWc BWb BWa CE2 VDD VSS CLK GW BWE OE ADSC ADSP ADV A A 100-Pin QFP (256K x 32) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 10 71 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 NC DQb DQb VDDQ VSS DQb DQb DQb DQb VSS VDDQ DQb DQb VSS NC VDD ZZ DQa DQa VDDQ VSS DQa DQa DQa DQa VSS VDDQ DQa DQa NC MODE A A A A A1 A0 NC NC VSS VDD NC A A A A A A A A NC DQc DQc VDDQ VSS DQc DQc DQc DQc VSS VDDQ DQc DQc NC VDD NC VSS DQd DQd VDDQ VSS DQd DQd DQd DQd VSS VDDQ DQd DQd NC (3 Chip-Enable option) PIN DESCRIPTIONS A0, A1 A Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus. Synchronous Address Inputs ADSC Synchronous Controller Address Status ADSP Synchronous Processor Address Status ADV Synchronous Burst Address Advance BWa-BWd Synchronous Byte Write Enable BWE Synchronous Byte Write Enable DQa-DQd GW MODE Synchronous Data Input/Output Synchronous Global Write Enable Burst Sequence Mode Selection OE Output Enable Vdd Power Supply Vddq Vss ZZ I/O Power Supply Ground Snooze Enable CE, CE2, CE2 Synchronous Chip Enable CLK Synchronous Clock Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 9 Rev. B3 05/26/2017 IS61LPS51218B, IS61LPS25636B, IS61LPS25632B, IS64LPS25636B, IS61VPS/VVPS51218B, IS61VPS/VVPS25636B PIN CONFIGURATION A NC NC VDDQ VSS NC DQPa DQa DQa VSS VDDQ DQa DQa VSS NC VDD ZZ DQa DQa VDDQ VSS DQa DQa NC NC VSS VDDQ NC NC NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 10 71 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 NC NC NC VDDQ VSS NC NC DQb DQb VSS VDDQ DQb DQb NC VDD NC VSS DQb DQb VDDQ VSS DQb DQb DQPb NC VSS VDDQ NC NC NC A NC NC VDDQ VSS NC DQPa DQa DQa VSS VDDQ DQa DQa VSS NC VDD ZZ DQa DQa VDDQ VSS DQa DQa NC NC VSS VDDQ NC NC NC MODE A A A A A1 A0 NC NC VSS VDD NC NC A A A A A A A 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 10 71 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 MODE A A A A A1 A0 NC NC VSS VDD NC A A A A A A A A NC NC NC VDDQ VSS NC NC DQb DQb VSS VDDQ DQb DQb NC VDD NC VSS DQb DQb VDDQ VSS DQb DQb DQPb NC VSS VDDQ NC NC NC A A CE CE2 NC NC BWb BWa A VDD VSS CLK GW BWE OE ADSC ADSP ADV A A A A CE CE2 NC NC BWb BWa CE2 VDD VSS CLK GW BWE OE ADSC ADSP ADV A A 100-Pin QFP (512K x 18) (3 Chip-Enable Option) (2 Chip-Enable Option) PIN DESCRIPTIONS A0, A1 Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus. A Synchronous Address Inputs Synchronous Controller Address Status ADSC ADSP Synchronous Processor Address Status ADV Synchronous Burst Address Advance BWa-BWb Synchronous Byte Write Enable BWE Synchronous Byte Write Enable CE, CE2, CE2 Synchronous Chip Enable CLK Synchronous Clock DQa-DQb Synchronous Data Input/Output 10 DQPa-DQPb Parity Data I/O; DQPa is parity for DQa1-8; DQPb is parity for DQb1-8 GW MODE Synchronous Global Write Enable Burst Sequence Mode Selection OE Vdd Vddq Vss ZZ Output Enable Power Supply I/O Power Supply Ground Snooze Enable Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B3 05/26/2017 IS61LPS51218B, IS61LPS25636B, IS61LPS25632B, IS64LPS25636B, IS61VPS/VVPS51218B, IS61VPS/VVPS25636B TRUTH TABLE(1-8)  OPERATION ADDRESS CE CE2 CE2 ZZ ADSP ADSC ADV Deselect Cycle, Power-Down None H X X L X L X Deselect Cycle, Power-Down None L X L L L X X Deselect Cycle, Power-Down None L H X L L X X Deselect Cycle, Power-Down None L X L L H L X Deselect Cycle, Power-Down None L H X L H L X Snooze Mode, Power-Down None X X X H X X X Read Cycle, Begin Burst External L L H L L X X Read Cycle, Begin Burst External L L H L L X X Write Cycle, Begin Burst External L L H L H L X Read Cycle, Begin Burst External L L H L H L X Read Cycle, Begin Burst External L L H L H L X Read Cycle, Continue Burst Next X X X L H H L Read Cycle, Continue Burst Next X X X L H H L Read Cycle, Continue Burst Next H X X L X H L Read Cycle, Continue Burst Next H X X L X H L Write Cycle, Continue Burst Next X X X L H H L Write Cycle, Continue Burst Next H X X L X H L Read Cycle, Suspend Burst Current X X X L H H H Read Cycle, Suspend Burst Current X X X L H H H Read Cycle, Suspend Burst Current H X X L X H H Read Cycle, Suspend Burst Current H X X L X H H Write Cycle, Suspend Burst Current X X X L H H H Write Cycle, Suspend Burst Current H X X L X H H WRITE OE CLK DQ X X L-H High-Z X X L-H High-Z X X L-H High-Z X X L-H High-Z X X L-H High-Z X X X High-Z X L L-H Q X H L-H High-Z L X L-H D H L L-H Q H H L-H High-Z H L L-H Q H H L-H High-Z H L L-H Q H H L-H High-Z L X L-H D L X L-H D H L L-H Q H H L-H High-Z H L L-H Q H H L-H High-Z L X L-H D L X L-H D NOTE: 1. X means “Don’t Care.” H means logic HIGH. L means logic LOW. 2. For WRITE, L means one or more byte write enable signals (BWa-d) and BWE are LOW or GW is LOW. WRITE = H for all BWx, BWE, GW HIGH. 3. BWa enables WRITEs to DQa’s and DQPa. BWb enables WRITEs to DQb’s and DQPb. BWc enables WRITEs to DQc’s  and DQPc. BWd enables WRITEs to DQd’s and DQPd. DQPa and DQPb are available on the x18 version.  DQPa-DQPd are available on the x36 version. 4. All inputs except OE and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK. 5. Wait states are inserted by suspending burst. 6. For a WRITE operation following a READ operation, OE must be HIGH before the input data setup time and held HIGH during the input data hold time. 7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up. 8. ADSP LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more byte write enable signals and BWE LOW or GW LOW for the subsequent L-H edge of CLK. See WRITE timing diagram for clarification. PARTIAL TRUTH TABLE Function GW BWE BWa BWb BWc BWd Read H H X X X X Read H L H H H H Write Byte 1 H L L H H H Write All Bytes H L L L L L Write All Bytes L X X X X X Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 11 Rev. B3 05/26/2017 IS61LPS51218B, IS61LPS25636B, IS61LPS25632B, IS64LPS25636B, IS61VPS/VVPS51218B, IS61VPS/VVPS25636B Power Up Sequence Vddq → Vdd1 → I/O Pins2 Notes: 1. Vdd can be applied at the same time as Vddq 2. Applying I/O inputs is recommended after Vddq is ready. The inputs of the I/O pins can be applied at the same time as Vddq provided Vih (level of I/O pins) is lower than Vddq. Power-UP INITIALIZATION TIMING VDD power > 1ms VDD VDDQ Device Initialization Device ready for normal operation INTERLEAVED BURST ADDRESS TABLE (MODE = Vdd or No Connect) External Address A1 A0 00 01 10 11 1st Burst Address A1 A0 01 00 11 10 2nd Burst Address A1 A0 10 11 00 01 3rd Burst Address A1 A0 11 10 01 00 LINEAR BURST ADDRESS TABLE (MODE = Vss) 0,0 A1', A0' = 1,1     12 0,1 1,0 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B3 05/26/2017 IS61LPS51218B, IS61LPS25636B, IS61LPS25632B, IS64LPS25636B, IS61VPS/VVPS51218B, IS61VPS/VVPS25636B ABSOLUTE MAXIMUM RATINGS(1) Symbol Tstg Pd Iout Vin, Vout Vin Vdd Parameter LPS Value Storage Temperature –55 to +150 Power Dissipation 1.6 Output Current (per I/O) 100 Voltage Relative to Vss for I/O Pins –0.5 to Vddq + 0.5 Voltage Relative to Vss for –0.5 to Vdd + 0.5 for Address and Control Inputs Voltage on Vdd Supply Relative to Vss –0.5 to Vdd + 0.5 VPS/VVPS Value –55 to +150 1.6 100 –0.5 to Vddq + 0.3 –0.5 to Vdd + 0.3 Unit °C W mA V V –0.3 to Vdd + 0.3 V Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. This device contains circuity to protect the inputs against damage due to high static voltages or electric fields; however, precautions may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. 3. This device contains circuitry that will ensure the output devices are in High-Z at power up. OPERATING RANGE (IS61LPSXXXXX) Range Commercial Industrial Ambient Temperature 0°C to +70°C –40°C to +85°C Vdd Vddq 3.3V + 5% 3.3V / 2.5V + 5% 3.3V + 5% 3.3V / 2.5V + 5% OPERATING RANGE (IS61VPSXXXXX) Range Commercial Industrial Ambient Temperature 0°C to +70°C –40°C to +85°C Vdd Vddq 2.5V + 5% 2.5V + 5% 2.5V + 5% 2.5V + 5% OPERATING RANGE (IS61VVPSXXXXX) Range Commercial Industrial Ambient Temperature 0°C to +70°C –40°C to +85°C Vdd Vddq 1.8V + 5% 1.8V + 5% 1.8V + 5% 1.8V + 5% OPERATING RANGE (IS64LPSXXXXX) Range Automotive Ambient Temperature –40°C to +125°C Vdd Vddq 3.3V + 5% 3.3V / 2.5V + 5% Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 13 Rev. B3 05/26/2017 IS61LPS51218B, IS61LPS25636B, IS61LPS25632B, IS64LPS25636B, IS61VPS/VVPS51218B, IS61VPS/VVPS25636B DC ELECTRICAL CHARACTERISTICS (Over Operating Range) 1, 2, 3 3.3V Symbol Parameter Test Conditions Min. Max. Voh Output HIGH Voltage Ioh = –4.0 mA (3.3V) 2.4 — Ioh = –1.0 mA (2.5V, 1.8V) Vol Output LOW Voltage Iol = 8.0 mA (3.3V) — 0.4 Iol = 1.0 mA (2.5V, 1.8V) Vih Input HIGH Voltage 2.0 Vdd + 0.3 Vil Input LOW Voltage -0.3 0.8 (1) Ili Input Leakage Current Vss ≤ Vin ≤ Vdd -5 5 Ilo Output Leakage Current Vss ≤ Vout ≤ Vddq, -5 5 OE = Vih 2.5V 1.8V Min. Max. Min. Max. 2.0 — Vddq - 0.4 — — 0.4 — 0.4 Unit V V 1.7 Vdd + 0.3 0.6Vdd Vdd + 0.3 V -0.3 0.7 -0.3 0.3Vdd V -5 5 -5 5 µA -5 5 -5 5 µA Notes: 1. All voltages referenced to ground. 2. Overshoot: 3.3V and 2.5V: Vih (AC) ≤ Vdd + 1.5V (Pulse width less than tkc /2) 1.8V: Vih (AC) ≤ Vdd + 0.5V (Pulse width less than tkc /2) 3. Undershoot: 3.3V and 2.5V: Vil (AC) ≥ -1.5V (Pulse width less than tkc /2) 1.8V: Vil (AC) ≥ -0.5V (Pulse width less than tkc /2) POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter Icc AC Operating Supply Current Isb Standby Current TTL Input Isbi Standby Current CMOS Input Test Conditions Temp. range Device Selected, Com. OE = Vih, ZZ ≤ Vil, Ind. All Inputs ≤ 0.2V or ≥ Vdd – 0.2V, Auto Cycle Time ≥ tkc min. Device Deselected, Com. Vdd = Max., Ind. All Inputs ≤ Vil or ≥ Vih, Auto ZZ ≤ Vil, f = Max. Device Deselected, Com. Vdd = Max., Ind. Vin ≤ Vss + 0.2V or ≥Vdd – 0.2V Auto f = 0 -250 -200 MAX MAX x18 x36 x18 x36 Unit 185 185 155 155 mA 190 190 160 160 170 170 75 80 - 75 80 - 75 75 mA 80 80 85 85 55 60 - 55 60 - 55 60 65 55 60 65 mA Note: 1. MODE pin has an internal pullup and should be tied to Vdd or Vss. It exhibits ±100µA maximum leakage current when tied to ≤ Vss + 0.2V or ≥ Vdd – 0.2V. 14 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B3 05/26/2017 IS61LPS51218B, IS61LPS25636B, IS61LPS25632B, IS64LPS25636B, IS61VPS/VVPS51218B, IS61VPS/VVPS25636B CAPACITANCE(1,2) Symbol Cin Cout Parameter Input Capacitance Input/Output Capacitance Conditions Vin = 0V Vout = 0V Max. 6 8 Unit pF pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: Ta = 25°C, f = 1 MHz, Vdd = 3.3V. 3.3V I/O AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Refe rence Level Output Load Unit 0V to 3.0V 1.5 ns 1.5V See Figures 1 and 2 AC TEST LOADS 317 Ω 3.3V ZO = 50Ω Output 50Ω 1.5V Figure 1 OUTPUT 5 pF Including jig and scope 351 Ω Figure 2 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 15 Rev. B3 05/26/2017 IS61LPS51218B, IS61LPS25636B, IS61LPS25632B, IS64LPS25636B, IS61VPS/VVPS51218B, IS61VPS/VVPS25636B 2.5V I/O AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0V to 2.5V 1.5 ns 1.25V See Figures 3 and 4 2.5 I/O OUTPUT LOAD EQUIVALENT 1,667 Ω 2.5V ZO = 50Ω Output 50Ω OUTPUT 1,538 Ω 5 pF Including jig and scope 1.25V Figure 3 Figure 4 1.8V I/O AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0V to 1.8V 1.5 ns 0.9V See Figures 5 and 6 1.8 I/O OUTPUT LOAD EQUIVALENT 1K Ω 1.8V ZO = 50Ω Output 50Ω 0.9V Figure 5 16 OUTPUT 5 pF Including jig and scope 1K Ω Figure 6 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B3 05/26/2017 IS61LPS51218B, IS61LPS25636B, IS61LPS25632B, IS64LPS25636B, IS61VPS/VVPS51218B, IS61VPS/VVPS25636B READ/WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range) -250 -200 -166 Symbol Parameter Min. Max. Min. Max. Min. Max. fmax Clock Frequency — 250 — 200 — 166 tkc Cycle Time 4.0 — 5 — 6 — tkh Clock High Time 1.7 — 2 — 2.4 — tkl Clock Low Time 1.7 — 2 — 2.3 — tkq Clock Access Time — 2.6 — 3.1 — 3.8 (2) tkqx Clock High to Output Invalid 0.8 — 1.5 — 1.5 — (2,3) tkqlz Clock High to Output Low-Z 0.8 — 1 — 1.5 — tkqhz(2,3) Clock High to Output High-Z — 2.6 — 3.0 3.5 — toeq Output Enable to Output Valid — 2.6 — 3.1 3.5 — (2,3) toelz Output Enable to Output Low-Z 0 — 0 — 0 — (2,3) toehz Output Disable to Output High-Z — 2.6 — 3.0 3.5 — tas tss tws tces tavs tds tah tsh twh tceh tavh tdh tpower(4) Address Setup Time Address Status Setup Time Read/Write Setup Time Chip Enable Setup Time Address Advance Setup Time Data Setup Time Address Hold Time Address Status Hold Time Write Hold Time Chip Enable Hold Time Address Advance Hold Time Data Hold Time Vdd (typical) to First Access 1.2 1.2 1.2 1.2 1.2 1.2 0.3 0.3 0.3 0.3 0.3 0.3 1 — — — — — — — — — — — — — 1.4 1.4 1.4 1.4 1.4 1.4 0.4 0.4 0.4 0.4 0.4 0.4 1 — — — — — — — — — — — — — 1.7 1.7 1.7 1.7 1.7 1.7 0.7 0.7 0.7 0.7 0.7 0.7 1 — — — — — — — — — — — — — Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms Note: 1. Configuration signal MODE is static and must not change during normal operation. 2. Guaranteed but not 100% tested. This parameter is periodically sampled. 3. Tested with load in Figure 2. 4. tpower is the time that the power needs to be supplied above Vdd (min) initially before READ or WRITE operation can be initiated. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 17 Rev. B3 05/26/2017 IS61LPS51218B, IS61LPS25636B, IS61LPS25632B, IS64LPS25636B, IS61VPS/VVPS51218B, IS61VPS/VVPS25636B READ CYCLE TIMING tKC CLK tSS tSH tKH tKL ADSP is blocked by CE inactive ADSP tSS tSH ADSC initiate read ADSC tAVH tAVS Suspend Burst tSS tSH ADV tAS Address tAH RD1 RD3 RD2 tWS tWH tWS tWH GW BWE BWx tCES tCEH tCES tCEH tCES tCEH CE Masks ADSP CE Unselected with CE2 CE2 and CE2 only sampled with ADSP or ADSC CE2 CE2 tOEHZ tOEQ OE tKQX tOELZ DATAOUT High-Z 1a 2a 2b 2c tKQLZ 2d tKQHZ tKQ DATAIN High-Z Pipelined Read Single Read 18 Burst Read Unselected Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B3 05/26/2017 IS61LPS51218B, IS61LPS25636B, IS61LPS25632B, IS64LPS25636B, IS61VPS/VVPS51218B, IS61VPS/VVPS25636B WRITE CYCLE TIMING tKC CLK tSS tSH tKH tKL ADSP is blocked by CE inactive ADSP ADSC initiate Write ADSC ADV must be inactive for ADSP Write tAVS tAVH tSS tSH ADV tAS Address tAH WR1 WR3 WR2 tWS tWH tWS tWH tWS tWH GW BWE WR1 BWx tCES tCEH tCES tCEH tCES tCEH tWS tWH WR2 WR3 CE Masks ADSP CE Unselected with CE2 CE2 and CE2 only sampled with ADSP or ADSC CE2 CE2 OE DATAOUT High-Z tDS DATAIN High-Z Single Write tDH 1a BW4-BW1 only are applied to first cycle of WR2 2a 2b 2c 2d Burst Write 3a Write Unselected Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 19 Rev. B3 05/26/2017 IS61LPS51218B, IS61LPS25636B, IS61LPS25632B, IS64LPS25636B, IS61VPS/VVPS51218B, IS61VPS/VVPS25636B SNOOZE MODE ELECTRICAL CHARACTERISTICS Symbol Parameter Conditions Isb2 Current during SNOOZE MODE ZZ ≥ Vih tpds ZZ active to input ignored tpus ZZ inactive to input sampled tzzi ZZ active to SNOOZE current trzzi ZZ inactive to exit SNOOZE current Temperature Range Com. Ind. Auto. Min. Max. — — — — 2 — 0 20 25 35 2 — 2 — Unit mA cycle cycle cycle ns SNOOZE MODE TIMING CLK tPDS ZZ setup cycle tPUS ZZ recovery cycle ZZ tZZI Isupply ISB2 tRZZI All Inputs (except ZZ) Deselect or Read Only Deselect or Read Only Normal operation cycle Outputs (Q) High-Z Don't Care 20 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B3 05/26/2017 IS61LPS51218B, IS61LPS25636B, IS61LPS25632B, IS64LPS25636B, IS61VPS/VVPS51218B, IS61VPS/VVPS25636B IEEE 1149.1 Serial Boundary Scan (JTAG) Test Access Port (TAP) - Test Clock The serial boundary scan Test Access Port (TAP) is only available in the BGA package. (The QFP package not available.) This port operates in accordance with IEEE Standard 1149.1-1900, but does not include all functions required for full 1149.1 compliance. These functions from the IEEE specification are excluded because they place added delay in the critical speed path of the SRAM. The TAP controller operates in a manner that does not conflict with the performance of other devices using 1149.1 fully compliant TAPs. The test clock is only used with the TAP controller. All inputs are captured on the rising edge of TCK and outputs are driven from the falling edge of TCK. Disabling the JTAG Feature The TDI pin is used to serially input information to the registers and can be connected to the input of any register. The register between TDI and TDO is chosen by the instruction loaded into the TAP instruction register. For information on instruction register loading, see the TAP Controller State Diagram. TDI is internally pulled up and can be disconnected if the TAP is unused in an application. TDI is connected to the Most Significant Bit (MSB) on any register. The SRAM can operate without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (Vss) to prevent clocking of the device. TDI and TMS are internally pulled up and may be disconnected. They may alternately be connected to Vdd through a pull-up resistor. TDO should be left disconnected. On power-up, the device will start in a reset state which will not interfere with the device operation. Test Mode Select (TMS) The TMS input is used to send commands to the TAP controller and is sampled on the rising edge of TCK. This pin may be left disconnected if the TAP is not used. The pin is internally pulled up, resulting in a logic HIGH level. Test Data-In (TDI) tap controller block diagram 0 Bypass Register 2 1 0 Instruction Register TDI Selection Circuitry 31 30 29 . . . Selection Circuitry 2 1 0 2 1 0 TDO Identification Register x . . . . . Boundary Scan Register* TCK TMS TAP CONTROLLER Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 21 Rev. B3 05/26/2017 IS61LPS51218B, IS61LPS25636B, IS61LPS25632B, IS64LPS25636B, IS61VPS/VVPS51218B, IS61VPS/VVPS25636B Test Data Out (TDO) Boundary Scan Register The TDO output pin is used to serially clock data-out from the registers. The output is active depending on the current state of the TAP state machine (see TAP Controller State Diagram). The output changes on the falling edge of TCK and TDO is connected to the Least Significant Bit (LSB) of any register. The boundary scan register is connected to all input and output pins on the SRAM. Several no connect (NC) pins are also included in the scan register to reserve pins for higher density devices. The x36 configuration has a 75-bit-long register and the x18 configuration also has a 75-bit-long register. The boundary scan register is loaded with the contents of the RAM Input and Output ring when the TAP controller is in the Capture-DR state and then placed between the TDI and TDO pins when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD and SAMPLE-Z instructions can be used to capture the contents of the Input and Output ring. The Boundary Scan Order tables show the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI, and the LSB is connected to TDO. Performing a TAP Reset A Reset is performed by forcing TMS HIGH (Vdd) for five rising edges of TCK. RESET may be performed while the SRAM is operating and does not affect its operation. At power-up, the TAP is internally reset to ensure that TDO comes up in a high-Z state. TAP Registers Registers are connected between the TDI and TDO pins and allow data to be scanned into and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction registers. Data is serially loaded into the TDI pin on the rising edge of TCK and output on the TDO pin on the falling edge of TCK. Instruction Register Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO pins. (See TAP Controller Block Diagram)  At power-up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as previously described. When the TAP controller is in the CaptureIR state, the two least significant bits are loaded with a binary “01” pattern to allow for fault isolation of the board level serial test path. Bypass Register To save time when serially shifting data through registers, it is sometimes advantageous to skip certain states. The bypass register is a single-bit register that can be placed between TDI and TDO pins. This allows data to be shifted through the SRAM with minimal delay. The bypass register is set LOW (Vss) when the BYPASS instruction is executed. Scan Register Sizes Register Name Instruction Bypass ID Boundary Scan Bit Size Bit Size (x18) (x36) 3 3 1 1 32 32 90 90 Identification (ID) Register The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded to the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has vendor code and other information described in the Identification Register Definitions table. Identification Register Definitions Instruction Field Revision Number  (31:28) Device Depth  (27:23) Device Width  (22:18) ISSI Device ID  (17:12) ISSI JEDEC ID  (11:1) ID Register Presence  (0) 22 Description 256K x 36 Reserved for version number. xxxx Defines depth of SRAM. 256K or 512K 00111 Defines width of the SRAM. x36 or x18 00100 Reserved for future use. xxxxx Allows unique identification of SRAM vendor. 00001010101 Indicate the presence of an ID register. 1 512K x 18 xxxx 01000 00011 xxxxx 00001010101 1 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B3 05/26/2017 IS61LPS51218B, IS61LPS25636B, IS61LPS25632B, IS64LPS25636B, IS61VPS/VVPS51218B, IS61VPS/VVPS25636B TAP Instruction Set SAMPLE/PRELOAD Eight instructions are possible with the three-bit instruction register and all combinations are listed in the Instruction Code table. Three instructions are listed as RESERVED and should not be used and the other five instructions are described below. The TAP controller used in this SRAM is not fully compliant with the 1149.1 convention because some mandatory instructions are not fully implemented. The TAP controller cannot be used to load address, data or control signals and cannot preload the Input or Output buffers. The SRAM does not implement the 1149.1 commands EXTEST or INTEST or the PRELOAD portion of SAMPLE/ PRELOAD; instead it performs a capture of the Inputs and Output ring when these instructions are executed. Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted from the instruction register through the TDI and TDO pins. To execute an instruction once it is shifted in, the TAP controller must be moved into the Update-IR state. SAMPLE/PRELOAD is a 1149.1 mandatory instruction.The PRELOAD portion of this instruction is not implemented, so the TAP controller is not fully 1149.1 compliant. When the SAMPLE/PRELOAD instruction is loaded to the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the inputs and output pins is captured in the boundary scan register. It is important to realize that the TAP controller clock operates at a frequency up to 10 MHz, while the SRAM clock runs more than an order of magnitude faster. Because of the clock frequency differences, it is possible that during the Capture-DR state, an input or output will under-go a transition. The TAP may attempt a signal capture while in transition (metastable state).The device will not be harmed, but there is no guarantee of the value that will be captured or repeatable results. To guarantee that the boundary scan register will capture the correct signal value, the SRAM signal must be stabilized long enough to meet the TAP controller’s capture set-up plus hold times (tcs and tch). To insure that the SRAM clock input is captured correctly, designs need a way to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is not an issue, it is possible to capture all other signals and simply ignore the value of the CLK captured in the boundary scan register. Once the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins. Note that since the PRELOAD part of the command is not implemented, putting the TAP into the Update to the UpdateDR state while performing a SAMPLE/PRELOAD instruction will have the same effect as the Pause-DR command. EXTEST EXTEST is a mandatory 1149.1 instruction which is to be executed whenever the instruction register is loaded with all 0s. Because EXTEST is not implemented in the TAP controller, this device is not 1149.1 standard compliant. The TAP controller recognizes an all-0 instruction. When an EXTEST instruction is loaded into the instruction register, the SRAM responds as if a SAMPLE/PRELOAD instruction has been loaded. There is a difference between the instructions, unlike the SAMPLE/PRELOAD instruction, EXTEST places the SRAM outputs in a High-Z state. IDCODE The IDCODE instruction causes a vendor-specific, 32bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO pins and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction is loaded into the instruction register upon power-up or whenever the TAP controller is given a test logic reset state. Bypass When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO pins. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. SAMPLE-Z Reserved The SAMPLE-Z instruction causes the boundary scan register to be connected between the TDI and TDO pins when the TAP controller is in a Shift-DR state. It also places all SRAM outputs into a High-Z state. These instructions are not implemented but are reserved for future use. Do not use these instructions. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 23 Rev. B3 05/26/2017 IS61LPS51218B, IS61LPS25636B, IS61LPS25632B, IS64LPS25636B, IS61VPS/VVPS51218B, IS61VPS/VVPS25636B Instruction Codes Code Instruction Description 000 EXTEST Captures the Input/Output ring contents. Places the boundary scan register between the TDI and TDO. Forces all SRAM outputs to High-Z state. This instruction is not 1149.1 compliant. 001 IDCODE Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operation. 010 SAMPLE-Z Captures the Input/Output contents. Places the boundary scan register between TDI and TDO. Forces all SRAM output drivers to a High-Z state. 011 RESERVED Do Not Use: This instruction is reserved for future use. 100 SAMPLE/PRELOAD Captures the Input/Output ring contents. Places the boundary scan register between TDI and TDO. Does not affect the SRAM operation. This instruction does not implement 1149.1 preload function and is therefore not 1149.1 compliant. 101 RESERVED Do Not Use: This instruction is reserved for future use. 110 RESERVED Do Not Use: This instruction is reserved for future use. 111 BYPASS Places the bypass register between TDI and TDO. This operation does not affect SRAM operation. TAP CONTROLLER STATE DIAGRAM Test Logic Reset 1 0 Run Test/Idle 1 Select DR 0 0 1 1 1 Capture DR 0 Shift DR 1 Exit1 DR 0 Select IR 0 1 Exit1 IR 0 Pause DR 0 1 0 1 24 Exit2 DR 1 Update DR 0 Capture IR 0 Shift IR 1 0 Pause IR 1 0 1 1 0 1 0 Exit2 IR 1 Update IR 0 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B3 05/26/2017 IS61LPS51218B, IS61LPS25636B, IS61LPS25632B, IS64LPS25636B, IS61VPS/VVPS51218B, IS61VPS/VVPS25636B TAP Electrical Characteristics (2.5V and 3.3V Operating Range) Symbol Voh1 Voh2 Vol1 Vol2 Vih Vil Ix Parameter Output HIGH Voltage Output HIGH Voltage Output LOW Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current Test Conditions Ioh = –2.0 mA Ioh = –100 µA Iol = 2.0 mA Iol = 100 µA Vss ≤ V I ≤ Vddq TAP Electrical Characteristics (1.8V Operating Range) Symbol Voh1 Vol1 Vih Vil Ix Min. 1.7 2.1 — — 1.7 –0.3 –10 Max. — — 0.7 0.2 Vdd +0.3 0.7 10 Units V V V V V V µA Parameter Output HIGH Voltage Test Conditions Ioh = –2.0 mA Min. Vdd -0.4 Max. — Units V Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current Iol = 2.0 mA Vss ≤ V I ≤ Vddq -0.3 1.3 –0.3 –10 0.5 Vdd +0.3 0.7 10 V V V µA TAP AC ELECTRICAL CHARACTERISTICS (Over Operating Range) Parameter Symbol Min Max Units TCK cycle time tTHTH 100 – ns TCK high pulse width tTHTL 40 – ns TCK low pulse width tTLTH 40 – ns TMS Setup tMVTH 10 – ns TMS Hold tTHMX 10 – ns TDI Setup tDVTH 10 – ns TDI Hold tTHDX 10 – ns TCK Low to Valid Data tTLOV – 20 ns Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 25 Rev. B3 05/26/2017 IS61LPS51218B, IS61LPS25636B, IS61LPS25632B, IS64LPS25636B, IS61VPS/VVPS51218B, IS61VPS/VVPS25636B TAP AC TEST CONDITIONS (1.8V/2.5V/3.3V) Input pulse levels Input rise and fall times Input timing reference levels Output reference levels Test load termination supply voltage Vtrig 0 to 1.8V/0 to 2.5V/0 to 3.0V 1.5ns 0.9V/1.25V/1.5V 0.9V/1.25V/1.5V 0.9V/1.25V/1.5V 0.9V/1.25V/1.5V TAP Output Load Equivalent 50Ω Vtrig TDO 20 pF Z0 = 50Ω GND Tap timing 1 2 tTHTH 3 4 5 6 tTLTH TCK tTHTL tMVTH tTHMX TMS tDVTH tTHDX TDI tTLOV TDO tTLOX DON'T CARE UNDEFINED 26 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B3 05/26/2017 IS61LPS51218B, IS61LPS25636B, IS61LPS25632B, IS64LPS25636B, IS61VPS/VVPS51218B, IS61VPS/VVPS25636B 119 BGA Boundary Scan Order TBD Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 27 Rev. B3 05/26/2017 IS61LPS51218B, IS61LPS25636B, IS61LPS25632B, IS64LPS25636B, IS61VPS/VVPS51218B, IS61VPS/VVPS25636B 165 BGA Boundary Scan Order 165 BGA 165 BGA x36 Bit # 28 Bump ID x36 x18 Signal Bump ID Signal Bit # Bump ID x18 Signal Bump ID Signal 1 N6 NC N6 NC 41 B8 /OE B8 /OE 2 N7 NC N7 NC 42 A7 /BWE A7 /BWE 3 N10 NC N10 NC 43 B7 /GW B7 /GW 4 P11 A8 P11 A8 44 B6 CLK B6 CLK 5 P8 A17 P8 A17 45 A6 /CE2 A6 /CE2 6 R8 A16 R8 A16 46 B5 /Bwa B5 /Bwa 7 R9 A15 R9 A15 47 A5 /Bwb A5 NC 8 P9 A14 P9 A14 48 A4 /Bwc A4 /Bwb 9 P10 A13 P10 A13 49 B4 /Bwd B4 NC B3 CE2 B3 CE2 10 R10 A12 R10 A12 50 11 R11 A11 R11 A11 51 A3 /CE1 A3 /CE1 12 H11 ZZ H11 ZZ 52 A2 A7 A2 A7 13 N11 DQa0 N11 NC 53 B2 A6 B2 A6 14 M11 DQa1 M11 NC 54 C2 NC C2 NC 15 L11 DQa2 L11 NC 55 B1 NC B1 NC 16 M10 DQa3 M10 NC 56 A1 NC A1 NC 17 L10 DQa4 L10 NC 57 C1 DQc0 C1 NC 18 K11 DQa5 K11 DQa8 58 D1 DQc1 D1 NC E1 DQc2 E1 NC NC 19 J11 DQa6 J11 DQa7 59 20 K10 DQa7 K10 DQa6 60 D2 DQc3 D2 21 J10 DQa8 J10 DQa5 61 E2 DQc4 E2 NC 22 H9 NC H9 NC 62 F1 DQc5 F1 DQb8 23 H10 NC H10 NC 63 G1 DQc6 G1 DQb7 24 G11 DQb8 G11 DQa4 64 F2 DQc7 F2 DQb6 25 F11 DQb7 F11 DQa3 65 G2 DQc8 G2 DQb5 26 G10 DQb6 G10 DQa2 66 H1 NC H1 NC 27 E11 DQb5 E11 DQa1 67 H2 NC H2 NC 28 D11 DQb4 D11 DQa0 68 H3 NC H3 NC 29 F10 DQb3 C11 NC 69 J1 DQd8 J1 DQb4 K1 DQd7 K1 DQb3 J2 DQd6 J2 DQb2 30 E10 DQb2 E10 NC 70 31 D10 DQb1 D10 NC 71 32 C11 DQb0 F10 NC 72 L1 DQd5 L1 DQb1 33 A11 NC A11 A18 73 M1 DQd4 M1 DQb0 34 B11 NC B11 NC 74 K2 DQd3 N1 NC 35 A10 A10 A10 A10 75 L2 DQd2 L2 NC 36 B10 A9 B10 A9 76 M2 DQd1 M2 NC 37 A9 /ADV A9 /ADV 77 N1 DQd0 K2 NC 38 B9 /ADSP B9 /ADSP 78 N2 NC N2 NC P1 NC P1 NC R1 MODE R1 MODE 39 C10 NC C10 NC 79 40 A8 /ADSC A8 /ADSC 80 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B3 05/26/2017 IS61LPS51218B, IS61LPS25636B, IS61LPS25632B, IS64LPS25636B, IS61VPS/VVPS51218B, IS61VPS/VVPS25636B 165 BGA x36 x18 Bit # Bump ID Signal Bump ID Signal 81 R2 NC R2 NC 82 P3 A5 P3 A5 83 R3 A4 R3 A4 84 P2 NC P2 NC 85 P4 A2 P4 A2 86 R4 A3 R4 A3 87 N5 NC N5 NC 88 P6 A1 P6 A1 89 R6 A0 R6 A0 90 * Int * Int Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 29 Rev. B3 05/26/2017 IS61LPS51218B, IS61LPS25636B, IS61LPS25632B, IS64LPS25636B, IS61VPS/VVPS51218B, IS61VPS/VVPS25636B ORDERING INFORMATION (3.3V core/2.5V-3.3V I/O) Industrial Range: -40°C to +85°C Configuration 256Kx32 Frequency Order Part Number Package(1) 200 IS61LPS25632B-200TQLI 100 QFP, 3CE, Lead-free 250 200 166 IS61LPS25636B-250TQLI IS61LPS25636B-250B2I IS61LPS25636B-250B3I IS61LPS25636B-200TQLI IS61LPS25636B-200B2I IS61LPS25636B-200B3I IS61LPS25636B-200B3LI IS61LPS25636B-166TQLI 100 QFP, 3CE, Lead-free 119 BGA 165 BGA 100 QFP, 3CE, Lead-free 119 BGA 165 BGA 165 BGA, Lead-free 100 QFP, 3CE, Lead-free 250 200 IS61LPS51218B-250TQLI IS61LPS51218B-250TQ2LI IS61LPS51218B-250B2I IS61LPS51218B-250B3I IS61LPS51218B-200TQLI IS61LPS51218B-200TQ2LI IS61LPS51218B-200B2I IS61LPS51218B-200B3I 100 QFT, 3CE, Lead-free 100 QFT, 2CE, Lead-free 119 BGA 165 BGA 100 QFP, 3CE, Lead-free 100 QFP, 2CE, Lead-free 119 BGA 165 BGA 256Kx36 512Kx18 Note: 1. For 100 QFP, 2CE option contact SRAM Marketing at sram@issi.com Automotive Range: -40°C to +125°C Configuration 256Kx36 30 Frequency 200 166 Order Part Number IS64LPS25636B-200TQLA3 IS64LPS25636B-166TQLA3 Package 100 QFP, 3CE, Lead-free 100 QFP, 3CE, Lead-free Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B3 05/26/2017 IS61LPS51218B, IS61LPS25636B, IS61LPS25632B, IS64LPS25636B, IS61VPS/VVPS51218B, IS61VPS/VVPS25636B ORDERING INFORMATION (2.5V core/2.5V I/O) Industrial Range: -40°C to +85°C Configuration 256Kx36 Frequency Order Part Number Package(1) 250 200 IS61VPS25636B-250TQLI IS61VPS25636B-250B2I IS61VPS25636B-250B3I IS61VPS25636B-200TQLI IS61VPS25636B-200B2I IS61VPS25636B-200B3I 100 QFP, 3CE, Lead-free 119 BGA 165 BGA 100 QFP, 3CE, Lead-free 119 BGA 165 BGA 250 200 IS61VPS51218B-250TQLI IS61VPS51218B-250B2I IS61VPS51218B-250B3I IS61VPS51218B-200B2I IS61VPS51218B-200B3I 100 QFP, 3CE, Lead-free 119 BGA 165 BGA 119 BGA 165 BGA 512Kx18 Note: 1. For 100 QFP, 2CE option contact SRAM Marketing at sram@issi.com ORDERING INFORMATION (Vdd 1.8V/Vddq = 1.8V) Please contact SRAM Marketing at sram@issi.com Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 31 Rev. B3 05/26/2017 IS61LPS51218B, IS61LPS25636B, IS61LPS25632B, IS64LPS25636B, IS61VPS/VVPS51218B, IS61VPS/VVPS25636B 32 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B3 05/26/2017 IS61LPS51218B, IS61LPS25636B, IS61LPS25632B, IS64LPS25636B, IS61VPS/VVPS51218B, IS61VPS/VVPS25636B Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 33 Rev. B3 05/26/2017 34 Package Outline 1. CONTROLLING DIMENSION : MM . NOTE : 08/28/2008 IS61LPS51218B, IS61LPS25636B, IS61LPS25632B, IS64LPS25636B, IS61VPS/VVPS51218B, IS61VPS/VVPS25636B Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B3 05/26/2017