IS61LV12816-10BI

IS61LV12816 128K x 16 HIGH-SPEED CMOS STATIC RAM WITH 3.3V SUPPLY FEATURES • • • • • High-speed access time: 10, 12, and 15 ns CMOS low power operation TTL and CMOS compatible interface levels Single 3.3V ± 10% power supply Fully static operation: no clock or refresh required • Three state outputs • Data control for upper and lower bytes • Industrial temperature available ISSI DESCRIPTION ® FEBRUARY 2003 The ISSI IS61LV12816 is a high-speed, 2,097,152-bit static RAM organized as 131,072 words by 16 bits. It is fabricated using ISSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields access times as fast as 10 ns with low power consumption. When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs, CE and OE. The active LOW Write Enable (WE) controls both writing and reading of the memory. A data byte allows Upper Byte (UB) and Lower Byte (LB) access. The IS61LV12816 is packaged in the JEDEC standard 44pin 400-mil SOJ, 44-pin TSOP (Type II), 44-pin LQFP, and 48-pin mini BGA (6mm x 8mm). FUNCTIONAL BLOCK DIAGRAM A0-A16 DECODER 128K x 16 MEMORY ARRAY VDD GND I/O0-I/O7 Lower Byte I/O8-I/O15 Upper Byte I/O DATA CIRCUIT COLUMN I/O CE OE WE UB LB Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. CONTROL CIRCUIT Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. C 02/05/2003 1 I S61LV12816 PIN CONFIGURATIONS 44-Pin SOJ (K) A4 A3 A2 A1 A0 CE I/O0 I/O1 I/O2 I/O3 VDD GND I/O4 I/O5 I/O6 I/O7 WE A16 A15 A14 A13 A12 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE UB LB I/O15 I/O14 I/O13 I/O12 GND VDD I/O11 I/O10 I/O9 I/O8 NC A8 A9 A10 A11 NC ISSI 44-Pin TSOP-II (T) A4 A3 A2 A1 A0 CE I/O0 I/O1 I/O2 I/O3 VDD GND I/O4 I/O5 I/O6 I/O7 WE A16 A15 A14 A13 A12 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE UB LB I/O15 I/O14 I/O13 I/O12 GND VDD I/O11 I/O10 I/O9 I/O8 NC A8 A9 A10 A11 NC ® 48-Pin mini BGA (B) 1 2 3 4 5 6 44-Pin LQFP (LQ) A16 A15 A14 A13 A12 A11 A10 A9 OE UB LB A B C D E F G H LB I/O8 I/O9 GND VDD I/O14 I/O15 NC OE UB I/O10 I/O11 I/O12 I/O13 NC A8 A0 A3 A5 NC NC A14 A12 A9 A1 A4 A6 A7 A16 A15 A13 A10 A2 CE I/O1 I/O3 I/O4 I/O5 WE A11 N/C I/O0 I/O2 VDD GND I/O6 I/O7 NC CE I/O0 I/O1 I/O2 I/O3 VDD GND I/O4 I/O5 I/O6 I/O7 44 43 42 41 40 39 38 37 36 35 345 33 1 32 2 31 3 30 4 29 5 TOP VIEW 28 6 27 7 26 8 25 9 24 10 23 11 12 13 14 15 16 17 18 19 20 21 22 WE A0 A1 A2 A3 A4 NC A5 A6 A7 A8 I/O15 I/O14 I/O13 I/O12 GND VDD I/O11 I/O10 I/O9 I/O8 NC 2 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. C 02/05/2003 I S61LV12816 PIN DESCRIPTIONS A0-A16 I/O0-I/O15 CE OE WE LB UB NC VDD GND Address Inputs Data Inputs/Outputs Chip Enable Input Output Enable Input Write Enable Input Lower-byte Control (I/O0-I/O7) Upper-byte Control (I/O8-I/O15) No Connection Power Ground ISSI OPERATING RANGE Range Commercial Industrial Ambient Temperature 0°C to + 70°C –40°C to + 85°C VDD 3.3V ± 10% 3.3V ± 10% ® ABSOLUTE MAXIMUM RATINGS(1) Symbol VDD VTERM TSTG PT IOUT Parameter Power Supply Voltage Relative to GND Terminal Voltage with Respect to GND Storage Temperature Power Dissipation DC Output Current Value –0.3 to 4.0 –0.5 to VDD + 0.5 –65 to + 150 1.0 ±20 Unit V V °C W mA Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Symbol VOH VOL VIH VIL ILI ILO Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage(1) Input LOW Voltage(1) Input Leakage Output Leakage GND ≤ VIN ≤ VDD GND ≤ VOUT ≤ VDD, Outputs Disabled Test Conditions VDD = Min., IOH = –4.0 mA VDD = Min., IOL = 8.0 mA Min. 2.4 — 2 –0.3 –1 –1 Max. — 0.4 VDD + 0.3 0.8 1 1 Unit V V V V µA µA Note: 1. VIL (min.) = –0.3V DC; VIL (min.) = –2.0V AC (pulse width - 2.0 ns). VIH (max.) = VDD + 0.3V DC; VIH (max.) = VDD + 2.0V AC (pulse width - 2.0 ns). Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. C 02/05/2003 3 I S61LV12816 TRUTH TABLE Mode Not Selected Output Disabled Read WE X H X H H H L L L CE H L L L L L L L L OE X H X L L L X X X LB X X H L H L L H L UB X X H H L L H L L I/O PIN I/O0-I/O7 I/O8-I/O15 High-Z High-Z High-Z DOUT High-Z DOUT DIN High-Z DIN High-Z High-Z High-Z High-Z DOUT DOUT High-Z DIN DIN ISSI VDD Current ISB1, ISB2 ICC ICC ® Write ICC POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) Symbol ICC ISB1 Parameter VDD Operating Supply Current TTL Standby Current (TTL Inputs) CMOS Standby Current (CMOS Inputs) Test Conditions VDD = Max., CE = VIL IOUT = 0 mA, f = Max. VDD = Max., VIN = VIH or VIL CE ≥ VIH, f = max VDD = Max., CE ≥ VDD – 0.2V, VIN ≥ VDD – 0.2V, or VIN ≤ 0.2V, f = 0 Com. Ind. Com. Ind. Com. Ind. -10 ns Min. Max. — — — — — — 125 135 40 50 10 20 -12 ns Min. Max. — — — — — — 110 120 35 45 10 20 -15 ns Min. Max. — — — — — — 90 100 30 40 10 20 Unit mA mA ISB2 mA Note: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 4 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. C 02/05/2003 I S61LV12816 CAPACITANCE(1) Symbol CIN COUT Parameter Input Capacitance Input/Output Capacitance Conditions VIN = 0V VOUT = 0V Max. 6 8 Unit pF pF ISSI ® Note: 1. Tested initially and after any design or process changes that may affect these parameters. READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter -10 ns Min. Max. 10 — 3 — — — 0 0 3 — 0 0 — 10 — 10 4 4 — 4 — 4 4 — -12 ns Min. Max. 12 — 3 — — — 0 0 3 — 0 0 — 12 — 12 5 5 — 5 — 5 5 — -15 ns Min. Max. 15 — 3 — — 0 0 0 3 — 0 0 — 15 — 15 6 6 — 8 — 6 6 — Unit ns ns ns ns ns ns ns ns ns ns ns ns tRC tAA tOHA tACE tDOE tHZOE (2) Read Cycle Time Address Access Time Output Hold Time CE Access Time OE Access Time OE to High-Z Output OE to Low-Z Output CE to High-Z Output CE to Low-Z Output LB, UB Access Time LB, UB to High-Z Output LB, UB to Low-Z Output tLZOE(2) tHZCE(2) tLZCE tBA tHZB(2) tLZB(2) (2) Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to 3.0V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. C 02/05/2003 5 I S61LV12816 AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0V to 3.0V 3 ns 1.5V See Figures 1 and 2 ISSI ® AC TEST LOADS 319 Ω 3.3V 319 Ω 3.3V OUTPUT 30 pF Including jig and scope 353 Ω OUTPUT 5 pF Including jig and scope 353 Ω Figure 1. Figure 2. 6 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. C 02/05/2003 I S61LV12816 AC WAVEFORMS READ CYCLE NO. 1(1,2) (Address Controlled) (CE = OE = VIL, UB or LB = VIL) t RC ADDRESS ISSI ® t AA t OHA DOUT PREVIOUS DATA VALID t OHA DATA VALID READ1.eps READ CYCLE NO. 2(1,3) t RC ADDRESS t AA OE t OHA t DOE CE t HZOE t LZOE t ACE t LZCE t HZCE LB, UB DOUT HIGH-Z t LZB t BA DATA VALID t HZB UB_CEDR2.eps Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE, UB, or LB = VIL. 3. Address is valid prior to or coincident with CE LOW transition. Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. C 02/05/2003 7 I S61LV12816 WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range) Symbol Parameter -10 ns Min. Max. 10 8 8 0 0 8 7 8 5 0 — 0 — — — — — — — — — — 4 — -12 ns Min. Max. 12 8 8 0 0 9 8 10 6 0 — 0 — — — — — — — — — — 5 — -15 ns Min. Max. 15 10 10 0 0 10 10 11 7 0 — 0 — — — — — — — — — — 6 — Unit ns ns ns ns ns ns ns ns ns ns ns ns ISSI ® tWC tSCE tAW tHA tSA tPWB tPWE1 tPWE2 tSD tHD tLZWE (3) Write Cycle Time CE to Write End Address Setup Time to Write End Address Hold from Write End Address Setup Time LB, UB Valid to End of Write WE Pulse Width (OE = HIGH) WE Pulse Width (OE = LOW) Data Setup to Write End Data Hold from Write End WE HIGH to Low-Z Output tHZWE(3) WE LOW to High-Z Output Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to 3.0V and output loading specified in Figure 1. 2. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. 3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 8 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. C 02/05/2003 I S61LV12816 WRITE CYCLE NO. 1(1,2) (CE Controlled, OE = HIGH or LOW) ISSI t WC VALID ADDRESS ® ADDRESS t SA CE t SCE t HA WE t AW t PWE1 t PWE2 t PBW UB, LB t HZWE DOUT DATA UNDEFINED HIGH-Z t LZWE t SD DIN t HD DATAIN VALID UB_CEWR1.eps Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. C 02/05/2003 9 I S61LV12816 WRITE CYCLE NO. 2(1) (WE Controlled, OE = HIGH during Write Cycle) t WC ADDRESS VALID ADDRESS ISSI t HA ® OE CE LOW t AW t PWE1 WE t SA UB, LB t PBW t HZWE DOUT DATA UNDEFINED HIGH-Z t LZWE t SD DIN t HD DATAIN VALID UB_CEWR2.eps WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle) t WC ADDRESS VALID ADDRESS OE CE LOW t HA LOW t AW t PWE2 WE t SA UB, LB t PBW t HZWE DOUT DATA UNDEFINED HIGH-Z t LZWE t SD DIN t HD DATAIN VALID UB_CEWR3.eps 10 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. C 02/05/2003 I S61LV12816 WRITE CYCLE NO. 4 (LB, UB Controlled, Back-to-Back Write) (1,3) t WC ADDRESS ADDRESS 1 ISSI t WC ADDRESS 2 ® OE t SA CE LOW WE t HA t SA t PBW t PBW WORD 2 t HA UB, LB WORD 1 t HZWE DOUT HIGH-Z t LZWE t HD DATAIN VALID DATA UNDEFINED t SD DIN t SD DATAIN VALID t HD UB_CEWR4.eps Notes: 1. The internal Write time is defined by the overlap of CE = LOW, UB and/or LB = LOW, and WE = LOW. All signals must be in valid states to initiate a Write, but any can be deasserted to terminate the Write. The t SA, t HA, t SD, and t HD timing is referenced to the rising or falling edge of the signal that terminates the Write. 2. Tested with OE HIGH for a minimum of 4 ns before WE = LOW to place the I/O in a HIGH-Z state. 3. WE may be held LOW across many address cycles and the LB, UB pins can be used to control the Write function. Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. C 02/05/2003 11 I S61LV12816 IS61LV12816 STANDARD VERSION ORDERING INFORMATION Commercial Range: 0°C to +70°C Speed (ns) 10 Order Part No. IS61LV12816-10B IS61LV12816-10K IS61LV12816-10LQ IS61LV12816-10T IS61LV12816-12B IS61LV12816-12K IS61LV12816-12LQ IS61LV12816-12T IS61LV12816-15B IS61LV12816-15LQ IS61LV12816-15T Package mini BGA (6mm x 8mm) 400-mil Plastic SOJ LQFP Plastic TSOP-II mini BGA (6mm x 8mm) 400-mil Plastic SOJ LQFP Plastic TSOP-II mini BGA (6mm x 8mm) LQFP Plastic TSOP-II ISSI ® 12 15 IS61LV12816 STANDARD VERSION ORDERING INFORMATION Industrial Range: –40°C to +85°C Speed (ns) 10 Order Part No. IS61LV12816-10BI IS61LV12816-10KI IS61LV12816-10LQI IS61LV12816-10TI IS61LV12816-12LQI IS61LV12816-12TI IS61LV12816-15BI IS61LV12816-15LQI IS61LV12816-15TI Package mini BGA (6mm x 8mm) 400-mil Plastic SOJ LQFP Plastic TSOP-II LQFP Plastic TSOP-II mini BGA (6mm x 8mm) LQFP Plastic TSOP-II 12 15 12 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. C 02/05/2003