IS61LV12824-8BL

IS61LV12824 128K x 24 HIGH-SPEED CMOS STATIC RAM WITH 3.3V SUPPLY FEATURES • High-speed access time: 8, 10 ns • CMOS low power operation — 756 mW (max.) operating @ 8 ns — 36 mW (max.) standby @ 8 ns • TTL compatible interface levels • Single 3.3V power supply • Fully static operation: no clock or refresh required • Three state outputs • Available in 119-pin Plastic Ball Grid Array (PBGA) and 100-pin TQFP packages. • Industrial temperature available • Lead-free available ISSI JUNE 2005 ® DESCRIPTION The ISSI IS61LV12824 is a high-speed, static RAM organized as 131,072 words by 24 bits. It is fabricated using ISSI's highperformance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields access times as fast as 8 ns with low power consumption. When CE1, CE2 are HIGH and CE2 is LOW (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs, CE1, CE2, CE2 and OE. The active LOW Write Enable (WE) controls both writing and reading of the memory. The IS61LV12824 is packaged in the JEDEC standard 119-pin PBGA and 100-pin TQFP. FUNCTIONAL BLOCK DIAGRAM A0-A16 DECODER 128K x 24 MEMORY ARRAY VCC GND I/O DATA CIRCUIT I/O0-I/O23 COLUMN I/O CE2 CE1 CE2 OE WE CONTROL CIRCUIT Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. D 06/22/05 1 IS61LV12824 ISSI PIN DESCRIPTIONS 6 A4 A3 NC VCCQ GND VCCQ GND VCCQ GND VCCQ GND VCCQ GND VCCQ NC A1 A2 7 NC NC I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 VCCQ I/O6 I/O7 I/O8 I/O9 I/O10 I/O11 NC NC A0-A16 CE1, CE2 CE2 OE WE NC Vcc VCCQ GND Address Inputs Chip Enable Input LOW I/O0-I/O23 Data Inputs/Outputs 3 A14 A13 CE2 GND VCC GND VCC GND VCC GND VCC GND VCC GND NC A8 A7 4 A15 CE1 NC GND GND GND GND GND GND GND GND GND GND GND NC WE OE 5 A16 A5 CE2 GND VCC GND VCC GND VCC GND VCC GND VCC GND NC A0 A6 ® PIN CONFIGURATION - 119-pin PBGA 1 A B C D E F G H J K L M N P R T U NC NC I/O16 I/O17 I/O18 I/O19 I/O20 I/O21 VCCQ I/O22 I/O23 I/O12 I/O13 I/O14 I/O15 NC NC 2 A11 A12 NC VCCQ GND VCCQ GND VCCQ GND VCCQ GND VCCQ GND VCCQ NC A10 A9 Chip Enable Input HIGH Output Enable Input Write Enable Input No Connection Power I/O Power Ground 2 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. D 06/22/05 IS61LV12824 PIN CONFIGURATION 100-Pin TQFP NC NC A11 A12 A13 A14 A15 CE2 Vcc GND CE2 CE1 A16 A5 A4 A3 NC NC NC NC ISSI ® 1 NC Vcc GND I/O0 I/O1 GND VccQ I/O2 I/O3 GND VccQ I/O4 I/O5 Vcc NC NC GND I/O6 I/O7 VccQ GND I/O8 I/O9 VccQ GND I/O10 I/O11 Vcc GND NC NC Vcc GND I/O16 I/O17 GND VccQ I/O18 I/O19 GND VccQ I/O20 I/O21 Vcc NC NC GND I/O22 I/O23 VccQ GND I/O12 I/O13 VccQ GND I/O14 I/O15 Vcc GND NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 1 79 2 78 3 77 4 76 5 75 6 74 7 73 8 72 9 71 10 70 11 69 12 68 13 67 14 66 15 65 16 64 17 63 18 62 19 61 20 60 21 59 22 58 23 57 24 56 25 55 26 54 27 53 28 52 29 51 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 2 3 4 5 6 7 8 9 10 11 12 PIN DESCRIPTIONS A0-A16 I/O0-I/O23 CE1, CE2 CE2 OE WE NC Vcc VCCQ GND Address Inputs Data Inputs/Outputs Chip Enable Input LOW Chip Enable Input HIGH Output Enable Input Write Enable Input No Connection Power I/O Power Ground Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. D 06/22/05 NC NC NC NC A10 A9 A8 A7 OE GND Vcc WE A6 A0 A1 A2 NC NC NC NC 3 IS61LV12824 TRUTH TABLE Mode Not Selected WE X X X H H L CE1 H X X L L L CE2 X L X H H H CE2 X X H L L L OE X X X H L X I/O0-I/O23 High-Z Vcc Current ISB1, ISB2 ISSI High-Z DOUT DIN ICC ICC ICC ® Output Disabled Read Write ABSOLUTE MAXIMUM RATINGS(1) Symbol VCC VTERM TSTG TBIAS PT IOUT Parameter Power Supply Voltage Relative to GND Terminal Voltage with Respect to GND Storage Temperature Temperature Under Bias: Com. Ind. Power Dissipation DC Output Current Value –0.5 to 5.0 –0.5 to Vcc + 0.5 –65 to + 150 –10 to + 85 –45 to + 90 2.0 ±20 Unit V V °C °C °C W mA Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. OPERATING RANGE Range Commercial Industrial Ambient Temperature 0°C to +70°C –40°C to +85°C VCC (8 ns) 3.3V + 10%, – 5% 3.3V + 10%, – 5% VCC (10 ns) 3.3V ± 10% 3.3V ± 10% DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Symbol VOH VOL VIH VIL ILI ILO Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage(1) GND ≤ VIN ≤ VCC GND ≤ VOUT ≤ VCC, Outputs Disabled Input Leakage Output Leakage Test Conditions VCC = Min., IOH = –4.0 mA VCC = Min., IOL = 8.0 mA Min. 2.4 — 2.2 –0.3 –1 –1 Max. — 0.4 VCC + 0.3 0.8 1 1 Unit V V V V µA µA Note: 1. VIL (min.) = –0.3V DC; VIL (min.) = –2.0V AC (pulse width ≤ 2.0 ns). VIH (max.) = VCC + 0.3V DC; VIH (max.) = VCC + 2.0V AC (pulse width ≤ 2.0 ns). 4 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. D 06/22/05 IS61LV12824 POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) -8 ns Symbol ICC ISB1 Parameter Vcc Dynamic Operating Supply Current TTL Standby Current (TTL Inputs) CMOS Standby Current (CMOS Inputs) Test Conditions VCC = Max., IOUT = 0 mA, f = fMAX Com. Ind. Min. Max. ISSI -10 ns Min. Max. ® Unit mA mA — — — — — — 210 240 70 80 10 20 — — — — — — 180 210 50 55 10 20 1 2 VCC = Max., Com. VIN = VIH or VIL, f = max. Ind. CE1, CE2, ≥ VIH, CE2 ≤ VIL VCC = Max., Com. CE1, CE2 ≥ VCC – 0.2V, Ind. CE2 ≤ 0.2V, VIN ≥ VCC – 0.2V, or VIN ≤ 0.2V, f = 0 ISB2 mA 3 4 5 6 7 8 9 Note: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. CAPACITANCE Symbol CIN COUT (1) Parameter Input Capacitance Input/Output Capacitance Conditions VIN = 0V VOUT = 0V Max. 6 8 Unit pF pF Note: 1. Tested initially and after any design or process changes that may affect these parameters. AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0V to 3.0V 2 ns 1.5V See Figures 1 and 2 AC TEST LOADS 319 Ω 10 11 353 Ω ZO = 50Ω OUTPUT 50Ω 3.3V OUTPUT 5 pF Including jig and scope 1.5V 12 Figure 1 Figure 2 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. D 06/22/05 5 IS61LV12824 READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter Read Cycle Time Address Access Time Output Hold Time CE1, CE2 Access Time CE2 Access Time OE Access Time (2) ISSI -8 Min. Max. 8 — 3 8 — 0 0 0 3 — 8 — — 4 3 — 4 — Min. 10 — 3 — — 0 0 0 3 -10 Max. — 10 — 10 4 3 — 5 — Unit ns ns ns ns ns ns ns ns ns ® tRC tAA tOHA tACE tACE2 tDOE tHZOE tLZOE (2) OE to High-Z Output OE to Low-Z Output CE1, CE2 to High-Z Output CE2 to High-Z Output CE, CE2 to Low-Z Output CE2 to Low-Z Output tHZCE(2) tHZCE2(2) tLZCE(2) tLZCE2(2) Notes: 1. Test conditions assume signal transition times of 2 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±200 mV from steady-state voltage. Not 100% tested. 6 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. D 06/22/05 IS61LV12824 AC WAVEFORMS READ CYCLE NO. 1(1,2) (Address Controlled) (CE1 = CE2 = OE = VIL; CE2 = VIH) ISSI t RC ® 1 t OHA DATA VALID READ1.eps ADDRESS t AA t OHA DOUT PREVIOUS DATA VALID 2 3 4 READ CYCLE NO. 2(1,3) t RC ADDRESS 5 t AA t OHA OE 6 t DOE t HZOE t LZOE CS1 7 8 t HZCS1 t HZCS2 DATA VALID CS2_RD2.eps CS2 t LZCS1 t LZCS2 DOUT HIGH-Z t ACS1 t ACS2 9 10 11 12 Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE1, CE2 = VIL. CE2 = VIH. 3. Address is valid prior to or coincident with CE1, CE2 LOW and CE2 HIGH transition. Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. D 06/22/05 7 IS61LV12824 WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range) Symbol Parameter Write Cycle Time CE1, CE2 to Write End CE2 to Write End Address Setup Time to Write End Address Hold from Write End Address Setup Time WE Pulse Width (OE = HIGH) WE Pulse Width (OE = LOW) Data Setup to Write End Data Hold from Write End WE LOW to High-Z Output WE HIGH to Low-Z Output -8 Min. Max. 8 7 7 7 0 0 6 6 4.5 0 — 3 — — — — — — — — — — 3.5 — -10 Min. 10 8 8 8 0 0 8 9 5 0 — 3 Max. — — — — — — — — — — 3.5 — ISSI Unit ns ns ns ns ns ns ns ns ns ns ns ® tWC tSCE tSCE2 tAW tHA tSA tPWE1 tPWE2 tSD tHD tHZWE(2) tLZWE(2) Notes: 1. Test conditions assume signal transition times of 2 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±200 mV from steady-state voltage. Not 100% tested. 3. The internal write time is defined by the overlap of CE1, CE2 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. 8 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. D 06/22/05 IS61LV12824 WRITE CYCLE NO. 1 (CE Controlled, OE = HIGH or LOW) ISSI t WC VALID ADDRESS ® ADDRESS 1 t HA t SA CE1 t SCE1 t SCE2 2 3 t LZWE HIGH-Z CE2 WE t AW t PWE1 t PWE2 t HZWE 4 5 CE2_WR1.eps DOUT DATA UNDEFINED t SD DIN t HD DATAIN VALID 6 7 WRITE CYCLE NO. 2(1) (WE Controlled: OE = HIGH during Write Cycle) t WC ADDRESS VALID ADDRESS t HA OE 8 9 CE1 CE2 WE LOW HIGH t AW t PWE1 t SA t HZWE DATA UNDEFINED HIGH-Z 10 t LZWE 11 12 CE2_WR2.eps DOUT t SD DIN t HD DATAIN VALID Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. D 06/22/05 9 IS61LV12824 WRITE CYCLE NO. 3(1) (WE Controlled: OE I S LOW DURING WRITE CYLE) ISSI t WC VALID ADDRESS ® ADDRESS OE CE1 LOW LOW HIGH t HA CE2 t AW t PWE2 WE t SA DOUT DATA UNDEFINED t HZWE HIGH-Z t LZWE t SD DIN t HD DATAIN VALID CE2_WR3.eps Note: 1. The internal Write time is defined by the overlap of CE1 and CE2 = LOW, CE2 = HIGH and WE = LOW. All signals must be in valid states to initiate a Write, but any can be deasserted to terminate the Write. The Data Input Setup and Hold timing is referenced to the rising or falling edge of the signal that terminates the Write. 10 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. D 06/22/05 IS61LV12824 ISSI Package Plastic Ball Grid Array Plastic Ball Grid Array, Lead-free TQFP Plastic Ball Grid Array Plastic Ball Grid Array, Lead-free TQFP ® ORDERING INFORMATION Commercial Range: 0°C to +70°C Speed (ns) Order Part No. 8 IS61LV12824-8B IS61LV12824-8BL IS61LV12824-8TQ IS61LV12824-10B IS61LV12824-10BL IS61LV12824-10TQ 1 2 3 4 5 6 7 8 9 10 11 12 10 Industrial Range: –40°C to +85°C Speed (ns) 8 10 Order Part No. IS61LV12824-8BI IS61LV12824-10BI IS61LV12824-10TQI IS61LV12824-10TQLI Package Plastic Ball Grid Array Plastic Ball Grid Array TQFP TQFP, Lead-free Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. D 06/22/05 11 PACKAGING INFORMATION Plastic Ball Grid Array Package Code: B (119-pin) ISSI φ b (119X) 7 6 5 4 32 1 A B C D E F G H J K L M N P R T U ® E A 30ϒ D D2 D1 e A2 E2 A3 A1 E1 A4 SEATING PLANE MILLIMETERS Sym. N0. Leads A A1 A2 A3 A4 b D D1 D2 E E1 E2 e — 0.50 0.80 1.30 0.60 21.80 19.40 13.80 11.90 INCHES Min. Max. Notes: Min. 119 Max. 2.41 0.70 1.00 1.70 0.90 22.20 19.60 14.20 12.10 — 0.020 0.032 0.051 0.024 0.858 0.764 0.543 0.469 0.095 0.028 0.039 0.067 0.035 0.874 0.772 0.559 0.476 1. Controlling dimension: millimeters, unless otherwise specified. 2. BSC = Basic lead spacing between centers. 3. Dimensions D1 and E do not include mold flash protrusion and should be measured from the bottom of the package. 4. Formed leads shall be planar with respect to one another within 0.004 inches at the seating plane. 0.56 BSC 0.022 BSC 20.32 BSC 0.800 BSC 7.62 BSC 1.27 BSC 0.300 BSC 0.050 BSC Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B 02/12/03 PACKAGING INFORMATION TQFP (Thin Quad Flat Pack Package) Package Code: TQ ISSI D D1 ® E E1 N 1 C e SEATING PLANE L1 L A2 A1 b A Millimeters Symbol Min Max Ref. Std. No. Leads (N) 100 A — 1.60 — 0.063 A1 0.05 0.15 0.002 0.006 A2 1.35 1.45 0.053 0.057 b 0.22 0.38 0.009 0.015 D 21.90 22.10 0.862 0.870 D1 19.90 20.10 0.783 0.791 E 15.90 16.10 0.626 0.634 E1 13.90 14.10 0.547 0.555 e 0.65 BSC 0.026 BSC L 0.45 0.75 0.018 0.030 L1 1.00 REF. 0.039 REF. C 0o 7o 0o 7o Thin Quad Flat Pack (TQ) Inches Millimeters Min Max Min Max 128 — 1.60 0.05 0.15 1.35 1.45 0.17 0.27 21.80 22.20 19.90 20.10 15.80 16.20 13.90 14.10 0.50 BSC 0.45 0.75 1.00 REF. 0o 7o Inches Min Max — 0.063 0.002 0.006 0.053 0.057 0.007 0.011 0.858 0.874 0.783 0.791 0.622 0.638 0.547 0.555 0.020 BSC 0.018 0.030 0.039 REF. 0o 7o Notes: 1. All dimensioning and tolerancing conforms to ANSI Y14.5M-1982. 2. Dimensions D1 and E1 do not include mold protrusions. Allowable protrusion is 0.25 mm per side. D1 and E1 do include mold mismatch and are determined at datum plane -H-. 3. Controlling dimension: millimeters. Integrated Silicon Solution, Inc. — 1-800-379-4774 PK13197LQ Rev. D 05/08/03