IS61LV25616AL-12K

IS61LV25616AL 256K x 16 HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM WITH 3.3V SUPPLY FEATURES • High-speed access time: — 10, 12 ns • CMOS low power operation • Low stand-by power: — Less than 5 mA (typ.) CMOS stand-by • TTL compatible interface levels • Single 3.3V power supply • Fully static operation: no clock or refresh required • Three state outputs • Data control for upper and lower bytes • Industrial temperature available ISSI FEBRUARY 2003 ® DESCRIPTION The ISSI IS61LV25616AL is a high-speed, 4,194,304-bit static RAM organized as 262,144 words by 16 bits. It is fabricated using ISSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields high-performance and low power consumption devices. When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs, CE and OE. The active LOW Write Enable (WE) controls both writing and reading of the memory. A data byte allows Upper Byte (UB) and Lower Byte (LB) access. The IS61LV25616AL is packaged in the JEDEC standard 44-pin 400-mil SOJ, 44-pin TSOP Type II, 44-pin LQFP and 48-pin Mini BGA (8mm x 10mm). FUNCTIONAL BLOCK DIAGRAM A0-A17 DECODER 256K x 16 MEMORY ARRAY VDD GND I/O0-I/O7 Lower Byte I/O8-I/O15 Upper Byte I/O DATA CIRCUIT COLUMN I/O CE OE WE UB LB CONTROL CIRCUIT Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A 02/21/03 1 IS61LV25616AL ISSI WE X H X H H H L L L CE H L L L L L L L L OE X H X L L L X X X LB X X H L H L L H L UB X X H H L L H L L I/O PIN I/O0-I/O7 I/O8-I/O15 High-Z High-Z High-Z DOUT High-Z DOUT DIN High-Z DIN High-Z High-Z High-Z High-Z DOUT DOUT High-Z DIN DIN VDD Current ISB1, ISB2 ICC I CC ® TRUTH TABLE Mode Not Selected Output Disabled Read Write I CC PIN CONFIGURATIONS 44-Pin TSOP (Type II) and SOJ PIN DESCRIPTIONS A0-A17 I/O0-I/O15 CE Address Inputs Data Inputs/Outputs Chip Enable Input Output Enable Input Write Enable Input Lower-byte Control (I/O0-I/O7) Upper-byte Control (I/O8-I/O15) No Connection Power Ground A0 A1 A2 A3 A4 CE I/O0 I/O1 I/O2 I/O3 VDD GND I/O4 I/O5 I/O6 I/O7 WE A5 A6 A7 A8 A9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A17 A16 A15 OE UB LB I/O15 I/O14 I/O13 I/O12 GND VDD I/O11 I/O10 I/O9 I/O8 NC A14 A13 A12 A11 A10 OE WE LB UB NC VDD GND 2 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A 02/21/03 IS61LV25616AL ISSI 48-Pin mini BGA 1 2 3 4 5 6 ® PIN CONFIGURATIONS 44-Pin LQFP 1 2 CE I/O0 I/O1 I/O2 I/O3 VDD GND I/O4 I/O5 I/O6 I/O7 44 43 42 41 40 39 38 37 36 35 34 33 1 32 2 31 3 30 4 29 5 TOP VIEW 28 6 27 7 26 8 25 9 24 10 23 11 12 13 14 15 16 17 18 19 20 21 22 WE A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A17 A16 A15 A14 A13 A12 A11 A10 OE UB LB I/O15 I/O14 I/O13 I/O12 GND VDD I/O11 I/O10 I/O9 I/O8 NC A B C D E F G H LB I/O8 I/O9 GND VDD I/O14 I/O15 NC OE UB I/O10 I/O11 I/O12 I/O13 NC A8 A0 A3 A5 A17 NC A14 A12 A9 A1 A4 A6 A7 A16 A15 A13 A10 A2 CE I/O1 I/O3 I/O4 I/O5 WE A11 N/C I/O0 I/O2 VDD GND I/O6 I/O7 NC 3 4 5 6 7 PIN DESCRIPTIONS A0-A17 I/O0-I/O15 CE OE WE LB UB NC VDD GND Address Inputs Data Inputs/Outputs Chip Enable Input Output Enable Input Write Enable Input Lower-byte Control (I/O0-I/O7) Upper-byte Control (I/O8-I/O15) No Connection Power Ground 8 9 10 11 12 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A 02/21/03 3 IS61LV25616AL ISSI Value –0.5 to VDD+0.5 –65 to +150 1.0 Unit V °C W ® ABSOLUTE MAXIMUM RATINGS(1) Symbol Parameter VTERM TSTG PT Terminal Voltage with Respect to GND Storage Temperature Power Dissipation Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. OPERATING RANGE VDD Range Commercial Industrial Ambient Temperature 0°C to +70°C –40°C to +85°C 10ns 3.3V +10%, -5% 3.3V +10%, -5% 12ns 3.3V + 10% 3.3V + 10% DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Symbol VOH VOL VIH VIL ILI ILO Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage(1) Input Leakage Output Leakage GND ≤ VIN ≤ VDD GND ≤ VOUT ≤ VDD Outputs Disabled Com. Ind. Com. Ind. Test Conditions VDD = Min., IOH = –4.0 mA VDD = Min., IOL = 8.0 mA Min. 2.4 — 2.0 –0.3 –2 –5 –2 –5 Max. — 0.4 VDD + 0.3 0.8 2 5 2 5 Unit V V V V µA µA Notes: 1. VIL (min.) = –2.0V for pulse width less than 10 ns. 4 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A 02/21/03 IS61LV25616AL ISSI Test Conditions VDD = Max., Com. IOUT = 0 mA, f = fMAX Ind. VDD = Max., VIN = VIH or VIL CE ≥ VIH, f = fMAX. VDD = Max., VIN = VIH or VIL CE ≥ VIH, f = 0 Com. Ind. Com. Ind. -10 Min. Max. — — — — — — — — 100 110 50 55 20 25 15 20 -12 Min. Max. — — — — — — — — 90 100 45 50 20 25 15 20 Unit mA mA ® POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter ICC ISB VDD Dynamic Operating Supply Current TTL Standby Current (TTL Inputs) TTL Standby Current (TTL Inputs) CMOS Standby Current (CMOS Inputs) 1 2 3 4 5 6 ISB1 mA ISB2 VDD = Max., Com. CE ≥ VDD – 0.2V, Ind. VIN ≥ VDD – 0.2V, or VIN ≤ 0.2V, f = 0 mA Note: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. Shaded area product in development CAPACITANCE Symbol CIN COUT (1) Parameter Input Capacitance Input/Output Capacitance Conditions VIN = 0V VOUT = 0V Max. 6 8 Unit pF pF 7 8 9 10 11 12 Note: 1. Tested initially and after any design or process changes that may affect these parameters. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A 02/21/03 5 IS61LV25616AL ISSI -10 Min. Max. 10 — 2 — — — 0 0 3 — 0 0 0 — — 10 — 10 4 4 — 4 — 4 3 — — 10 -12 Min. Max. 12 — 2 — — — 0 0 3 — 0 0 0 — — 12 — 12 5 5 — 6 — 5 4 — — 12 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ® READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter Read Cycle Time Address Access Time Output Hold Time CE Access Time OE Access Time OE to High-Z Output OE to Low-Z Output CE to High-Z Output CE to Low-Z Output LB, UB Access Time LB, UB to High-Z Output LB, UB to Low-Z Output Power Up Time Power Down Time tRC tAA tOHA tACE tDOE tHZOE(2) tLZOE(2) tHZCE(2 tLZCE(2) tBA tHZB(2) tLZB(2) tPU tPD Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to 3.0V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. AC TEST LOADS 319 Ω 3.3V 319 Ω 3.3V OUTPUT 30 pF Including jig and scope 353 Ω OUTPUT 5 pF Including jig and scope 353 Ω Figure 1 Figure 2 AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load 6 Unit 0V to 3.0V 3 ns 1.5V See Figures 1 and 2 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A 02/21/03 IS61LV25616AL ISSI ® AC WAVEFORMS READ CYCLE NO. 1(1,2) (Address Controlled) (CE = OE = VIL, UB or LB = VIL) 1 2 t OHA DATA VALID READ1.eps t RC ADDRESS t AA t OHA DOUT PREVIOUS DATA VALID 3 4 READ CYCLE NO. 2(1,3) tRC ADDRESS 5 6 tAA tOHA tDOE tHZOE OE 7 8 CE tLZOE tACE tLZCE tHZCE LB, UB DOUT HIGH-Z tLZB tBA tRC DATA VALID tHZB VDD Supply Current tPU 50% tPD ICC 50% 9 10 11 12 ISB UB_CEDR2.eps Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE, UB, or LB = VIL. 3. Address is valid prior to or coincident with CE LOW transition. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A 02/21/03 7 IS61LV25616AL ISSI tRC ® READ CYCLE NO. 2(1,3) ADDRESS tAA OE tOHA tDOE CE tHZOE tLZOE tACE tLZCE tHZCE LB, UB DOUT HIGH-Z tLZB tBA tRC DATA VALID tHZB VDD Supply Current tPU 50% tPD ICC 50% ISB UB_CEDR2.eps Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE, UB, or LB = VIL. 3. Address is valid prior to or coincident with CE LOW transition. WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range) Symbol Parameter Write Cycle Time CE to Write End Address Setup Time to Write End Address Hold from Write End Address Setup Time LB, UB Valid to End of Write WE Pulse Width WE Pulse Width (OE = LOW) Data Setup to Write End Data Hold from Write End WE LOW to High-Z Output WE HIGH to Low-Z Output -10 Min. Max. 10 8 8 0 0 8 8 10 6 0 — 2 — — — — — — — — — — 5 — -12 Min. Max. 12 8 8 0 0 8 8 12 6 0 — 2 — — — — — — — — — — 6 — Unit ns ns ns ns ns ns ns ns ns ns ns ns tWC tSCE tAW tHA tSA tPWB tPWE1 tPWE2 tSD tHD tHZWE(2) tLZWE(2) Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to 3.0V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3. The internal write time is defined by the overlap of CE LOW and UB or LB and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. 8 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A 02/21/03 IS61LV25616AL ISSI ® AC WAVEFORMS WRITE CYCLE NO. 1 (CE Controlled, OE is HIGH or LOW) (1 ) t WC ADDRESS VALID ADDRESS 1 t HA t SA CE t SCE 2 3 WE t AW t PWE1 t PWE2 t PBW UB, LB t HZWE DOUT DATA UNDEFINED HIGH-Z t LZWE 4 5 UB_CEWR1.eps t SD DIN t HD DATAIN VALID Notes: 1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CE and WE inputs and at least one of the LB and UB inputs being in the LOW state. 2. WRITE = (CE) [ (LB) = (UB) ] (WE). 6 7 WRITE CYCLE NO. 2 (WE Controlled. OE is HIGH During Write Cycle) (1,2) t WC ADDRESS VALID ADDRESS 8 t HA OE 9 10 CE LOW t AW t PWE1 WE t SA UB, LB t PBW t HZWE DOUT DATA UNDEFINED HIGH-Z t LZWE 11 UB_CEWR2.eps t SD DIN t HD DATAIN VALID 12 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A 02/21/03 9 IS61LV25616AL ISSI ® AC WAVEFORMS WRITE CYCLE NO. 3 (WE Controlled. OE is LOW During Write Cycle) (1) t WC ADDRESS VALID ADDRESS OE CE LOW t HA LOW t AW t PWE2 WE t SA UB, LB t PBW t HZWE DOUT DATA UNDEFINED HIGH-Z t LZWE t SD DIN t HD DATAIN VALID UB_CEWR3.eps WRITE CYCLE NO. 4 (LB, UB Controlled, Back-to-Back Write) (1,3) t WC ADDRESS ADDRESS 1 t WC ADDRESS 2 OE t SA CE LOW WE t HA t SA t PBW t PBW WORD 2 t HA UB, LB WORD 1 t HZWE DOUT HIGH-Z t LZWE t HD DATAIN VALID DATA UNDEFINED t SD DIN t SD DATAIN VALID t HD UB_CEWR4.eps Notes: 1. The internal Write time is defined by the overlap of CE = LOW, UB and/or LB = LOW, and WE = LOW. All signals must be in valid states to initiate a Write, but any can be deasserted to terminate the Write. The t SA, t HA, t SD, and t HD timing is referenced to the rising or falling edge of the signal that terminates the Write. 2. Tested with OE HIGH for a minimum of 4 ns before WE = LOW to place the I/O in a HIGH-Z state. 3. WE may be held LOW across many address cycles and the LB, UB pins can be used to control the Write function. 10 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A 02/21/03 IS61LV25616AL ISSI Test Condition See Data Retention Waveform VDD = 2.0V, CE ≥ VDD – 0.2V See Data Retention Waveform See Data Retention Waveform O ® DATA RETENTION SWITCHING CHARACTERISTICS (LL) Symbol Parameter VDD for Data Retention Data Retention Current Data Retention Setup Time Recovery Time Options Com. Ind. Min. 2.0 — — 0 Typ.(1) — 5 — — — Max. 3.6 10 15 — — Unit V mA ns ns 1 2 3 4 VDR IDR tSDR tRDR tRC Note 1: Typical values are measured at VDD = 3.0V, TA = 25 C and not 100% tested. DATA RETENTION WAVEFORM (CE Controlled) tSDR VDD 1.65V Data Retention Mode tRDR 5 6 1.4V VDR CE ≥ VDD - 0.2V CE GND 7 8 9 10 11 12 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A 02/21/03 11 IS61LV25616AL ISSI Package TSOP (Type II) 400-mil SOJ LQFP Mini BGA (8mm x 10mm) TSOP (Type II) 400-mil SOJ Mini BGA (8mm x 10mm) ® ORDERING INFORMATION Commercial Range: 0°C to +70°C Speed (ns) 10 Order Part No. IS61LV25616AL-10T IS61LV25616AL-10K IS61LV25616AL-10LQ IS61LV25616AL-10B IS61LV25616AL-12T IS61LV25616AL-12K IS61LV25616AL-12B 12 Industrial Range: –40°C to +85°C Speed (ns) 10 Order Part No. IS61LV25616AL-10TI IS61LV25616AL-10KI IS61LV25616AL-10LQI IS61LV25616AL-10BI IS61LV25616AL-12TI IS61LV25616AL-12KI Package TSOP (Type II) 400-mil SOJ LQFP Mini BGA (8mm x 10mm) TSOP (Type II) 400-mil SOJ 12 12 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A 02/21/03