IS61LV2568L-10TL-TR

IS61LV2568L 256K x 8 HIGH-SPEED CMOS STATIC RAM DESCRIPTION The ISSI IS61LV2568L is a very high-speed, low power, FEATURES • • • • • • • • • • APRIL 2008 High-speed access time: 8, 10 ns Operating Current: 50mA (typ.) Standby Current: 700µA (typ.) Multiple center power and ground pins for greater noise immunity Easy memory expansion with CE and OE options CE power-down TTL compatible inputs and outputs Single 3.3V power supply Packages available: – 36-pin 400-mil SOJ – 44-pin TSOP (Type II) Lead-free available 262,144-word by 8-bit CMOS static RAM. The IS61LV2568L is fabricated using ISSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields higher performance and low power consumption devices. When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation can be reduced down to 36mW (max.) with CMOS input levels. The IS61LV2568L operates from a single 3.3V power supply and all inputs are TTL-compatible. The IS61LV2568L is available in 36-pin 400-mil SOJ and 44-pin TSOP (Type II) packages. FUNCTIONAL BLOCK DIAGRAM A0-A17 DECODER 256K X 8 MEMORY ARRAY I/O DATA CIRCUIT COLUMN I/O VDD GND I/O0-I/O7 CE OE CONTROL CIRCUIT WE Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. D 04/28/08 1 IS61LV2568L PIN CONFIGURATION 44-Pin TSOP (Type II) 36-Pin SOJ A4 1 36 NC A3 2 35 A5 A2 3 34 A6 A1 4 33 A7 A0 5 32 A8 CE 6 31 OE I/O0 7 30 I/O7 I/O1 8 29 I/O6 VDD 9 28 GND GND 10 27 VDD I/O2 11 26 I/O5 I/O3 12 25 I/O4 WE 13 24 A9 A17 14 23 A10 A16 15 22 A11 A15 16 21 A12 A14 17 20 NC A13 18 19 NC NC NC A4 A3 A2 A1 A0 CE I/O0 I/O1 VDD GND I/O2 I/O3 WE A17 A16 A15 A14 A13 NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 NC NC NC A5 A6 A7 A8 OE I/O7 I/O6 GND VDD I/O5 I/O4 A9 A10 A11 A12 NC NC NC NC PIN DESCRIPTIONS 2 A0-A17 Address Inputs CE Chip Enable Input OE Output Enable Input WE Write Enable Input I/O0-I/O7 Bidirectional Ports VDD Power GND Ground NC No Connection Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. D 04/28/08 IS61LV2568L TRUTH TABLE Mode WE CE OE I/O Operation VDD Current X H X High-Z ISB1, ISB2 H H L L L L H L X High-Z DOUT DIN ICC ICC ICC Not Selected (Power-down) Output Disabled Read Write ABSOLUTE MAXIMUM RATINGS(1) Symbol VDD VTERM TSTG PD Parameter Supply voltage with Respect to GND Terminal Voltage with Respect to GND Storage Temperature Power Dissipation Value –0.5 to +4.0 –0.5 to VDD + 0.5 –65 to +150 1.0 Unit V V °C W Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. OPERATING RANGE Range Commercial Industrial Ambient Temperature 0°C to +70°C –40°C to +85°C VDD (8ns) 3.3V +10%,-5% VDD (10 ns) 3.3V + 10% 3.3V + 10% DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Symbol Parameter Test Conditions Min. Max. Unit VOH Output HIGH Voltage VDD = Min., IOH = –4.0 mA 2.4 — V VOL Output LOW Voltage VDD = Min., IOL = 8.0 mA — 0.4 V VIH Input HIGH Voltage(1) 2.0 VDD + 0.3 V –0.3 0.8 V (1) VIL Input LOW Voltage ILI Input Leakage GND ≤ VIN ≤ VDD –1 1 µA ILO Output Leakage GND ≤ VOUT ≤ VDD, Outputs Disabled –1 1 µA Note: 1. VIL(min) = –0.3V (DC); VIL(min) = –2.0V (pulse width - 2.0 ns). VIH(max) = VDD + 0.3V (DC); VIH(max) = VDD + 2.0V (pulse width - 2.0 ns). Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. D 04/28/08 3 IS61LV2568L POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) Symbol ICC Parameter Test Conditions VDD Operating Supply Current VDD = Max., CE = VIL IOUT = 0 mA, f = Max. -8 ns Min. Max. Com. Ind. typ.(2) — 65 — 50 -10 ns Min. Max. Unit — — — 60 65 50 mA ISB1 TTL Standby Current (TTL Inputs) VDD = Max., VIN = VIH or VIL CE ≥ VIH, f = max Com. Ind. — 30 — — 25 30 mA ISB2 CMOS Standby Current (CMOS Inputs) VDD = Max., CE ≥ VDD – 0.2V, VIN ≥ VDD – 0.2V, or VIN ≤ 0.2V, f = 0 Com. Ind. typ.(2) — 3 — 700 — — — 3 4 700 mA mA μA Note: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. Typical values are measured at VDD=3.3V, TA=250C. Not 100% tested. CAPACITANCE(1,2) Symbol Parameter CIN Input Capacitance CI/O Input/Output Capacitance Conditions Max. Unit VIN = 0V 6 pF VOUT = 0V 8 pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25°C, f = 1 MHz, VDD = 3.3V. 4 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. D 04/28/08 IS61LV2568L AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Levels Output Load Unit 0V to 3.0V 3 ns 1.5V See Figures 1 and 2 AC TEST LOADS 319 Ω ZO = 50Ω 1.5V OUTPUT 30 pF Including jig and scope Figure 1 3.3V 50Ω OUTPUT 5 pF Including jig and scope Figure 2 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. D 04/28/08 353 Ω 5 IS61LV2568L READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter - 8 ns Min. Max -10 ns Min. Max. Unit tRC Read Cycle Time 8 — 10 — ns tAA Address Access Time — 8 — 10 ns tOHA Output Hold Time 2.5 — 2.5 — ns tACE CE Access Time — 8 — 10 ns tDOE OE Access Time — 3.5 — 4 ns tLZOE(2) OE to Low-Z Output 0 — 0 — ns (2) tHZOE OE to High-Z Output 0 3.5 0 4 ns (2) tLZCE CE to Low-Z Output 3.5 — 3 — ns 0 3.5 0 4 ns tHZCE(2) CE to High-Z Output Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±200 mV from steady-state voltage. Not 100% tested. 6 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. D 04/28/08 IS61LV2568L AC WAVEFORMS READ CYCLE NO. 1(1,2) (Address Controlled) (CE = OE = VIL) t RC ADDRESS t AA t OHA t OHA DOUT DATA VALID PREVIOUS DATA VALID READ1.eps READ CYCLE NO. 2(1,3) (CE and OE Controlled) t RC ADDRESS t AA t OHA OE t HZOE t DOE CE t LZOE t ACE t HZCE t LZCE DOUT HIGH-Z DATA VALID CE_RD2.eps Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE = VIL. 3. Address is valid prior to or coincident with CE LOW transitions. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. D 04/28/08 7 IS61LV2568L WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range) Symbol - 8 ns Min. Max Parameter -10 ns Min. Max. Unit tWC Write Cycle Time 8 — 10 — ns tSCE CE to Write End 7 — 8 — ns tAW Address Setup Time to Write End 7 — 8 — ns tHA Address Hold from Write End 0 — 0 — ns tSA Address Setup Time 0 — 0 — ns tPWE1 WE Pulse Width (OE = HIGH) 6 — 7 — ns tPWE2 WE Pulse Width (OE = LOW) 6.5 — 8 — ns tSD Data Setup to Write End 4 — 5 — ns tHD Data Hold from Write End 0 — 0 — ns (3) WE LOW to High-Z Output — 3 — 4 ns (3) WE HIGH to Low-Z Output 0 — 0 — ns tHZWE tLZWE Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1. 2. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. 3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 8 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. D 04/28/08 IS61LV2568L AC WAVEFORMS WRITE CYCLE NO. 1(1,2) (CE Controlled, OE = HIGH or LOW) t WC VALID ADDRESS ADDRESS t SA t SCE t HA CE t AW t PWE1 t PWE2 WE t HZWE DOUT DATA UNDEFINED t LZWE HIGH-Z t SD DIN t HD DATAIN VALID CE_WR1.eps Note: 1. The internal Write time is defined by the overlap of CE = LOW and WE = LOW. All signals must be in valid states to initiate a Write, but any can be deasserted to terminate the Write. The Data Input Setup and Hold timing is referenced to the rising or falling edge of the signal that terminates the Write. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. D 04/28/08 9 IS61LV2568L AC WAVEFORMS WRITE CYCLE NO. 2(1) (WE Controlled, OE = HIGH during Write Cycle) t WC ADDRESS VALID ADDRESS t HA OE CE LOW t AW t PWE1 WE t SA DOUT t HZWE t LZWE HIGH-Z DATA UNDEFINED t SD t HD DATAIN VALID DIN CE_WR2.eps Note: 1. The internal Write time is defined by the overlap of CE = LOW and WE = LOW. All signals must be in valid states to initiate a Write, but any can be deasserted to terminate the Write. The Data Input Setup and Hold timing is referenced to the rising or falling edge of the signal that terminates the Write. WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle) t WC ADDRESS VALID ADDRESS OE LOW CE LOW t HA t AW t PWE2 WE t SA DOUT DATA UNDEFINED t HZWE t LZWE HIGH-Z t SD DIN t HD DATAIN VALID CE_WR3.eps Note: 1. The internal Write time is defined by the overlap of CE = LOW and WE = LOW. All signals must be in valid states to initiate a Write, but any can be deasserted to terminate the Write. The Data Input Setup and Hold timing is referenced to the rising or falling edge of the signal that terminates the Write. 10 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. D 04/28/08 IS61LV2568L ORDERING INFORMATION Commercial Range: 0°C to +70°C Speed (ns) Order Part No. Package 8 IS61LV2568L-8K IS61LV2568L-8T IS61LV2568L-8TL 400-mil SOJ TSOP (Type II) TSOP (Type II), Lead-free 10 IS61LV2568L-10T IS61LV2568L-10TL TSOP (Type II) TSOP (Type II), Lead-free Industrial Range: –40°C to +85°C Speed (ns) 10 Order Part No. Package IS61LV2568L-10KI IS61LV2568L-10KLI 400-mil SOJ 400-mil SOJ, Lead-free Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. D 04/28/08 11 PACKAGING INFORMATION 400-mil Plastic SOJ Package Code: K N Notes: 1. Controlling dimension: millimeters. 2. BSC = Basic lead spacing between centers. 3. Dimensions D and E1 do not include mold flash protrusions and should be measured from the bottom of the package. 4. Reference document: JEDEC MS-027. N/2+1 E1 1 E N/2 SEATING PLANE D b A C A2 e Symbol No. Leads A A1 A2 B b C D E E1 E2 e B Millimeters Inches Min Max Min Max (N) 28 3.25 3.75 0.128 0.148 0.64 — 0.025 — 2.08 — 0.082 — 0.38 0.51 0.015 0.020 0.66 0.81 0.026 0.032 0.18 0.33 0.007 0.013 18.29 18.54 0.720 0.730 11.05 11.30 0.435 0.445 10.03 10.29 0.395 0.405 9.40 BSC 0.370 BSC 1.27 BSC 0.050 BSC A1 E2 Millimeters Min Max Inches Min Max Millimeters Min Max 32 3.25 3.75 0.64 — 2.08 — 0.38 0.51 0.66 0.81 0.18 0.33 20.82 21.08 11.05 11.30 10.03 10.29 9.40 BSC 1.27 BSC 0.128 0.148 0.025 — 0.082 — 0.015 0.020 0.026 0.032 0.007 0.013 0.820 0.830 0.435 0.445 0.395 0.405 0.370 BSC 0.050 BSC 3.25 3.75 0.64 — 2.08 — 0.38 0.51 0.66 0.81 0.18 0.33 23.37 23.62 11.05 11.30 10.03 10.29 9.40 BSC 1.27 BSC Inches Min Max 36 0.128 0.148 0.025 — 0.082 — 0.015 0.020 0.026 0.032 0.007 0.013 0.920 0.930 0.435 0.445 0.395 0.405 0.370 BSC 0.050 BSC Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. F 10/29/03 PACKAGING INFORMATION Millimeters Inches Symbol Min Max Min Max No. Leads (N) 40 A 3.25 3.75 0.128 0.148 A1 0.64 — 0.025 — A2 2.08 — 0.082 — B 0.38 0.51 0.015 0.020 b 0.66 0.81 0.026 0.032 C 0.18 0.33 0.007 0.013 D 25.91 26.16 1.020 1.030 E 11.05 11.30 0.435 0.445 E1 10.03 10.29 0.395 0.405 E2 9.40 BSC 0.370 BSC e 1.27 BSC 0.050 BSC Millimeters Min Max Inches Min Max Millimeters Min Max 42 3.25 3.75 0.64 — 2.08 — 0.38 0.51 0.66 0.81 0.18 0.33 27.18 27.43 11.05 11.30 10.03 10.29 9.40 BSC 1.27 BSC 0.128 0.148 0.025 — 0.082 — 0.015 0.020 0.026 0.032 0.007 0.013 1.070 1.080 0.435 0.445 0.395 0.405 0.370 BSC 0.050 BSC 3.25 3.75 0.64 — 2.08 — 0.38 0.51 0.66 0.81 0.18 0.33 28.45 28.70 11.05 11.30 10.03 10.29 9.40 BSC 1.27 BSC Inches Min Max 44 0.128 0.148 0.025 — 0.082 — 0.015 0.020 0.026 0.032 0.007 0.013 1.120 1.130 0.435 0.445 0.395 0.405 0.370 BSC 0.050 BSC Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. 2 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. F 10/29/03 PACKAGING INFORMATION Plastic TSOP Package Code: T (Type II) N N/2+1 E1 1 Notes: 1. Controlling dimension: millimieters, unless otherwise specified. 2. BSC = Basic lead spacing between centers. 3. Dimensions D and E1 do not include mold flash protrusions and should be measured from the bottom of the package. 4. Formed leads shall be planar with respect to one another within 0.004 inches at the seating plane. E N/2 D SEATING PLANE A ZD . b e Symbol Ref. Std. No. Leads A A1 b C D E1 E e L ZD α Millimeters Min Max Inches Min Max (N) 32 — 1.20 — 0.047 0.05 0.15 0.002 0.006 0.30 0.52 0.012 0.020 0.12 0.21 0.005 0.008 20.82 21.08 0.820 0.830 10.03 10.29 0.391 0.400 11.56 11.96 0.451 0.466 1.27 BSC 0.050 BSC 0.40 0.60 0.016 0.024 0.95 REF 0.037 REF 0° 5° 0° 5° L α A1 Plastic TSOP (T - Type II) Millimeters Inches Min Max Min Max 44 — 1.20 — 0.047 0.05 0.15 0.002 0.006 0.30 0.45 0.012 0.018 0.12 0.21 0.005 0.008 18.31 18.52 0.721 0.729 10.03 10.29 0.395 0.405 11.56 11.96 0.455 0.471 0.80 BSC 0.032 BSC 0.41 0.60 0.016 0.024 0.81 REF 0.032 REF 0° 5° 0° 5° Millimeters Min Max C Inches Min Max 50 — 1.20 0.05 0.15 0.30 0.45 0.12 0.21 20.82 21.08 10.03 10.29 11.56 11.96 0.80 BSC 0.40 0.60 0.88 REF 0° 5° — 0.047 0.002 0.006 0.012 0.018 0.005 0.008 0.820 0.830 0.395 0.405 0.455 0.471 0.031 BSC 0.016 0.024 0.035 REF 0° 5° Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. F 06/18/03