IS61LV256AL-10TLI

IS61LV256AL 32K x 8 LOW VOLTAGE CMOS STATIC RAM FEATURES • High-speed access times: — 10 ns • Automatic power-down when chip is deselected • CMOS low power operation — 60 µW (typical) CMOS standby — 65 mW (typical) operating • TTL compatible interface levels • Single 3.3V power supply • Fully static operation: no clock or refresh required • Three-state outputs • Lead-free available ISSI MARCH 2006 ® DESCRIPTION The ISSI IS61LV256AL is a very high-speed, low power, 32,768-word by 8-bit static RAM. It is fabricated using ISSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields access times as fast as 8 ns maximum. When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation is reduced to 150 µW (typical) with CMOS input levels. Easy memory expansion is provided by using an active LOW Chip Enable (CE). The active LOW Write Enable (WE) controls both writing and reading of the memory. The IS61LV256AL is available in the JEDEC standard 28pin, 300-mil SOJ and the 450-mil TSOP (Type I) packages. FUNCTIONAL BLOCK DIAGRAM A0-A14 DECODER 32K X 8 MEMORY ARRAY VDD GND I/O DATA CIRCUIT I/O0-I/O7 COLUMN I/O CE OE WE CONTROL CIRCUIT Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. A 03/17/06 1 IS61LV256AL PIN CONFIGURATION 28-Pin SOJ A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VDD WE A13 A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 ISSI PIN CONFIGURATION 28-Pin TSOP (Type I) OE A11 A9 A8 A13 WE VDD A14 A12 A7 A6 A5 A4 A3 22 23 24 25 26 27 28 1 2 3 4 5 6 7 21 20 19 18 17 16 15 14 13 12 11 10 9 8 ® A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 PIN DESCRIPTIONS A0-A14 CE OE WE I/O0-I/O7 VDD GND Address Inputs Chip Enable Input Output Enable Input Write Enable Input Input/Output Power Ground TRUTH TABLE Mode Not Selected (Power-down) Output Disabled Read Write WE X H H L CE H L L L OE X H L X I/O Operation High-Z High-Z DOUT DIN VDD Current ISB1, ISB2 ICC ICC ICC ABSOLUTE MAXIMUM RATINGS(1) Symbol VDD VTERM TSTG PD IOUT Parameter Power Supply Voltage Relative to GND Terminal Voltage with Respect to GND Storage Temperature Power Dissipation DC Output Current Value –0.5 to +4.6 –0.5 to +4.6 –65 to +150 1 ±20 Unit V V °C W mA Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. A 03/17/06 IS61LV256AL ISSI Ambient Temperature 0°C to +70°C –40°C to +85°C Speed (ns) 10 10 VDD(1) 3.3V, +10%, –5% 3.3V + 10%, –5% ® OPERATING RANGE Range Commercial Industrial Note: 1. If operated at 12ns, VDD range is 3.3V + 10%. DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Symbol Parameter VOH VOL VIH VIL ILI ILO Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage(1) Input Leakage Output Leakage GND ≤ VIN ≤ VDD GND ≤ VOUT ≤ VDD, Outputs Disabled Com. Ind. Com. Ind. Test Conditions VDD = Min., IOH = –2.0 mA VDD = Min., IOL = 4.0 mA Min. 2.4 — 2.2 –0.3 –1 –2 –1 –2 Max. — 0.4 VDD + 0.3 0.8 1 2 1 2 Unit V V V V µA µA Notes: 1. VIL (min.) = –0.3V (DC); VIL (min.) = –2.0V (pulse width ≤ 2.0 ns). VIH (max.) = VDD + 0.5V (DC); VIH (max.) = VDD + 2.0V (pulse width ≤ 2.0 ns). 2. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds. Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. A 03/17/06 3 IS61LV256AL ISSI -10 ns Test Conditions VDD = Max., CE = VIL IOUT = 0 mA, f = 1 MHz VDD = Max., CE = VIL IOUT = 0 mA, f = fMAX VDD = Max., VIN = VIH or VIL CE ≥ VIH, f = 0 VDD = Max., CE ≤ VDD – 0.2V, VIN ≥ VDD – 0.2V, or VIN ≤ 0.2V, f = 0 Com. Ind. Com. Ind. typ.(2) Com. Ind. Com. Ind. typ.(2) Min. Max. Unit ® POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) Sym. ICC1 ICC2 Parameter VDD Operating Supply Current VDD Dynamic Operating Supply Current TTL Standby Current (TTL Inputs) CMOS Standby Current (CMOS Inputs) — — — — 20 — — — — 2 20 25 30 35 1 1 40 50 mA mA ISB1 mA ISB2 µA Notes: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. Typical values are measured at VDD = 3.3V, TA = 25oC and not 100% tested. CAPACITANCE(1,2) Symbol CIN COUT Parameter Input Capacitance Output Capacitance Conditions VIN = 0V VOUT = 0V Max. 6 5 Unit pF pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25°C, f = 1 MHz, VDD = 3.3V. 4 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. A 03/17/06 IS61LV256AL READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) -10 ns Symbol Parameter Read Cycle Time Address Access Time Output Hold Time CE Access Time OE Access Time (2) (2) ISSI -12 ns Min. Max. Unit Min. Max. ® tRC tAA tOHA tACE tDOE tLZOE tHZOE tHZCE tPU tPD (3) (3) 10 — 2 — — 0 — 3 — 0 — — 10 — 10 5 — 5 — 5 — 10 12 — 2 — — 0 — 3 — 0 — — 12 — 12 5 — 5 — 6 — 12 ns ns ns ns ns ns ns ns ns ns ns OE to Low-Z Output OE to High-Z Output CE to Low-Z Output CE to High-Z Output CE to Power-Up CE to Power-Down tLZCE(2) (2) Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±200 mV from steady-state voltage. Not 100% tested. 3. Not 100% tested. AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Levels Output Load Unit 0V to 3.0V 3 ns 1.5V See Figures 1 and 2 AC TEST LOADS 319 Ω 3.3V 3.3V 319 Ω OUTPUT 30 pF Including jig and scope 353 Ω OUTPUT 5 pF Including jig and scope 353 Ω Figure 1. Figure 2. 5 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. A 03/17/06 IS61LV256AL AC WAVEFORMS READ CYCLE NO. 1(1,2) t RC ADDRESS ISSI ® t AA t OHA DOUT PREVIOUS DATA VALID t OHA DATA VALID READ1.eps READ CYCLE NO. 2(1,3) t RC ADDRESS t AA OE t OHA t HZOE t DOE CE t LZOE t LZCE t ACE DATA VALID CE_RD2.eps t HZCE DOUT HIGH-Z Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE = VIL. 3. Address is valid prior to or coincident with CE LOW transitions. 6 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. A 03/17/06 IS61LV256AL WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range) -10 ns Symbol Parameter Write Cycle Time CE to Write End Address Setup Time to Write End Address Hold from Write End Address Setup Time WE Pulse Width (OE HIGH) WE Pulse Width (OE LOW) Data Setup to Write End Data Hold from Write End WE LOW to High-Z Output WE HIGH to Low-Z Output (3) ISSI -12 ns Min. Max. Unit Min. Max. ® tWC tSCE tAW tHA tSA tPWE1 tPWE2 tSD tHD tHZWE(3) tLZWE 10 8 8 0 0 7 10 6.5 0 — 0 — — — — — — — — — 3.5 — 12 8 8 0 0 8 12 7 0 — 0 — — — — — — — — — 5 — ns ns ns ns ns ns ns ns ns ns ns Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1. 2. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. 3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. AC WAVEFORMS WRITE CYCLE NO. 1 (CE Controlled, OE is HIGH or LOW) (1 ) t WC ADDRESS VALID ADDRESS t SA CE t SCE t AW t PWE1 t PWE2 t HZWE t HA WE t LZWE HIGH-Z DOUT DATA UNDEFINED t SD DIN t HD DATAIN VALID CE_WR1.eps Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. A 03/17/06 7 IS61LV256AL WRITE CYCLE NO. 2 (WE Controlled, OE is HIGH During Write Cycle) (1,2) t WC ADDRESS VALID ADDRESS ISSI t HA ® OE CE LOW t AW WE t PWE1 t LZWE HIGH-Z t SA DOUT DATA UNDEFINED t HZWE t SD DIN t HD DATAIN VALID CE_WR2.eps WRITE CYCLE NO. 3 (WE Controlled, OE is LOW During Write Cycle) (1) t WC ADDRESS OE CE VALID ADDRESS LOW t HA LOW t AW WE t PWE2 t LZWE HIGH-Z t SA DOUT DATA UNDEFINED t HZWE t SD DIN t HD DATAIN VALID CE_WR3.eps Notes: 1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. 2. I/O will assume the High-Z state if OE > VIH. 8 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. A 03/17/06 IS61LV256AL DATA RETENTION SWITCHING CHARACTERISTICS Symbol Parameter VDD for Data Retention Data Retention Current Data Retention Setup Time Recovery Time Test Condition See Data Retention Waveform VDD = 2.0V, CE ≥ VDD – 0.2V VIN ≥ VDD – 0.2V, or VIN ≤ VSS + 0.2V See Data Retention Waveform See Data Retention Waveform Com. Ind. Min. 2.0 — — 0 2 — Typ.(1) ISSI Max. 3.6 40 50 — — Unit V µA ns ns ® VDR IDR tSDR tRDR Note: tRC 1. Typical Values are measured at VDD = 3.3V, TA = 25oC and not 100% tested. DATA RETENTION WAVEFORM (CE Controlled) tSDR VDD Data Retention Mode tRDR VDR CE ≥ VDD - 0.2V CE GND Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. A 03/17/06 9 IS61LV256AL ISSI Package TSOP - Type I TSOP - Type I, Lead-free 300-mil Plastic SOJ 300-mil Plastic SOJ, Lead-free ® ORDERING INFORMATION Commercial Range: 0°C to +70°C Speed (ns) 10 Order Part No. IS61LV256AL-10T IS61LV256AL-10TL IS61LV256AL-10J IS61LV256AL-10JL ORDERING INFORMATION Industrial Range: –40°C to +85°C Speed (ns) 10 Order Part No. IS61LV256AL-10TI IS61LV256AL-10TLI IS61LV256AL-10JI IS61LV256AL-10JLI Package TSOP - Type I TSOP - Type I, Lead-free 300-mil Plastic SOJ 300-mil Plastic SOJ, Lead-free 10 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. A 03/17/06 PACKAGING INFORMATION 300-mil Plastic SOJ Package Code: J N ISSI ® E1 E 1 D A SEATING PLANE B A2 C e b A1 E2 MILLIMETERS Sym. N0. Leads A A1 A2 b B C D E E1 E2 e — 0.64 2.41 0.41 0.66 0.20 17.02 8.26 7.49 6.27 INCHES Min. Typ. Max. Min. Typ. Max. 24/26 — — — — — — — — — — 3.56 — 2.67 0.51 0.81 0.25 17.27 8.76 7.75 7.29 Notes: 1. Controlling dimension: inches, unless otherwise specified. 2. BSC = Basic lead spacing between centers. 3. Dimensions D and E1 do not include mold flash protrusions and should be measured from the bottom of the package. 4. Formed leads shall be planar with respect to one another within 0.004 inches at the seating plane. — 0.025 0.095 0.016 0.026 0.008 0.670 0.325 0.295 0.247 — 0.140 — — — — — — — — — — 0.105 0.020 0.032 0.010 0.680 0.345 0.305 0.287 1.27 BSC 0.050 BSC Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. D 02/25/03 PACKAGING INFORMATION 300-mil Plastic SOJ Package Code: J ISSI ® MILLIMETERS Sym. N0. Leads A A1 A2 b B C D E E1 E2 e — 0.64 2.41 0.41 0.66 0.20 18.29 8.26 7.49 6.27 INCHES Min. Typ. Max. Sym. N0. Leads MILLIMETERS Min. Typ. Max. 32 — 0.64 2.41 0.41 0.66 0.20 20.83 8.26 7.49 6.27 — — — — — — — — — — 3.56 — 2.67 0.51 0.81 0.25 21.08 8.76 7.75 7.29 — INCHES Min. Typ. Max. Min. Typ. Max. 28 — — — — — — — — — — 3.56 — 2.67 0.51 0.81 0.25 18.54 8.76 7.75 7.29 — 0.025 0.095 0.016 0.026 0.008 0.720 0.325 0.295 0.247 — — — — — — — — — — 0.140 — 0.105 0.020 0.032 0.010 0.730 0.345 0.305 0.287 A A1 A2 b B C D E E1 E2 e — — — — — — — — — — 0.140 — 0.105 0.020 0.032 0.010 0.830 0.345 0.305 0.287 0.025 0.095 0.016 0.026 0.008 0.820 0.325 0.295 0.247 1.27 BSC 0.050 BSC 1.27 BSC 0.050 BSC 2 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. D 02/25/03 PACKAGING INFORMATION Plastic TSOP - 28-pins Package Code: T (Type I) 1 ISSI ® E H N D SEATING PLANE S A e B L A1 α C Symbol Ref. Std. No. Leads A A1 B C D E H e L α Plastic TSOP (T—Type I) Millimeters Inches Min Max Min Max 28 1.00 1.20 0.05 0.20 0.16 0.27 0.10 0.20 7.90 8.10 11.70 11.90 13.20 13.60 0.55 BSC 0.30 0.70 0° 5° 0.037 0.047 0.002 0.008 0.006 0.011 0.004 0.008 0.308 0.316 0.456 0.465 0.515 0.531 0.022 BSC 0.011 0.027 0° 5° Notes: 1. Controlling dimension: millimeters, unless otherwise specified. 2. BSC = Basic lead spacing between centers. 3. Dimensions D and E do not include mold flash protrusions and should be measured from the bottom of the package. 4. Formed leads shall be planar with respect to one another within 0.004 inches at the seating plane. Integrated Silicon Solution, Inc. PK13197T28 Rev. B 01/31/97