IS61NLF51218B-7.5TQLI-TR

IS61NLF25636B/IS61NVF/NVVF25636B IS61NLF51218B/IS61NVF/NVVF51218B  MAY 2016 256K x 36 and 512K x 18 9Mb, FLOW THROUGH 'NO WAIT' STATE BUS SRAM FEATURES DESCRIPTION • 100 percent bus utilization The 9 Meg product family features high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, 'no wait' state, device for networking and communications applications. They are organized as 256K words by 36 bits and 512K words by 18 bits, fabricated with ISSI's advanced CMOS technology. • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single Read/Write control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control using MODE input • Three chip enables for simple depth expansion and address pipelining • Power Down mode • Common data inputs and data outputs • CKE pin to enable clock and suspend operation • JEDEC 100-pin QFP, 119-ball BGA, and 165ball BGA packages • Power supply: NLF: Vdd 3.3V (± 5%), Vddq 3.3V/2.5V (± 5%) NVF: Vdd 2.5V (± 5%), Vddq 2.5V (± 5%) NVVF: Vdd 1.8V (± 5%), Vddq 1.8V (± 5%) • JTAG Boundary Scan for BGA packages • Industrial temperature available • Lead-free available Incorporating a 'no wait' state feature, wait cycles are eliminated when the bus switches from read to write, or write to read. This device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers are controlled by a positive-edge-triggered single clock input. Operations may be suspended and all synchronous inputs ignored when Clock Enable, CKE is HIGH. In this state the internal device will hold their previous values. All Read, Write and Deselect cycles are initiated by the ADV input. When the ADV is HIGH the internal burst counter is incremented. New external addresses can be loaded when ADV is LOW. Write cycles are internally self-timed and are initiated by the rising edge of the clock inputs and when WE is LOW. Separate byte enables allow individual bytes to be written. A burst mode pin (MODE) defines the order of the burst sequence. When tied HIGH, the interleaved burst sequence is selected. When tied LOW, the linear burst sequence is selected. FAST ACCESS TIME Symbol Parameter tkq Clock Access Time tkc Cycle Time Frequency 6.5 6.5 7.5 133 7.5 7.5 8.5 117 Units ns ns MHz Copyright © 2016 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 1 Rev. A1 05/23/2016 IS61NLF25636B/IS61NVF/NVVF25636B IS61NLF51218B/IS61NVF/NVVF51218B  BLOCK DIAGRAM A0-17 ( A0-18) A0-17 ( A0-18) A2-17(A2-A18) A0-17(A0-18) Address Registers MODE ADV A0-A1 A'0-A'1 K K Address Registers CLK 256Kx36; 512Kx18 Memory Array Burst Logic Address Registers /CKE Data-In Register K /CE Control register CE2 /CE2 ADV /WE /BWx (X=a,b,c,d or a,b) Data-In Register Control Logic K /OE Output Buffers ZZ 36(18) K DQx/DQPx 2 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A1 05/23/2016 IS61NLF25636B/IS61NVF/NVVF25636B IS61NLF51218B/IS61NVF/NVVF51218B  Bottom View 165-Ball, 13 mm x 15mm BGA Bottom View 119-Ball, 14 mm x 22 mm BGA Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 3 Rev. A1 05/23/2016 IS61NLF25636B/IS61NVF/NVVF25636B IS61NLF51218B/IS61NVF/NVVF51218B  Pin Configuration — ­ 256K x 36, 165-Ball BGA (Top View) 1 2 3 4 5 6 7 8 9 10 11 A B C D E F G H J K L M NC NC DQPc DQc DQc DQc DQc NC DQd DQd DQd DQd A A NC DQc DQc DQc DQc NC DQd DQd DQd DQd CE CE2 Vddq Vddq Vddq Vddq Vddq NC Vddq Vddq Vddq Vddq BWc BWd VSS Vdd Vdd Vdd Vdd Vdd Vdd Vdd Vdd BWb BWa VSS VSS VSS VSS VSS VSS VSS VSS VSS CE2 CLK VSS VSS VSS VSS VSS VSS VSS VSS VSS CKE WE VSS VSS VSS VSS VSS VSS VSS VSS VSS ADV OE VSS Vdd Vdd Vdd Vdd Vdd Vdd Vdd Vdd A NC Vddq Vddq Vddq Vddq Vddq NC Vddq Vddq Vddq A A NC DQb DQb DQb DQb NC DQa DQa DQa NC NC DQPb DQb DQb DQb DQb ZZ DQa DQa DQa N P R DQPd NC MODE NC NC NC Vddq A A Vdd VSS A A VSS NC TDI TMS VSS NC A1* A0* VSS NC TDO TCK Vdd VSS A A Vddq Vddq A A DQa NC A A DQa DQPa NC A Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired. PIN DESCRIPTIONS Symbol A A0, A1 ADV Pin Name Address Inputs Synchronous Burst Address Inputs Synchronous Burst Address Advance/ Load WE Synchronous Read/Write Control Input CLK Synchronous Clock CKE Clock Enable CE, CE2, CE2 Synchronous Chip Enable BWx (x=a-d) Synchronous Byte Write Inputs OE Output Enable ZZ Power Sleep Mode 4 MODE TCK, TDI TDO, TMS VDD NC DQx DQPx VDDQ Vss Burst Sequence Selection JTAG Pins Power Supply No Connect Data Inputs/Outputs Parity Data I/O I/O Power Supply Ground Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A1 05/23/2016 IS61NLF25636B/IS61NVF/NVVF25636B IS61NLF51218B/IS61NVF/NVVF51218B  119-PIN BGA PACKAGE CONFIGURATION 256K x 36 (TOP VIEW) 1 2 3 4 5 6 7 A VDDQ A A NC A A VDDQ B NC CE2 A ADV A CE2 NC C NC A A VDD A A NC D DQc DQPc VSS NC Vss DQPb DQb E DQc DQc VSS CE Vss DQb DQb F VDDQ DQc VSS OE Vss DQb VDDQ G DQc DQc BWc A BWb DQb DQb H DQc DQc VSS WE Vss DQb DQb J VDDQ VDD NC VDD NC VDD VDDQ K DQd DQd VSS CLK Vss DQa DQa L DQd DQd BWd NC BWa DQa DQa M VDDQ DQd VSS CKE Vss DQa VDDQ N DQd DQd VSS A 1* Vss DQa DQa P DQd DQPd VSS A0* Vss DQPa DQa R NC A MODE VDD NC A NC T NC NC A A A NC ZZ U VDDQ TMS TDI TCK TDO NC VDDQ Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired. PIN DESCRIPTIONS Symbol A A0, A1 ADV WE CLK CKE CE CE2 CE2 BWx (x=a-d) Pin Name Address Inputs Synchronous Burst Address Inputs Synchronous Burst Address Advance/ Load Synchronous Read/Write Control Input Synchronous Clock Clock Enable Synchronous Chip Select Synchronous Chip Select Synchronous Chip Select Synchronous Byte Write Inputs OE Output Enable ZZ Power Sleep Mode MODE Burst Sequence Selection TCK, TDO JTAG Pins TMS, TDI Vdd Power Supply Vss Ground NC No Connect DQa-DQd Data Inputs/Outputs DQPa-Pd Parity Data I/O Vddq I/O Power Supply Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 5 Rev. A1 05/23/2016 IS61NLF25636B/IS61NVF/NVVF25636B IS61NLF51218B/IS61NVF/NVVF51218B  165-PIN BGA PACKAGE CONFIGURATION 512K x 18 (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 A NC A BWb NC CE2 CKE ADV B NC A CE CE2 A NC A A C NC NC VDDQ NC Vss BWa Vss CLK Vss WE Vss D NC DQb VDDQ VDD Vss Vss Vss OE Vss VDD A VDDQ NC NC DQPa VDDQ NC DQa E NC DQb VDDQ VDD Vss Vss Vss VDD VDDQ NC DQa F NC DQb VDDQ VDD Vss Vss Vss VDD VDDQ NC DQa G NC DQb VDDQ Vss H NC NC NC VDD VDD Vss Vss Vss Vss VDD VDD VDDQ NC DQa J DQb NC VDDQ VDD Vss Vss NC NC ZZ Vss Vss VDD VDDQ DQa NC K DQb NC VDDQ VDD Vss Vss Vss VDD VDDQ DQa VDD Vss Vss VDD VDDQ DQa VDDQ VDD Vss Vss Vss NC NC L DQb NC VDDQ M DQb NC Vss VDD VDDQ DQa NC N DQPb NC Vss A NC TDI NC NC Vss NC TDO A A NC NC A A TMS A1* A0* VDDQ A NC NC VDDQ A P NC R MODE TCK A A A A Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired. PIN DESCRIPTIONS Symbol A A0, A1 ADV Pin Name Address Inputs Synchronous Burst Address Inputs Synchronous Burst Address Advance/ Load WE Synchronous Read/Write Control Input CLK Synchronous Clock CKE Clock Enable CE, CE2, CE2 Synchronous Chip Enable BWx (x=a,b) Synchronous Byte Write Inputs OE Output Enable ZZ Power Sleep Mode 6 MODE TCK, TDI TDO, TMS VDD NC DQx DQPx VDDQ Vss Burst Sequence Selection JTAG Pins Power Supply No Connect Data Inputs/Outputs Parity Data I/O I/O Power Supply Ground Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A1 05/23/2016 IS61NLF25636B/IS61NVF/NVVF25636B IS61NLF51218B/IS61NVF/NVVF51218B  119-PIN BGA PACKAGE CONFIGURATION 512K x 18 (TOP VIEW) 1 2 3 4 5 6 7 A VDDQ A A NC A A VDDQ B NC CE2 A ADV A CE2 NC C NC A A VDD A A NC D DQb NC VSS NC Vss DQPa NC E DQb VSS CE Vss NC DQa F NC VDDQ NC VSS OE Vss DQa VDDQ G NC DQb BWb A NC NC DQa H DQb NC WE Vss DQa NC J VDDQ VDD VSS NC VDD NC VDD VDDQ K NC DQb VSS CLK Vss NC DQa L DQb NC NC NC BWa DQa NC M VDDQ DQb VSS CKE Vss NC VDDQ N DQb NC VSS A 1* Vss DQa NC P NC DQPb VSS A0* Vss NC DQa R NC A MODE VDD NC A NC T NC A A NC A A ZZ U VDDQ TMS TDI TCK TDO NC VDDQ Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired. PIN DESCRIPTIONS Symbol A A0, A1 ADV WE CLK CKE CE CE2 CE2 BWx (x=a,b) Pin Name Address Inputs Synchronous Burst Address Inputs Synchronous Burst Address Advance/ Load Synchronous Read/Write Control Input Synchronous Clock Clock Enable Synchronous Chip Select Synchronous Chip Select Synchronous Chip Select Synchronous Byte Write Inputs OE Output Enable ZZ Power Sleep Mode MODE Burst Sequence Selection TCK, TDO JTAG Pins TMS, TDI Vdd Power Supply Vss Ground NC No Connect DQa-DQb Data Inputs/Outputs DQPa-Pb Parity Data I/O Vddq I/O Power Supply Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A1 05/23/2016 7 IS61NLF25636B/IS61NVF/NVVF25636B IS61NLF51218B/IS61NVF/NVVF51218B  PIN CONFIGURATION DQa DQb DQa DQb VDDQ VDDQ Vss NC Vss DQa Vss DQb DQa DQb DQa DQa Vss DQPb NC VDDQ VDDQ DQa DQa DQPa NC NC NC Vss A ADV NC OE CKE CLK WE CE2 VDD Vss BWa NC BWb NC CE2 CE A A A NC NC VDDQ Vss NC DQPa DQa DQa Vss VDDQ DQa DQa Vss NC VDD ZZ DQa DQa VDDQ Vss DQa DQa NC NC Vss VDDQ NC NC NC A A DQb NC VDD A DQb Vss NC VDD ZZ A DQb A VDDQ DQb A VDDQ NC A Vss NC DQb VDD Vss DQb Vss DQb NC NC NC NC DQb Vss A1 A0 MODE DQd DQd DQPd DQb DQb VDDQ A VDDQ Vss NC A DQd DQd Vss VDDQ NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 10 71 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 A DQd DQb NC A Vss DQd DQb MODE VDDQ DQPb A A DQd A DQd A NC Vss A DQc NC VDD A DQc NC A VDDQ NC Vss Vss DQc VDD DQc NC NC DQc DQc A1 A0 Vss A VDDQ A DQc A DQc 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 10 71 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 A DQPc A A A A A OE ADV NC CKE CLK WE CE2 VDD Vss BWa BWc BWb BWd CE2 CE A A 100-Pin QFP 512K x 18 256K x 36 PIN DESCRIPTIONS A0, A1 A CLK ADV BWa-BWd WE CKE Vss NC 8 Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus. Synchronous Address Inputs Synchronous Clock Synchronous Burst Address Advance Synchronous Byte Write Enable Write Enable Clock Enable Ground for Core Not Connected CE, CE2, CE2 OE DQa-DQd DQPa-DQPd MODE Vdd Vss Vddq ZZ Synchronous Chip Enable Output Enable Synchronous Data Input/Output Parity Data I/O Burst Sequence Selection Power Supply Ground for output Buffer I/O Power Supply Snooze Enable Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A1 05/23/2016 IS61NLF25636B/IS61NVF/NVVF25636B IS61NLF51218B/IS61NVF/NVVF51218B  STATE DIAGRAM READ READ READ BURST WRITE BEGIN READ DS DS READ WRITE DESELECT BURST BURST READ BEGIN WRITE BURST DS BURST DS DS WRITE READ BURST WRITE WRITE WRITE BURST SYNCHRONOUS TRUTH TABLE(1) Address Operation Used CE CE2 CE2 Not Selected N/A H X X Not Selected N/A X L X Not Selected N/A X X H Not Selected Continue N/A X X X Begin Burst Read External Address L H L Continue Burst Read Next Address X X X NOP/Dummy Read External Address L H L Dummy Read Next Address X X X Begin Burst Write External Address L H L Continue Burst Write Next Address X X X NOP/Write Abort N/A L H L Write Abort Next Address X X X Ignore Clock Current Address X X X Notes: ADV WE L X L X L X H X L H H X L H H X L L H X L L H X X X BWx X X X X X X X X L L H H X OE X X X X L L H H X X X X X CKE L L L L L L L L L L L L H CLK ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ 1. "X" means don't care. 2. The rising edge of clock is symbolized by ↑ 3. A continue deselect cycle can only be entered if a deselect cycle is executed first. 4. WE = L means Write operation in Write Truth Table. WE = H means Read operation in Write Truth Table. 5. Operation finally depends on status of asynchronous pins (ZZ and OE). Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A1 05/23/2016 9 IS61NLF25636B/IS61NVF/NVVF25636B IS61NLF51218B/IS61NVF/NVVF51218B  ASYNCHRONOUS TRUTH TABLE(1) Operation ZZ OE Sleep Mode H X Read L L L H Write L X Deselected L X Notes: I/O STATUS High-Z DQ High-Z Din, High-Z High-Z 1. X means "Don't Care". 2. For write cycles following read cycles, the output buffers must be disabled with OE, otherwise data bus contention will occur. 3. Sleep Mode means power Sleep Mode where stand-by current does not depend on cycle time. 4. Deselected means power Sleep Mode where stand-by current depends on cycle time. WRITE TRUTH TABLE (x18) Operation READ WRITE BYTE a WRITE BYTE b WRITE ALL BYTEs WRITE ABORT/NOP Notes: WE BWa BWb H X X L L H L H L L L L L H H 1. X means "Don't Care". 2. All inputs in this table must beet setup and hold time around the rising edge of CLK. 10 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A1 05/23/2016 IS61NLF25636B/IS61NVF/NVVF25636B IS61NLF51218B/IS61NVF/NVVF51218B  WRITE TRUTH TABLE (x36) Operation READ WRITE BYTE a WRITE BYTE b WRITE BYTE c WRITE BYTE d WRITE ALL BYTEs WRITE ABORT/NOP Notes: WE BWa BWb BWc BWd H X X X X L L H H H L H L H H L H H L H L H H H L L L L L L L H H H H 1. X means "Don't Care". 2. All inputs in this table must beet setup and hold time around the rising edge of CLK. Power Up Sequence Vddq → Vdd1 → I/O Pins2 Notes: 1. Vdd can be applied at the same time as Vddq 2. Applying I/O inputs is recommended after Vddq is ready. The inputs of the I/O pins can be applied at the same time as Vddq provided Vih (level of I/O pins) is lower than Vddq. Power-UP INITIALIZATION TIMING VDD power > 1ms VDD VDDQ Device Initialization Device ready for normal operation INTERLEAVED BURST ADDRESS TABLE (MODE = Vdd or NC) External Address 1st Burst Address 2nd Burst Address 3rd Burst Address A1 A0 A1 A0 A1 A0 A1 A0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 11 Rev. A1 05/23/2016 IS61NLF25636B/IS61NVF/NVVF25636B IS61NLF51218B/IS61NVF/NVVF51218B  LINEAR BURST ADDRESS TABLE (MODE = Vss)   0,0 A1', A0' = 1,1 0,1 1,0 ABSOLUTE MAXIMUM RATINGS(1) Symbol Tstg Pd Iout Vin, Vout Vin Parameter Storage Temperature Power Dissipation Output Current (per I/O) Voltage Relative to Vss for I/O Pins Voltage Relative to Vss for for Address and Control Inputs NLF Value –65 to +150 1.6 100 –0.5 to Vddq + 0.3 –0.3 to Vdd + 0.5 NVF/NVVF Value –65 to +150 1.6 100 –0.5 to Vddq + 0.3 –0.3 to Vdd + 0.3 Unit °C W mA V V Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. This device contains circuity to protect the inputs against damage due to high static voltages or electric fields; however, precautions may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. 3. This device contains circuitry that will ensure the output devices are in High-Z at power up. OPERATING RANGE (IS61NLFx) Range Commercial Industrial 12 Ambient Temperature 0°C to +70°C -40°C to +85°C Vdd 3.3V ± 5% 3.3V ± 5% Vddq 3.3V / 2.5V ± 5% 3.3V / 2.5V ± 5% Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A1 05/23/2016 IS61NLF25636B/IS61NVF/NVVF25636B IS61NLF51218B/IS61NVF/NVVF51218B  OPERATING RANGE (IS61NVFx) Range Commercial Industrial Ambient Temperature 0°C to +70°C -40°C to +85°C Vdd 2.5V ± 5% 2.5V ± 5% Vddq 2.5V ± 5% 2.5V ± 5% Vdd 1.8V ± 5% 1.8V ± 5% Vddq 1.8V ± 5% 1.8V ± 5% OPERATING RANGE (IS61NVVFx) Range Commercial Industrial Ambient Temperature 0°C to +70°C -40°C to +85°C DC ELECTRICAL CHARACTERISTICS (Over Operating Range) 1, 2, 3 3.3V 2.5V 1.8V Symbol Parameter Test Conditions Min. Max. Min. Max. Min. Max. Unit Voh Output HIGH Voltage Ioh = –4.0 mA  (3.3V) 2.4 — 2.0 — Vddq - 0.4 — V Ioh = –1.0 mA  (2.5V, 1.8V) Vol Output LOW Voltage Iol = 8.0 mA  (3.3V) — 0.4 — 0.4 — 0.4 V Iol = 1.0 mA  (2.5V, 1.8V) Vih Input HIGH Voltage 2.0 Vdd + 0.3 1.7 Vdd + 0.3 0.6Vdd Vdd + 0.3 V Vil Input LOW Voltage –0.3 0.8 –0.3 0.7 –0.3 0.3Vdd V (1) Ili Input Leakage Current Vss ≤ Vin ≤ Vdd –5 5 –5 5 –5 5 µA Ilo Output Leakage Current Vss ≤ Vout ≤ Vddq, OE = Vih –5 5 –5 5 –5 5 µA Notes: 1. All voltages referenced to ground. 2. Overshoot: 3.3V and 2.5V: Vih (AC) ≤ Vdd + 1.5V (Pulse width less than tkc /2) 1.8V: Vih (AC) ≤ Vdd + 0.5V (Pulse width less than tkc /2) 3. Undershoot: 3.3V and 2.5V: Vil (AC) ≥ -1.5V (Pulse width less than tkc /2) 1.8V: Vil (AC) ≥ -0.5V (Pulse width less than tkc /2) POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter Icc AC Operating Supply Current Isb Standby Current TTL Input Isbi Standby Current CMOS Input Test Conditions Temp. range Device Selected, Com. OE = Vih, ZZ ≤ Vil, Ind. All Inputs ≤ 0.2V or ≥ Vdd – 0.2V, Cycle Time ≥ tkc min. Device Deselected, Com. Vdd = Max., Ind. All Inputs ≤ Vil or ≥ Vih, ZZ ≤ Vil, f = Max. Device Deselected, Com. Vdd = Max., Ind. Vin ≤ Vss + 0.2V or ≥Vdd – 0.2V f = 0 6.5 7.5 MAX MAX x18 x36 x18 x36 120 120 110 110 130 130 120 120 Unit mA 65 70 65 70 65 70 65 70 mA 50 55 50 55 50 55 50 55 mA Note: 1. MODE pin has an internal pullup and should be tied to Vdd or Vss. It exhibits ±100 µA maximum leakage current when tied to ≤ Vss + 0.2V or ≥ Vdd – 0.2V. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 13 Rev. A1 05/23/2016 IS61NLF25636B/IS61NVF/NVVF25636B IS61NLF51218B/IS61NVF/NVVF51218B  CAPACITANCE(1,2) Symbol Cin Cout Parameter Input Capacitance Input/Output Capacitance Conditions Vin = 0V Vout = 0V Max. 6 8 Unit pF pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: Ta = 25°C, f = 1 MHz, Vdd = 3.3V. 3.3V I/O AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0V to 3.0V 1.5 ns 1.5V See Figures 1 and 2 3.3V I/O OUTPUT LOAD EQUIVALENT 317 Ω +3.3V Zo= 50Ω OUTPUT OUTPUT 50Ω 5 pF Including jig and scope 351 Ω 1.5V Figure 1 14 Figure 2 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A1 05/23/2016 IS61NLF25636B/IS61NVF/NVVF25636B IS61NLF51218B/IS61NVF/NVVF51218B  2.5V I/O AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0V to 2.5V 1.5 ns 1.25V See Figures 3 and 4 2.5V I/O OUTPUT LOAD EQUIVALENT 1,667 Ω +2.5V ZO = 50Ω OUTPUT OUTPUT 50Ω 5 pF Including jig and scope 1,538 Ω 1.25V Figure 3 Figure 4 1.8V I/O AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0V to 1.8V 1.5 ns 0.9V See Figures 5 and 6 1.8V I/O OUTPUT LOAD EQUIVALENT 1K Ω +1.8V ZO = 50Ω OUTPUT OUTPUT 50Ω 5 pF Including jig and scope 1K Ω 0.9V Figure 5 Figure 6 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 15 Rev. A1 05/23/2016 IS61NLF25636B/IS61NVF/NVVF25636B IS61NLF51218B/IS61NVF/NVVF51218B  READ/WRITE CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)   Symbol fmax tkc tkh tkl tkq tkqx(2) tkqlz(2,3) tkqhz(2,3) toeq toelz(2,3) toehz(2,3) tas tws tces tse tadvs tds tah the twh tceh tadvh tdh tpower(4) Notes: 6.5 Min. Max. — 133 7.5 — 2.2 — 2.2 — — 6.5 2.5 — 2.5 — — 3.8 — 3.2 0 — Parameter Clock Frequency Cycle Time Clock High Time Clock Low Time Clock Access Time Clock High to Output Invalid Clock High to Output Low-Z Clock High to Output High-Z Output Enable to Output Valid Output Enable to Output Low-Z Output Disable to Output High-Z Address Setup Time Read/Write Setup Time Chip Enable Setup Time Clock Enable Setup Time Address Advance Setup Time Data Setup Time Address Hold Time Clock Enable Hold Time Write Hold Time Chip Enable Hold Time Address Advance Hold Time Data Hold Time Vdd (typical) to First Access — 1.5 1.5 1.5 1.5 1.5 1.5 0.5 0.5 0.5 0.5 0.5 0.5 1 3.5 — — — — — — — — — — — — — 7.5 Min. Max. — 117 8.5 — 2.5 — 2.5 — — 7.5 2.5 — 2.5 — — 4.0 — 3.4 0 — — 3.5 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — 1 — Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms 1.  Configuration signal MODE is static and must not change during normal operation. 2.  Guaranteed but not 100% tested. This parameter is periodically sampled. 3.  Tested with load in Figure 2. 4. tpower is the time that the power needs to be supplied above Vdd (min) initially before READ or WRITE operation can be initiated. 16 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A1 05/23/2016 IS61NLF25636B/IS61NVF/NVVF25636B IS61NLF51218B/IS61NVF/NVVF51218B  SNOOZE MODE ELECTRICAL CHARACTERISTICS Symbol Parameter Conditions Temperature Min. Max. Unit Range Isb2 Current during SNOOZE MODE ZZ ≥ Vih Com. — 15 mA Ind. — 20 tpds ZZ active to input ignored — 2 cycle tpus ZZ inactive to input sampled 2 — cycle tzzi ZZ active to SNOOZE current — 2 cycle trzzi ZZ inactive to exit SNOOZE current 0 — ns SLEEP MODE TIMING CLK tPDS ZZ setup cycle tPUS ZZ recovery cycle ZZ tZZI Isupply ISB2 tRZZI All Inputs (except ZZ) Deselect or Read Only Deselect or Read Only Normal operation cycle Outputs (Q) High-Z Don't Care Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A1 05/23/2016 17 IS61NLF25636B/IS61NVF/NVVF25636B IS61NLF51218B/IS61NVF/NVVF51218B  READ CYCLE TIMING tKH tKL CLK tKC tADVS tADVH ADV tAS tAH Address A1 A3 A2 tWS tWH WRITE tSE tHE CKE tCES tCEH CE OE tOEQ tOEHZ Data Out Q1-1 tOEHZ tDS Q2-1 tKQ Q2-2 tKQHZ Q2-3 NOTES: WRITE = L means WE = L and BWx = L WE = L and BWX = L CE = L means CE1 = L, CE2 = H and CE2 = L CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L 18 Q2-4 Q3-1 Q3-2 Q3-3 Q3-4 Don't Care Undefined Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A1 05/23/2016 IS61NLF25636B/IS61NVF/NVVF25636B IS61NLF51218B/IS61NVF/NVVF51218B  WRITE CYCLE TIMING tKH tKL CLK tKC ADV Address A1 A3 A2 WRITE tSE tHE CKE CE OE tDS Data In D1-1 D2-1 D2-2 D2-3 D2-4 D3-1 tDH D3-2 D3-3 D3-4 tOEHZ Data Out Q0-4 NOTES: WRITE = L means WE = L and BWx = L WE = L and BWX = L CE = L means CE1 = L, CE2 = H and CE2 = L CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A1 05/23/2016 Don't Care Undefined 19 IS61NLF25636B/IS61NVF/NVVF25636B IS61NLF51218B/IS61NVF/NVVF51218B  SINGLE READ/WRITE CYCLE TIMING tKH tKL CLK tSE tHE tKC CKE Address A1 A2 A3 A4 A5 A6 A7 A8 A9 WRITE CE ADV OE tOEQ Data Out tOELZ Q1 Q3 Q4 Q6 Q7 tDS tDH Data In D5 D2 NOTES: WRITE = L means WE = L and BWx = L CE = L means CE1 = L, CE2 = H and CE2 = L CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L 20 Don't Care Undefined Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A1 05/23/2016 IS61NLF25636B/IS61NVF/NVVF25636B IS61NLF51218B/IS61NVF/NVVF51218B  CKE OPERATION TIMING tKH tKL CLK tSE tHE tKC CKE Address A1 A2 A3 A4 A5 A6 WRITE CE ADV OE tKQ Data Out tKQLZ tKQHZ Q1 Q3 Q4 tDS tDH Data In D2 NOTES: WRITE = L means WE = L and BWx = L CE = L means CE1 = L, CE2 = H and CE2 = L CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L D5 Don't Care Undefined Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 21 Rev. A1 05/23/2016 IS61NLF25636B/IS61NVF/NVVF25636B IS61NLF51218B/IS61NVF/NVVF51218B  CE OPERATION TIMING tKH tKL CLK tSE tHE tKC CKE Address A1 A2 A3 A4 A5 WRITE CE ADV OE tOEQ Data Out tOELZ tKQHZ Q1 tKQ tKQLZ Q2 Q4 tDS tDH Data In D3 NOTES: WRITE = L means WE = L and BWx = L CE = L means CE1 = L, CE2 = H and CE2 = L CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L 22 D5 Don't Care Undefined Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A1 05/23/2016 IS61NLF25636B/IS61NVF/NVVF25636B IS61NLF51218B/IS61NVF/NVVF51218B  IEEE 1149.1 Serial Boundary Scan (JTAG) Test Access Port (TAP) - Test Clock The serial boundary scan Test Access Port (TAP) is only available in the BGA package. (Not available in QFP package.) This port operates in accordance with IEEE Standard 1149.1-1900, but does not include all functions required for full 1149.1 compliance. These functions from the IEEE specification are excluded because they place added delay in the critical speed path of the SRAM. The TAP controller operates in a manner that does not conflict with the performance of other devices using 1149.1 fully compliant TAPs. The test clock is only used with the TAP controller. All inputs are captured on the rising edge of TCK and outputs are driven from the falling edge of TCK. Disabling the JTAG Feature The TDI pin is used to serially input information to the registers and can be connected to the input of any register. The register between TDI and TDO is chosen by the instruction loaded into the TAP instruction register. For information on instruction register loading, see the TAP Controller State Diagram. TDI is internally pulled up and can be disconnected if the TAP is unused in an application. TDI is connected to the Most Significant Bit (MSB) on any register. The SRAM can operate without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (Vss) to prevent clocking of the device. TDI and TMS are internally pulled up and may be disconnected. They may alternately be connected to Vdd through a pull-up resistor. TDO should be left disconnected. On power-up, the device will start in a reset state which will not interfere with the device operation. Test Mode Select (TMS) The TMS input is used to send commands to the TAP controller and is sampled on the rising edge of TCK. This pin may be left disconnected if the TAP is not used. The pin is internally pulled up, resulting in a logic HIGH level. Test Data-In (TDI) tap controller block diagram 0 Bypass Register 2 1 0 Instruction Register TDI Selection Circuitry 31 30 29 . . . Selection Circuitry 2 1 0 2 1 0 TDO Identification Register x . . . . . Boundary Scan Register* TCK TMS TAP CONTROLLER Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 23 Rev. A1 05/23/2016 IS61NLF25636B/IS61NVF/NVVF25636B IS61NLF51218B/IS61NVF/NVVF51218B  Test Data Out (TDO) The TDO output pin is used to serially clock data-out from the registers. The output is active depending on the current state of the TAP state machine (see TAP Controller State Diagram). The output changes on the falling edge of TCK and TDO is connected to the Least Significant Bit (LSB) of any register. Performing a TAP Reset A Reset is performed by forcing TMS HIGH (Vdd) for five rising edges of TCK. RESET may be performed while the SRAM is operating and does not affect its operation. At power-up, the TAP is internally reset to ensure that TDO comes up in a high-Z state. TAP Registers Registers are connected between the TDI and TDO pins and allow data to be scanned into and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction registers. Data is serially loaded into the TDI pin on the rising edge of TCK and output on the TDO pin on the falling edge of TCK. Instruction Register Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO pins. (See TAP Controller Block Diagram)  At power-up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as previously described. When the TAP controller is in the CaptureIR state, the two least significant bits are loaded with a binary “01” pattern to allow for fault isolation of the board level serial test path. Bypass Register To save time when serially shifting data through registers, it is sometimes advantageous to skip certain states. The bypass register is a single-bit register that can be placed between TDI and TDO pins. This allows data to be shifted through the SRAM with minimal delay. The bypass reg- ister is set LOW (Vss) when the BYPASS instruction is executed. Boundary Scan Register The boundary scan register is connected to all input and output pins on the SRAM. Several no connect (NC) pins are also included in the scan register to reserve pins for higher density devices. The x36 configuration has a 75-bit-long register and the x18 configuration also has a 75-bit-long register. The boundary scan register is loaded with the contents of the RAM Input and Output ring when the TAP controller is in the Capture-DR state and then placed between the TDI and TDO pins when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD and SAMPLE-Z instructions can be used to capture the contents of the Input and Output ring. The Boundary Scan Order tables show the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI, and the LSB is connected to TDO. Scan Register Sizes Register Bit Size Bit Size Name (x18) (x36) Instruction 3 3 Bypass 1 1 ID 32 32 Boundary Scan 90 90 Identification (ID) Register The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded to the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has vendor code and other information described in the Identification Register Definitions table. Identification Register Definitions Instruction Field Revision Number  (31:28) Device Depth  (27:23) Device Width  (22:18) ISSI Device ID  (17:12) ISSI JEDEC ID  (11:1) ID Register Presence  (0) 24 Description Reserved for version number. Defines depth of SRAM. 256K or 512K Defines Width of the SRAM. x36 or x18 Reserved for future use. Allows unique identification of SRAM vendor. Indicate the presence of an ID register. 256K x 36 xxxx 00111 00100 xxxxx 00001010101 1 512K x 18 xxxx 01000 00011 xxxxx 00001010101 1 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A1 05/23/2016 IS61NLF25636B/IS61NVF/NVVF25636B IS61NLF51218B/IS61NVF/NVVF51218B  TAP Instruction Set SAMPLE/PRELOAD Eight instructions are possible with the three-bit instruction register and all combinations are listed in the Instruction Code table. Three instructions are listed as RESERVED and should not be used and the other five instructions are described below. The TAP controller used in this SRAM is not fully compliant with the 1149.1 convention because some mandatory instructions are not fully implemented. The TAP controller cannot be used to load address, data or control signals and cannot preload the Input or Output buffers. The SRAM does not implement the 1149.1 commands EXTEST or INTEST or the PRELOAD portion of SAMPLE/ PRELOAD; instead it performs a capture of the Inputs and Output ring when these instructions are executed. Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted from the instruction register through the TDI and TDO pins. To execute an instruction once it is shifted in, the TAP controller must be moved into the Update-IR state. SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The PRELOAD portion of this instruction is not implemented, so the TAP controller is not fully 1149.1 compliant. When the SAMPLE/PRELOAD instruction is loaded to the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the inputs and output pins is captured in the boundary scan register. It is important to realize that the TAP controller clock operates at a frequency up to 10 MHz, while the SRAM clock runs more than an order of magnitude faster. Because of the clock frequency differences, it is possible that during the Capture-DR state, an input or output will under-go a transition. The TAP may attempt a signal capture while in transition (metastable state). The device will not be harmed, but there is no guarantee of the value that will be captured or repeatable results. To guarantee that the boundary scan register will capture the correct signal value, the SRAM signal must be stabilized long enough to meet the TAP controller’s capture set-up plus hold times (tcs and tch). To insure that the SRAM clock input is captured correctly, designs need a way to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is not an issue, it is possible to capture all other signals and simply ignore the value of the CLK captured in the boundary scan register. Once the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins. Note that since the PRELOAD part of the command is not implemented, putting the TAP into the Update to the UpdateDR state while performing a SAMPLE/PRELOAD instruction will have the same effect as the Pause-DR command. EXTEST EXTEST is a mandatory 1149.1 instruction which is to be executed whenever the instruction register is loaded with all 0s. Because EXTEST is not implemented in the TAP controller, this device is not 1149.1 standard compliant. The TAP controller recognizes an all-0 instruction. When an EXTEST instruction is loaded into the instruction register, the SRAM responds as if a SAMPLE/PRELOAD instruction has been loaded. There is a difference between the instructions, unlike the SAMPLE/PRELOAD instruction, EXTEST places the SRAM outputs in a High-Z state. IDCODE The IDCODE instruction causes a vendor-specific, 32bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO pins and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction is loaded into the instruction register upon power-up or whenever the TAP controller is given a test logic reset state. SAMPLE-Z The SAMPLE-Z instruction causes the boundary scan register to be connected between the TDI and TDO pins when the TAP controller is in a Shift-DR state. It also places all SRAM outputs into a High-Z state. Bypass When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO pins. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 25 Rev. A1 05/23/2016 IS61NLF25636B/IS61NVF/NVVF25636B IS61NLF51218B/IS61NVF/NVVF51218B  Instruction Codes Code Instruction Description 000 EXTEST Captures the Input/Output ring contents. Places the boundary scan register between the TDI and TDO. Forces all SRAM outputs to High-Z state. This instruction is not 1149.1 compliant. 001 IDCODE Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operation. 010 SAMPLE-Z Captures the Input/Output contents. Places the boundary scan register between TDI and TDO. Forces all SRAM output drivers to a High-Z state. 011 RESERVED Do Not Use: This instruction is reserved for future use. 100 SAMPLE/PRELOAD Captures the Input/Output ring contents. Places the boundary scan register between TDI and TDO. Does not affect the SRAM operation. This instruction does not implement 1149.1 preload function and is therefore not 1149.1 compliant. 101 RESERVED Do Not Use: This instruction is reserved for future use. 110 RESERVED Do Not Use: This instruction is reserved for future use. 111 BYPASS Places the bypass register between TDI and TDO. This operation does not affect SRAM operation. TAP CONTROLLER STATE DIAGRAM Test Logic Reset 1 0 Run Test/Idle 1 Select DR 0 0 1 1 1 Capture DR 0 Shift DR 1 Exit1 DR 0 Select IR 0 1 Exit1 IR 0 Pause DR 0 1 0 1 26 Exit2 DR 1 Update DR 0 Capture IR 0 Shift IR 1 0 Pause IR 1 0 1 1 0 1 0 Exit2 IR 1 Update IR 0 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A1 05/23/2016 IS61NLF25636B/IS61NVF/NVVF25636B IS61NLF51218B/IS61NVF/NVVF51218B  TAP Electrical Characteristics (2.5V and 3.3V Operating Range) Symbol Parameter Test Conditions Min. Max. Voh1 Output HIGH Voltage Ioh = –2.0 mA 1.7 — Voh2 Output HIGH Voltage Ioh = –100 µA 2.1 — Vol1 Output LOW Voltage Iol = 2.0 mA — 0.7 Vol2 Output LOW Voltage Iol = 100 µA — 0.2 Vih Input HIGH Voltage 1.7 Vdd +0.3 Vil Input LOW Voltage –0.3 0.7 Ix Input Leakage Current Vss ≤ V I ≤ Vddq –10 10 TAP Electrical Characteristics (1.8V Operating Range) Symbol Parameter Voh1 Output HIGH Voltage Vol1 Vih Vil Ix Test Conditions Min. Max. Ioh = –2.0 mA Vdd -0.4 — Output LOW Voltage Iol = 2.0 mA -0.3 0.5 Input HIGH Voltage 1.3 Vdd +0.3 Input LOW Voltage –0.3 0.7 Input Leakage Current Vss ≤ V I ≤ Vddq –10 10 Units V V V V V V µA Units V V V V µA TAP AC ELECTRICAL CHARACTERISTICS (Over Operating Range) Parameter Symbol Min Max Units TCK cycle time tTHTH 100 – ns TCK high pulse width tTHTL 40 – ns TCK low pulse width tTLTH 40 – ns TMS Setup tMVTH 10 – ns TMS Hold tTHMX 10 – ns TDI Setup tDVTH 10 – ns TDI Hold tTHDX 10 – ns TCK Low to Valid Data tTLOV – 20 ns Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A1 05/23/2016 27 IS61NLF25636B/IS61NVF/NVVF25636B IS61NLF51218B/IS61NVF/NVVF51218B  TAP AC TEST conditions (1.8V/2.5V/3.3V)Input pulse levels 0 to 1.8V/0 to 2.5V/0 to 3.0V 1.5ns 0.9V/1.25V/1.5V 0.9V/1.25V/1.5V 0.9V/1.25V/1.5V 0.9V/1.25V/1.5V Input rise and fall times Input timing reference levels Output reference levels Test load termination supply voltage Vtrig TAP Output Load Equivalent 50Ω Vtrig TDO 20 pF Z0 = 50Ω GND Tap timing 1 2 tTHTH 3 4 5 6 tTLTH TCK tTHTL tMVTH tTHMX TMS tDVTH tTHDX TDI tTLOV TDO tTLOX DON'T CARE UNDEFINED 28 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A1 05/23/2016 IS61NLF25636B/IS61NVF/NVVF25636B IS61NLF51218B/IS61NVF/NVVF51218B  119 BGA Boundary Scan Order TBD Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A1 05/23/2016 29 IS61NLF25636B/IS61NVF/NVVF25636B IS61NLF51218B/IS61NVF/NVVF51218B  165 bga Boundary Scan Order 165 BGA 165 BGA X36 X18 X36 X18 Bit # Bump ID Signal Bump ID Signal Bit # Bump ID Signal Bump ID Signal 1 N6 NC N6 NC 41 B8 /OE B8 /OE 2 N7 NC N7 NC 42 A7 /CKE A7 /CKE 3 N10 NC N10 NC 43 B7 /WE B7 /WE 4 P11 NC P11 NC 44 B6 CLK B6 CLK 5 P8 A17 P8 A17 45 A6 /CE2 A6 /CE2 6 R8 A16 R8 A16 46 B5 /Bwa B5 /Bwa 7 R9 A15 R9 A15 47 A5 /Bwb A5 NC 8 P9 A14 P9 A14 48 A4 /Bwc A4 /Bwb 9 P10 A13 P10 A13 49 B4 /Bwd B4 NC 10 R10 A12 R10 A12 50 B3 CE2 B3 CE2 11 R11 A11 R11 A11 51 A3 /CE1 A3 /CE1 12 H11 ZZ H11 ZZ 52 A2 A7 A2 A7 13 N11 DQa0 N11 NC 53 B2 A6 B2 A6 14 M11 DQa1 M11 NC 54 C2 NC C2 NC B1 NC B1 NC 15 L11 DQa2 L11 NC 55 16 M10 DQa3 M10 NC 56 A1 NC A1 NC 17 L10 DQa4 L10 NC 57 C1 DQc0 C1 NC 18 K11 DQa5 K11 DQa8 58 D1 DQc1 D1 NC 19 J11 DQa6 J11 DQa7 59 E1 DQc2 E1 NC 20 K10 DQa7 K10 DQa6 60 D2 DQc3 D2 NC 21 J10 DQa8 J10 DQa5 61 E2 DQc4 E2 NC 22 H9 NC H9 NC 62 F1 DQc5 F1 DQb8 23 H10 NC H10 NC 63 G1 DQc6 G1 DQb7 24 G11 DQb8 G11 DQa4 64 F2 DQc7 F2 DQb6 25 F11 DQb7 F11 DQa3 65 G2 DQc8 G2 DQb5 26 G10 DQb6 G10 DQa2 66 H1 NC H1 NC 27 E11 DQb5 E11 DQa1 67 H2 NC H2 NC 28 D11 DQb4 D11 DQa0 68 H3 NC H3 NC 29 F10 DQb3 C11 NC 69 J1 DQd8 J1 DQb4 30 E10 DQb2 E10 NC 70 K1 DQd7 K1 DQb3 31 D10 DQb1 D10 NC 71 J2 DQd6 J2 DQb2 32 C11 DQb0 F10 NC 72 L1 DQd5 L1 DQb1 33 A11 NC A11 A18 73 M1 DQd4 M1 DQb0 34 B11 NC B11 NC 74 K2 DQd3 N1 NC 35 A10 A10 A10 A10 75 L2 DQd2 L2 NC 36 B10 A9 B10 A9 76 M2 DQd1 M2 NC 37 A9 A8 A9 A8 77 N1 DQd0 K2 NC 38 B9 NC B9 NC 78 N2 NC N2 NC 39 C10 NC C10 NC 79 P1 NC P1 NC 40 A8 ADV A8 ADV 80 R1 MODE R1 MODE 30 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A1 05/23/2016 IS61NLF25636B/IS61NVF/NVVF25636B IS61NLF51218B/IS61NVF/NVVF51218B  165 BGA X36 X18 Bit # Bump ID Signal Bump ID Signal 81 R2 NC R2 NC 82 P3 A5 P3 A5 83 R3 A4 R3 A4 84 P2 NC P2 NC 85 P4 A2 P4 A2 86 R4 A3 R4 A3 87 N5 NC N5 NC 88 P6 A1 P6 A1 89 R6 A0 R6 A0 90 * Int * Int Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 31 Rev. A1 05/23/2016 IS61NLF25636B/IS61NVF/NVVF25636B IS61NLF51218B/IS61NVF/NVVF51218B  ORDERING INFORMATION (Vdd = 3.3V/Vddq = 2.5V/3.3V) Commercial Range: 0°C to +70°C Access Time Order Part Number Package 256Kx36 6.5 IS61NLF25636B-6.5TQ 100 QFP IS61NLF25636B-6.5TQL 100 QFP, Lead-free IS61NLF25636B-6.5B2 119 BGA IS61NLF25636B-6.5B3 165 BGA 7.5 IS61NLF25636B-7.5TQ 100 QFP IS61NLF25636B-7.5TQL 100 QFP, Lead-free IS61NLF25636B-7.5B2 119 BGA IS61NLF25636B-7.5B3 165 BGA 512Kx18 6.5 IS61NLF51218B-6.5TQ 100 QFP IS61NLF51218B-6.5TQL 100 QFP, Lead-free IS61NLF51218B-6.5B2 119 BGA IS61NLF51218B-6.5B3 165 BGA 7.5 IS61NLF51218B-7.5TQ 100 QFP IS61NLF51218B-7.5TQL 100 QFP, Lead-free IS61NLF51218B-7.5B2 119 BGA IS61NLF51218B-7.5B3 165 BGA ORDERING INFORMATION (Vdd = 3.3V/Vddq = 2.5V/3.3V) Industrial Range: -40°C to +85°C Access Time Order Part Number Package 256Kx36 6.5 IS61NLF25636B-6.5TQI 100 QFP IS61NLF25636B-6.5TQLI 100 QFP, Lead-free IS61NLF25636B-6.5B2I 119 BGA IS61NLF25636B-6.5B3I 165 BGA 7.5 IS61NLF25636B-7.5TQI 100 QFP IS61NLF25636B-7.5TQLI 100 QFP, Lead-free IS61NLF25636B-7.5B2I 119 BGA IS61NLF25636B-7.5B3I 165 BGA 512Kx18 6.5 IS61NLF51218B-6.5TQI 100 QFP IS61NLF51218B-6.5TQLI 100 QFP, Lead-free IS61NLF51218B-6.5B2I 119 BGA IS61NLF51218B-6.5B3I 165 BGA 7.5 IS61NLF51218B-7.5TQI 100 QFP IS61NLF51218B-7.5TQLI 100 QFP, Lead-free IS61NLF51218B-7.5B2I 119 BGA IS61NLF51218B-7.5B3I 165 BGA 32 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A1 05/23/2016 IS61NLF25636B/IS61NVF/NVVF25636B IS61NLF51218B/IS61NVF/NVVF51218B  ORDERING INFORMATION (Vdd = 2.5V/Vddq = 2.5V) Industrial Range: -40°C to +85°C Access Time 6.5 7.5 6.5 7.5 Order Part Number Package 256Kx36 IS61NVF25636B-6.5TQI 100 QFP IS61NVF25636B-6.5B2I 119 BGA IS61NVF25636B-6.5B3I 165 BGA IS61NVF25636B-7.5TQI 100 QFP IS61NVF25636B-7.5B2I 119 BGA IS61NVF25636B-7.5B3I 165 BGA 512Kx18 IS61NVF51218B-6.5TQI 100 QFP IS61NVF51218B-6.5B2I 119 BGA IS61NVF51218B-6.5B3I 165 BGA IS61NVF51218B-7.5TQI 100 QFP IS61NVF51218B-7.5B2I 119 BGA IS61NVF51218B-7.5B3I 165 BGA ORDERING INFORMATION (Vdd = 1.8V/Vddq = 1.8V) Please contact SRAM Marketing at sram@issi.com Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 33 Rev. A1 05/23/2016 IS61NLF25636B/IS61NVF/NVVF25636B IS61NLF51218B/IS61NVF/NVVF51218B  34 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A1 05/23/2016 IS61NLF25636B/IS61NVF/NVVF25636B IS61NLF51218B/IS61NVF/NVVF51218B  Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 35 Rev. A1 05/23/2016 36 Package Outline 1. CONTROLLING DIMENSION : MM . NOTE : 08/28/2008 IS61NLF25636B/IS61NVF/NVVF25636B IS61NLF51218B/IS61NVF/NVVF51218B  Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A1 05/23/2016