IS61NLP102418-200B3I-TR

IS61NLP25672/IS61NVP25672 IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418  256K x 72, 512K x 36 and 1M x 18 18Mb, PIPELINE 'NO WAIT' STATE BUS SRAM SEPTEMBER 2011 FEATURES DESCRIPTION • 100 percent bus utilization The 18 Meg 'NLP/NVP' product family feature high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, 'no wait' state, device for networking and communications applications. They are organized as 256K words by 72 bits, 512K words by 36 bits and 1M words by 18 bits, fabricated with ISSI's advanced CMOS technology. • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control using MODE input • Three chip enables for simple depth expansion and address pipelining • Power Down mode • Common data inputs and data outputs • CKE pin to enable clock and suspend operation • JEDEC 100-pin TQFP, 119-ball PBGA, 165-ball PBGA and 209-ball (x72) PBGA packages • Power supply: NVP: Vdd 2.5V (± 5%), Vddq 2.5V (± 5%) NLP: Vdd 3.3V (± 5%), Vddq 3.3V/2.5V (± 5%) • JTAG Boundary Scan for PBGA packages Incorporating a 'no wait' state feature, wait cycles are eliminated when the bus switches from read to write, or write to read. This device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers are controlled by a positive-edge-triggered single clock input. Operations may be suspended and all synchronous inputs ignored when Clock Enable, CKE is HIGH. In this state the internal device will hold their previous values. All Read, Write and Deselect cycles are initiated by the ADV input. When the ADV is HIGH the internal burst counter is incremented. New external addresses can be loaded when ADV is LOW. Write cycles are internally self-timed and are initiated by the rising edge of the clock inputs and when WE is LOW. Separate byte enables allow individual bytes to be written. A burst mode pin (MODE) defines the order of the burst sequence.When tied HIGH, the interleaved burst sequence is selected. When tied LOW, the linear burst sequence is selected. • Industrial temperature available • Lead-free available • Leaded option available upon request FAST ACCESS TIME Symbol tkq tkc Parameter Clock Access Time Cycle Time Frequency -250 2.6 4 250 -200 3.1 5 200 Units ns ns MHz Copyright © 2011 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc. — www.issi.com Rev.  O 09/19/2011 1 IS61NLP25672/IS61NVP25672  IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418  BLOCK DIAGRAM x 72: A [0:17] or x 36: A [0:18] or x 18: A [0:19] ADDRESS REGISTER A2-A17 or A2-A18 or A2-A19 MODE A0-A1 CLK CONTROL LOGIC K CKE WRITE ADDRESS REGISTER BURST ADDRESS COUNTER 256Kx72; 512Kx36; 1024Kx18 MEMORY ARRAY A'0-A'1 WRITE ADDRESS REGISTER K DATA-IN REGISTER K DATA-IN REGISTER CE CE2 CE2 ADV WE BWŸX } CONTROL REGISTER K CONTROL LOGIC (X=a,b,c,d or a,b) OUTPUT REGISTER BUFFER OE ZZ 72, 36 or 18 DQx/DQPx 2 Integrated Silicon Solution, Inc. — www.issi.com Rev. O 09/19/2011 IS61NLP25672/IS61NVP25672  IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418  Bottom View 165-Ball, 13 mm x 15mm BGA 1 mm Ball Pitch, 11 x 15 Ball Array Bottom View 209-Ball, 14 mm x 22 mm BGA 1 mm Ball Pitch, 11 x 19 Ball Array Integrated Silicon Solution, Inc. — www.issi.com Rev.  O 09/19/2011 3 IS61NLP25672/IS61NVP25672  IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418  Pin Configuration ­— 256K x 72, 209-Ball PBGA (Top View) A B C D E F G H J K L M N P R T U V W 1 DQg DQg DQg DQg DQPg DQc DQc DQc DQc NC DQh DQh DQh DQh DQPd DQd DQd DQd DQd 2 DQg DQg DQg DQg DQPc DQc DQc DQc DQc NC DQh DQh DQh DQh DQPh DQd DQd DQd DQd 3 A BWc BWh VSS Vddq VSS Vddq VSS Vddq CLK Vddq VSS Vddq VSS Vddq VSS NC A TMS 4 CE2 BWg BWd NC Vddq VSS Vddq VSS Vddq NC Vddq VSS Vddq VSS Vddq NC A A TDI 5 A NC NC NC Vdd VSS Vdd VSS Vdd VSS Vdd VSS Vdd VSS Vdd NC NC A A 6 ADV WE CE OE Vdd NC NC NC NC CKE NC NC NC ZZ Vdd MODE A A1 A0 7 A A NC NC Vdd VSS Vdd VSS Vdd VSS Vdd VSS Vdd VSS Vdd NC NC A A 8 CE2 BWb BWe NC Vddq VSS Vddq VSS Vddq NC Vddq VSS Vddq VSS Vddq NC A A TDO 9 A BWf BWa VSS Vddq VSS Vddq VSS Vddq NC Vddq VSS Vddq VSS Vddq VSS NC A TCK 10 DQb DQb DQb DQb DQPf DQf DQf DQf DQf NC DQa DQa DQa DQa DQPa DQe DQe DQe DQe 11 DQb DQb DQb DQb DQPb DQf DQf DQf DQf NC DQa DQa DQa DQa DQPe DQe DQe DQe DQe 11 x 19 Ball BGA—14 x 22 mm2 Body—1 mm Ball Pitch PIN DESCRIPTIONS Symbol A A0, A1 Pin Name Synchronous Address Inputs Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus. ADV Synchronous Burst Address Advance BWa-BWh Synchronous Byte Write Enable CE, CE2, CE2 Synchronous Chip Enable CLK Synchronous Clock CKE Clock Enable DQx Synchronous Data Input/Output DQPx Parity Data I/O 4 Vss MODE OE TCK, TDI TDO, TMS Vdd Vddq WE ZZ Ground Burst Sequence Selection Output Enable JTAG Pins 3.3V/2.5V Power Supply Isolated Output Buffer Supply: 3.3V/2.5V Write Enable Snooze Enable Integrated Silicon Solution, Inc. — www.issi.com Rev. O 09/19/2011 IS61NLP25672/IS61NVP25672  IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418  Pin Configuration ­— 512K x 36, 165-Ball PBGA (Top View) A B C D E F G H J K L M N P R 1 2 3 4 5 6 7 8 9 10 11 NC NC DQPc DQc DQc DQc DQc NC DQd DQd DQd DQd DQPd NC MODE A A NC DQc DQc DQc DQc VDD DQd DQd DQd DQd NC NC NC CE CE2 Vddq Vddq Vddq Vddq Vddq NC Vddq Vddq Vddq Vddq Vddq A A BWc BWd VSS Vdd Vdd Vdd Vdd Vdd Vdd Vdd Vdd Vdd VSS A A BWb BWa VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDI TMS CE2 CLK VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC A1* A0* CKE WE VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDO TCK ADV OE VSS Vdd Vdd Vdd Vdd Vdd Vdd Vdd Vdd Vdd VSS A A A A A A NC DQb DQb DQb DQb NC DQa DQa DQa DQa NC A A NC NC DQPb DQb DQb DQb DQb ZZ DQa DQa DQa DQa DQPa NC A Vddq Vddq Vddq Vddq Vddq NC Vddq Vddq Vddq Vddq Vddq A A Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired. PIN DESCRIPTIONS Symbol A A0, A1 ADV Pin Name Address Inputs Synchronous Burst Address Inputs Synchronous Burst Address Advance/ Load WE Synchronous Read/Write Control Input CLK Synchronous Clock CKE Clock Enable CE, CE2, CE2 Synchronous Chip Enable BWx (x=a-d) Synchronous Byte Write Inputs OE Output Enable ZZ Power Sleep Mode Integrated Silicon Solution, Inc. — www.issi.com Rev.  O 09/19/2011 MODE TCK, TDI TDO, TMS VDD NC DQx DQPx VDDQ Vss Burst Sequence Selection JTAG Pins 3.3V/2.5V Power Supply No Connect Data Inputs/Outputs Parity Data I/O Isolated output Power Supply 3.3V/2.5V Ground 5 IS61NLP25672/IS61NVP25672  IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418  165-PIN PBGA PACKAGE CONFIGURATION 1024K x 18 (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 A NC A BWb NC CE2 CKE ADV A NC A NC NC VDDQ BWa Vss CLK Vss WE Vss VDDQ NC NC DQPa D NC DQb VDDQ VDD Vss Vss Vss OE Vss VDD A C NC Vss A A A B CE CE2 VDDQ NC DQa E NC DQb VDDQ VDD Vss Vss Vss VDD VDDQ NC DQa F NC DQb VDDQ VDD Vss Vss Vss VDD VDDQ NC DQa G NC DQb VDDQ Vss NC NC NC ZZ J DQb NC VDDQ VDD Vss Vss VDD VDD DQa VDD Vss Vss NC NC Vss Vss VDDQ H VDD VDD Vss Vss VDD VDDQ DQa NC K DQb NC VDDQ VDD Vss Vss Vss VDD VDDQ DQa L DQb NC VDDQ VDD Vss Vss VDD VDDQ DQa M DQb NC VDDQ VDD Vss Vss Vss NC NC Vss VDD VDDQ DQa NC N DQPb NC Vss NC TDO A A NC R MODE NC A A TMS A1* A0* VDDQ A NC NC NC TDI NC NC Vss A NC P VDDQ A TCK A A A A Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired. PIN DESCRIPTIONS Symbol A A0, A1 ADV Pin Name Address Inputs Synchronous Burst Address Inputs Synchronous Burst Address Advance/ Load WE Synchronous Read/Write Control Input CLK Synchronous Clock CKE Clock Enable CE, CE2, CE2 Synchronous Chip Enable BWx (x=a,b) Synchronous Byte Write Inputs OE Output Enable ZZ Power Sleep Mode 6 MODE TCK, TDI TDO, TMS VDD NC DQx DQPx VDDQ Vss Burst Sequence Selection JTAG Pins 3.3V/2.5V Power Supply No Connect Data Inputs/Outputs Parity Data I/O Isolated output Power Supply 3.3V/2.5V Ground Integrated Silicon Solution, Inc. — www.issi.com Rev. O 09/19/2011 IS61NLP25672/IS61NVP25672  IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418  119-PIN PBGA PACKAGE CONFIGURATION 1024K x 18 (TOP VIEW) 1 2 3 4 5 6 7 A VDDQ A A A A A VDDQ B NC CE2 A ADV A CE2 NC C NC A A VDD A A NC D DQb NC VSS NC Vss DQPa NC E DQb VSS CE Vss NC DQa F NC VDDQ NC VSS OE Vss DQa VDDQ G NC DQb BWb A NC NC DQa H DQb NC WE Vss DQa NC J VDDQ VDD VSS NC VDD NC VDD VDDQ K NC DQb VSS CLK Vss NC DQa L DQb NC NC NC BWa DQa NC M VDDQ DQb VSS CKE Vss NC VDDQ N DQb NC VSS A 1* Vss DQa NC P NC DQPb VSS A0* Vss NC DQa R NC A MODE VDD NC A NC T NC A A NC A A ZZ U VDDQ TMS TDI TCK TDO NC VDDQ Note: A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired. PIN DESCRIPTIONS Symbol A A0, A1 ADV WE CLK CKE CE CE2 CE2 BWx (x=a,b) Pin Name Address Inputs Synchronous Burst Address Inputs Synchronous Burst Address Advance/ Load Synchronous Read/Write Control Input Synchronous Clock Clock Enable Synchronous Chip Select Synchronous Chip Select Synchronous Chip Select Synchronous Byte Write Inputs Integrated Silicon Solution, Inc. — www.issi.com Rev.  O 09/19/2011 OE ZZ MODE TCK, TDO TMS, TDI Vdd Vss NC DQa-DQb DQPa-Pb Vddq Output Enable Power Sleep Mode Burst Sequence Selection JTAG Pins Power Supply Ground No Connect Data Inputs/Outputs Parity Data I/O Output Power Supply 7 IS61NLP25672/IS61NVP25672  IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418  PIN CONFIGURATION DQb NC VDD DQa DQb DQa DQb VDDQ VDDQ Vss DQa DQa DQa DQa Vss VDDQ DQa DQa DQPa NC Vss Vss DQb DQb DQPb NC Vss VDDQ NC NC NC A ADV A OE CLK WE CKE CE2 VDD Vss BWa NC BWb NC CE2 CE A A A NC NC VDDQ Vss NC DQPa DQa DQa Vss VDDQ DQa DQa Vss NC VDD ZZ DQa DQa VDDQ Vss DQa DQa NC NC Vss VDDQ NC NC NC A A DQb Vss NC VDD ZZ A DQb A VDDQ DQb A VDDQ NC A A Vss NC DQb Vss VDD DQb DQb Vss DQb NC NC NC NC A1 A0 MODE DQd DQd DQPd DQb DQb VDDQ Vss A VDDQ Vss NC A DQd DQd Vss VDDQ NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 10 71 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 A DQd DQb NC A Vss DQd DQb MODE DQd VDDQ DQPb A A DQd A NC Vss A DQc NC VDD A DQc NC A A VDDQ NC Vss Vss DQc VDD DQc NC NC DQc DQc A1 A0 Vss A VDDQ A DQc A DQc 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 10 71 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 A DQPc A A A A A ADV A OE CKE CLK WE CE2 VDD Vss BWa BWc BWb BWd CE2 CE A A 100-Pin TQFP 1M x 18 512K x 36 PIN DESCRIPTIONS A0, A1 A CLK ADV BWa-BWd WE CKE Vss NC 8 Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus. Synchronous Address Inputs Synchronous Clock Synchronous Burst Address Advance Synchronous Byte Write Enable Write Enable Clock Enable Ground for Core Not Connected CE, CE2, CE2 OE DQa-DQd DQPa-DQPd MODE Vdd Vss Vddq ZZ Synchronous Chip Enable Output Enable Synchronous Data Input/Output Parity Data I/O Burst Sequence Selection +3.3V/2.5V Power Supply Ground for output Buffer Isolated Output Buffer Supply: +3.3V/2.5V Snooze Enable Integrated Silicon Solution, Inc. — www.issi.com Rev. O 09/19/2011 IS61NLP25672/IS61NVP25672  IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418  STATE DIAGRAM READ READ READ BURST WRITE BEGIN READ DS DS READ WRITE DESELECT BURST BURST READ BEGIN WRITE BURST DS BURST DS DS WRITE READ BURST WRITE WRITE WRITE BURST SYNCHRONOUS TRUTH TABLE(1) Operation Not Selected Not Selected Not Selected Not Selected Continue Begin Burst Read Continue Burst Read NOP/Dummy Read Dummy Read Begin Burst Write Continue Burst Write NOP/Write Abort Write Abort Ignore Clock Notes: Address  Used N/A N/A N/A N/A External Address Next Address External Address Next Address External Address Next Address N/A Next Address Current Address CE H X X X L X L X L X L X X CE2 X L X X H X H X H X H X X CE2 X X H X L X L X L X L X X ADV L L L H L H L H L H L H X WE X X X X H X H X L X L X X BWx X X X X X X X X L L H H X OE X X X X L L H H X X X X X CKE L L L L L L L L L L L L H CLK ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ 1. "X" means don't care. 2. The rising edge of clock is symbolized by ↑ 3. A continue deselect cycle can only be entered if a deselect cycle is executed first. 4. WE = L means Write operation in Write Truth Table. WE = H means Read operation in Write Truth Table. 5. Operation finally depends on status of asynchronous pins (ZZ and OE). Integrated Silicon Solution, Inc. — www.issi.com Rev.  O 09/19/2011 9 IS61NLP25672/IS61NVP25672  IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418  ASYNCHRONOUS TRUTH TABLE(1) Operation Sleep Mode Read Write Deselected Notes: ZZ H L L L L I/O STATUS High-Z DQ High-Z Din, High-Z High-Z OE X L H X X 1. X means "Don't Care". 2. For write cycles following read cycles, the output buffers must be disabled with OE, otherwise data bus contention will occur. 3. Sleep Mode means power Sleep Mode where stand-by current does not depend on cycle time. 4. Deselected means power Sleep Mode where stand-by current depends on cycle time. WRITE TRUTH TABLE (x18) Operation READ WRITE BYTE a WRITE BYTE b WRITE ALL BYTEs WRITE ABORT/NOP Notes: WE H L L L L BWa X L H L H BWb X H L L H 1. X means "Don't Care". 2. All inputs in this table must beet setup and hold time around the rising edge of CLK. WRITE TRUTH TABLE (x36) Operation READ WRITE BYTE a WRITE BYTE b WRITE BYTE c WRITE BYTE d WRITE ALL BYTEs WRITE ABORT/NOP Notes: WE H L L L L L L BWa X L H H H L H BWb X H L H H L H BWc X H H L H L H BWd X H H H L L H 1. X means "Don't Care". 2. All inputs in this table must beet setup and hold time around the rising edge of CLK. 10 Integrated Silicon Solution, Inc. — www.issi.com Rev. O 09/19/2011 IS61NLP25672/IS61NVP25672  IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418  WRITE TRUTH TABLE (x72) Operation READ WRITE BYTE a WRITE BYTE b WRITE BYTE c WRITE BYTE d WRITE BYTE e WRITE BYTE f WRITE BYTE g WRITE BYTE h WRITE ALL BYTEs WRITE ABORT/NOP Notes: WE H L L L L L L L L L L BWa X L H H H H H H H L H BWb X H L H H H H H H L H BWc X H H L H H H H H L H BWd X H H H L H H H H L H BWe X H H H H L H H H L H BWf X H H H H H L H H L H BWg X H H H H H H L H L H BWh X H H H H H H H L L H 1. X means "Don't Care". 2. All inputs in this table must beet setup and hold time around the rising edge of CLK. INTERLEAVED BURST ADDRESS TABLE (MODE = Vdd or NC) External Address A1  A0 00 01 10 11 1st Burst Address A1  A0 01 00 11 10 2nd Burst Address A1  A0 10 11 00 01 Integrated Silicon Solution, Inc. — www.issi.com Rev.  O 09/19/2011 3rd Burst Address  A1  A0 11 10 01 00 11 IS61NLP25672/IS61NVP25672  IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418  LINEAR BURST ADDRESS TABLE (MODE = Vss)   0,0 A1', A0' = 1,1 0,1 1,0 ABSOLUTE MAXIMUM RATINGS(1) Symbol Tstg Pd Iout Vin, Vout Vin Parameter Storage Temperature Power Dissipation Output Current (per I/O) Voltage Relative to Vss for I/O Pins Voltage Relative to Vss for for Address and Control Inputs Value –65 to +150 1.6 100 –0.5 to Vddq + 0.3 –0.3 to 4.6 Unit °C W mA V V Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. This device contains circuity to protect the inputs against damage due to high static voltages or electric fields; however, precautions may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. 3. This device contains circuitry that will ensure the output devices are in High-Z at power up. OPERATING RANGE (IS61NLPx) Range Commercial Industrial Ambient Temperature 0°C to +70°C -40°C to +85°C Vdd 3.3V ± 5% 3.3V ± 5% Vddq 3.3V / 2.5V ± 5% 3.3V / 2.5V ± 5% Vdd 2.5V ± 5% 2.5V ± 5% Vddq 2.5V ± 5% 2.5V ± 5% OPERATING RANGE (IS61NVPx) Range Commercial Industrial 12 Ambient Temperature 0°C to +70°C -40°C to +85°C Integrated Silicon Solution, Inc. — www.issi.com Rev. O 09/19/2011 IS61NLP25672/IS61NVP25672  IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418  DC ELECTRICAL CHARACTERISTICS (Over Operating Range) 3.3V Symbol Voh Vol Vih Vil Ili Ilo Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current Output Leakage Current Test Conditions Ioh = –4.0 mA  (3.3V) Ioh = –1.0 mA  (2.5V) Iol = 8.0 mA  (3.3V) Iol = 1.0 mA  (2.5V) Vss ≤ Vin ≤ Vdd(1) Vss ≤ Vout ≤ Vddq, OE = Vih Min. 2.4 — 2.0 –0.3 –5 –5 2.5V Max. — Min. 2.0 Max. — Unit V 0.4 — 0.4 V Vdd + 0.3 0.8 5 5 1.7 –0.3 –5 –5 Vdd + 0.3 0.7 5 5 V V µA µA POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter Icc AC Operating Supply Current Isb Standby Current TTL Input Isbi Standby Current CMOS Input Isb2 Sleep Mode Test Conditions Temp. range x18 Device Selected, Com. 450 OE = Vih, ZZ ≤ Vil, Ind. 500 All Inputs ≤ 0.2V or ≥ Vdd – 0.2V, Cycle Time ≥ tkc min. Device Deselected, Com. 150 Vdd = Max., Ind. 150 All Inputs ≤ Vil or ≥ Vih, ZZ ≤ Vil, f = Max. Device Deselected, Com. 110 Vdd = Max., Ind. 125 Vin ≤ Vss + 0.2V or ≥Vdd – 0.2V f=0 ZZ>Vih Com. 60 Ind. 75 -250 MAX x36 450 500 x18 425 475 -200 MAX x36 425 475 x72 600 650 x72 550 600 Unit mA 150 150 150 150 150 150 150 150 150 150 mA 110 125 110 125 110 125 110 125 110 125 mA 60 75 60 75 60 75 60 75 60 75 mA Note: 1. MODE pin has an internal pullup and should be tied to Vdd or Vss. It exhibits ±100µA maximum leakage current when tied to ≤ Vss + 0.2V or ≥ Vdd – 0.2V. Integrated Silicon Solution, Inc. — www.issi.com Rev.  O 09/19/2011 13 IS61NLP25672/IS61NVP25672  IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418  CAPACITANCE(1,2) Symbol Cin Cout Parameter Input Capacitance Input/Output Capacitance Conditions Vin = 0V Vout = 0V Max. 6 8 Unit pF pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: Ta = 25°C, f = 1 MHz, Vdd = 3.3V. 3.3V I/O AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0V to 3.0V 1.5 ns 1.5V See Figures 1 and 2 3.3V I/O OUTPUT LOAD EQUIVALENT 317 Ω +3.3V Zo= 50Ω OUTPUT OUTPUT 50Ω 5 pF Including jig and scope 351 Ω 1.5V Figure 1 14 Figure 2 Integrated Silicon Solution, Inc. — www.issi.com Rev. O 09/19/2011 IS61NLP25672/IS61NVP25672  IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418  2.5V I/O AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0V to 2.5V 1.5 ns 1.25V See Figures 3 and 4 2.5V I/O OUTPUT LOAD EQUIVALENT 1,667 Ω +2.5V ZO = 50Ω OUTPUT OUTPUT 50Ω 5 pF Including jig and scope 1,538 Ω 1.25V Figure 3 Integrated Silicon Solution, Inc. — www.issi.com Rev.  O 09/19/2011 Figure 4 15 IS61NLP25672/IS61NVP25672  IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418  READ/WRITE CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) Parameter Clock Frequency Cycle Time Clock High Time Clock Low Time Clock Access Time Clock High to Output Invalid Clock High to Output Low-Z Clock High to Output High-Z Output Enable to Output Valid Output Enable to Output Low-Z -250 Min. Max. — 250 4.0 — 1.7 — 1.7 — — 2.6 0.8 — 0.8 — — 2.6 — 2.8 0 — -200 Min. Max. — 200 5 — 2 — 2 — — 3.1 1.5 — 1 — — 3.0 — 3.1 0 — Unit MHz ns ns ns ns ns ns ns ns ns Output Disable to Output High-Z Address Setup Time Read/Write Setup Time Chip Enable Setup Time Clock Enable Setup Time Address Advance Setup Time Data Setup Time Address Hold Time Clock Enable Hold Time Write Hold Time Chip Enable Hold Time Address Advance Hold Time Data Hold Time ZZ High to Power Down ZZ Low to Power Down — 1.2 1.2 1.2 1.2 1.2 1.2 0.3 0.3 0.3 0.3 0.3 0.3 — — — 3.0 1.4 — 1.4 — 1.4 — 1.4 — 1.4 — 1.4 — 0.4 — 0.4 — 0.4 — 0.4 — 0.4 — 0.4 — — 2 — 2 ns ns ns ns ns ns ns ns ns ns ns ns ns cyc cyc   Symbol fmax tkc tkh tkl tkq tkqx(2) tkqlz(2,3) tkqhz(2,3) toeq toelz(2,3) toehz(2,3) tas tws tces tse tadvs tds tah the twh tceh tadvh tdh tpds tpus Notes: 2.6 — — — — — — — — — — — — 2 2 1.  Configuration signal MODE is static and must not change during normal operation. 2.  Guaranteed but not 100% tested. This parameter is periodically sampled. 3.  Tested with load in Figure 2. 16 Integrated Silicon Solution, Inc. — www.issi.com Rev. O 09/19/2011 IS61NLP25672/IS61NVP25672  IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418  SLEEP MODE ELECTRICAL CHARACTERISTICS Symbol Isb2 tpds tpus tzzi trzzi Parameter Current during SLEEP MODE ZZ active to input ignored ZZ inactive to input sampled ZZ active to SLEEP current ZZ inactive to exit SLEEP current Conditions ZZ ≥ Vih Min. 2 2 2 0 Max. 60 Unit mA cycle cycle cycle ns SLEEP MODE TIMING CLK tPDS ZZ setup cycle tPUS ZZ recovery cycle ZZ tZZI Isupply ISB2 tRZZI All Inputs (except ZZ) Deselect or Read Only Deselect or Read Only Normal operation cycle Outputs (Q) High-Z Don't Care Integrated Silicon Solution, Inc. — www.issi.com Rev.  O 09/19/2011 17 IS61NLP25672/IS61NVP25672  IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418  READ CYCLE TIMING tKH tKL CLK tKC tADVS tADVH ADV tAS tAH Address A1 A3 A2 tWS tWH WRITE tSE tHE CKE tCES tCEH CE OE tOEQ tOEHZ Data Out Q1-1 tOEHZ tKQX Q2-1 tKQ Q2-2 tKQHZ Q2-3 NOTES: WRITE = L means WE = L and BWx = L WE = L and BWX = L CE = L means CE1 = L, CE2 = H and CE2 = L CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L 18 Q2-4 Q3-1 Q3-2 Q3-3 Q3-4 Don't Care Undefined Integrated Silicon Solution, Inc. — www.issi.com Rev. O 09/19/2011 IS61NLP25672/IS61NVP25672  IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418  WRITE CYCLE TIMING tKH tKL CLK tKC ADV Address A1 A3 A2 WRITE tSE tHE CKE CE OE tDS Data In D1-1 D2-1 D2-2 D2-3 D2-4 D3-1 tDH D3-2 D3-3 D3-4 tOEHZ Data Out Q0-3 Q0-4 NOTES: WRITE = L means WE = L and BWx = L WE = L and BWX = L CE = L means CE1 = L, CE2 = H and CE2 = L CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L Integrated Silicon Solution, Inc. — www.issi.com Rev.  O 09/19/2011 Don't Care Undefined 19 IS61NLP25672/IS61NVP25672  IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418  SINGLE READ/WRITE CYCLE TIMING tKH tKL CLK tSE tHE tKC CKE Address A1 A2 A3 A4 Q1 Q3 A5 A6 A7 A8 A9 WRITE CE ADV OE tOEQ Data Out tOELZ Q4 Q6 Q7 tDS tDH Data In D2 NOTES: WRITE = L means WE = L and BWx = L CE = L means CE1 = L, CE2 = H and CE2 = L CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L 20 D5 Don't Care Undefined Integrated Silicon Solution, Inc. — www.issi.com Rev. O 09/19/2011 IS61NLP25672/IS61NVP25672  IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418  CKE OPERATION TIMING tKH tKL CLK tSE tHE tKC CKE Address A1 A2 A3 A4 A5 A6 WRITE CE ADV OE tKQ Data Out tKQLZ tKQHZ Q1 Q3 Q4 tDS tDH Data In D2 NOTES: WRITE = L means WE = L and BWx = L CE = L means CE1 = L, CE2 = H and CE2 = L CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L Integrated Silicon Solution, Inc. — www.issi.com Rev.  O 09/19/2011 Don't Care Undefined 21 IS61NLP25672/IS61NVP25672  IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418  CE OPERATION TIMING tKH tKL CLK tSE tHE tKC CKE Address A1 A2 A3 A4 A5 WRITE CE ADV OE tOEQ Data Out tOELZ tKQHZ Q1 tKQ tKQLZ Q2 Q4 tDS tDH Data In D3 NOTES: WRITE = L means WE = L and BWx = L CE = L means CE1 = L, CE2 = H and CE2 = L CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L 22 D5 Don't Care Undefined Integrated Silicon Solution, Inc. — www.issi.com Rev. O 09/19/2011 IS61NLP25672/IS61NVP25672  IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418  IEEE 1149.1 Serial Boundary Scan (JTAG) Test Access Port (TAP) - Test Clock The IS61NLP and IS61NVP have a serial boundary scan Test Access Port (TAP) in the PBGA package only. (Not available in TQFP package.) This port operates in accordance with IEEE Standard 1149.1-1900, but does not include all functions required for full 1149.1 compliance. These functions from the IEEE specification are excluded because they place added delay in the critical speed path of the SRAM. The TAP controller operates in a manner that does not conflict with the performance of other devices using 1149.1 fully compliant TAPs. The TAP operates using JEDEC standard 2.5V I/O logic levels. The test clock is only used with the TAP controller. All inputs are captured on the rising edge of TCK and outputs are driven from the falling edge of TCK. Disabling the JTAG Feature The SRAM can operate without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (Vss) to prevent clocking of the device. TDI and TMS are internally pulled up and may be disconnected. They may alternately be connected to Vdd through a pull-up resistor. TDO should be left disconnected. On power-up, the device will start in a reset state which will not interfere with the device operation. Test Mode Select (TMS) The TMS input is used to send commands to the TAP controller and is sampled on the rising edge of TCK. This pin may be left disconnected if the TAP is not used. The pin is internally pulled up, resulting in a logic HIGH level. Test Data-In (TDI) The TDI pin is used to serially input information to the registers and can be connected to the input of any register. The register between TDI and TDO is chosen by the instruction loaded into the TAP instruction register. For information on instruction register loading, see the TAP Controller State Diagram. TDI is internally pulled up and can be disconnected if the TAP is unused in an application. TDI is connected to the Most Significant Bit (MSB) on any register. tap controller block diagram 0 Bypass Register 2 1 0 Instruction Register TDI Selection Circuitry 31 30 29 . . . Selection Circuitry 2 1 0 2 1 0 TDO Identification Register x . . . . . Boundary Scan Register* TCK TMS TAP CONTROLLER Integrated Silicon Solution, Inc. — www.issi.com Rev.  O 09/19/2011 23 IS61NLP25672/IS61NVP25672  IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418  Test Data Out (TDO) Boundary Scan Register The TDO output pin is used to serially clock data-out from the registers. The output is active depending on the current state of the TAP state machine (see TAP Controller State Diagram). The output changes on the falling edge of TCK and TDO is connected to the Least Significant Bit (LSB) of any register. The boundary scan register is connected to all input and output pins on the SRAM. Several no connect (NC) pins are also included in the scan register to reserve pins for higher density devices. The x36 configuration has a 75-bit-long register and the x18 configuration also has a 75-bit-long register. The boundary scan register is loaded with the contents of the RAM Input and Output ring when the TAP controller is in the Capture-DR state and then placed between the TDI and TDO pins when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD and SAMPLE-Z instructions can be used to capture the contents of the Input and Output ring. The Boundary Scan Order tables show the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI, and the LSB is connected to TDO. Performing a TAP Reset A Reset is performed by forcing TMS HIGH (Vdd) for five rising edges of TCK. RESET may be performed while the SRAM is operating and does not affect its operation. At power-up, the TAP is internally reset to ensure that TDO comes up in a high-Z state. TAP Registers Registers are connected between the TDI and TDO pins and allow data to be scanned into and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction registers. Data is serially loaded into the TDI pin on the rising edge of TCK and output on the TDO pin on the falling edge of TCK. Instruction Register Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO pins. (See TAP Controller Block Diagram)  At power-up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as previously described. When the TAP controller is in the CaptureIR state, the two least significant bits are loaded with a binary “01” pattern to allow for fault isolation of the board level serial test path. Bypass Register To save time when serially shifting data through registers, it is sometimes advantageous to skip certain states. The bypass register is a single-bit register that can be placed between TDI and TDO pins. This allows data to be shifted through the SRAM with minimal delay. The bypass register is set LOW (Vss) when the BYPASS instruction is executed. Scan Register Sizes Register Name Instruction Bypass ID Boundary Scan Bit Size (x18) 3 1 32 75 Bit Size (x36) 3 1 32 75 Bit Size (x72) 3 1 32 TBD Identification (ID) Register The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded to the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has vendor code and other information described in the Identification Register Definitions table. Identification Register Definitions Instruction Field Description 256K x 72 512K x 36 1M x 18 Revision Number  (31:28) Reserved for version number. xxxx xxxx xxxx Device Depth  (27:23) Defines depth of SRAM. 512K or 1M 00110 00111 01000 Device Width  (22:18) Defines width of the SRAM. x72, x36 or x18 00101 00100 00011 ISSI Device ID  (17:12) Reserved for future use. xxxx xxxxx xxxxx ISSI JEDEC ID  (11:1) Allows unique identification of SRAM vendor. 0011010101 00011010101 00011010101 ID Register Presence  (0) Indicate the presence of an ID register. 1 1 1 24 Integrated Silicon Solution, Inc. — www.issi.com Rev. O 09/19/2011 IS61NLP25672/IS61NVP25672  IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418  TAP Instruction Set SAMPLE/PRELOAD Eight instructions are possible with the three-bit instruction register and all combinations are listed in the Instruction Code table. Three instructions are listed as RESERVED and should not be used and the other five instructions are described below. The TAP controller used in this SRAM is not fully compliant with the 1149.1 convention because some mandatory instructions are not fully implemented. The TAP controller cannot be used to load address, data or control signals and cannot preload the Input or Output buffers. The SRAM does not implement the 1149.1 commands EXTEST or INTEST or the PRELOAD portion of SAMPLE/ PRELOAD; instead it performs a capture of the Inputs and Output ring when these instructions are executed. Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted from the instruction register through the TDI and TDO pins. To execute an instruction once it is shifted in, the TAP controller must be moved into the Update-IR state. SAMPLE/PRELOAD is a 1149.1 mandatory instruction.The PRELOAD portion of this instruction is not implemented, so the TAP controller is not fully 1149.1 compliant. When the SAMPLE/PRELOAD instruction is loaded to the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the inputs and output pins is captured in the boundary scan register. It is important to realize that the TAP controller clock operates at a frequency up to 10 MHz, while the SRAM clock runs more than an order of magnitude faster. Because of the clock frequency differences, it is possible that during the Capture-DR state, an input or output will under-go a transition. The TAP may attempt a signal capture while in transition (metastable state).The device will not be harmed, but there is no guarantee of the value that will be captured or repeatable results. To guarantee that the boundary scan register will capture the correct signal value, the SRAM signal must be stabilized long enough to meet the TAP controller’s capture set-up plus hold times (tcs and tch). To insure that the SRAM clock input is captured correctly, designs need a way to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is not an issue, it is possible to capture all other signals and simply ignore the value of the CLK captured in the boundary scan register. Once the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins. Note that since the PRELOAD part of the command is not implemented, putting the TAP into the Update to the UpdateDR state while performing a SAMPLE/PRELOAD instruction will have the same effect as the Pause-DR command. EXTEST EXTEST is a mandatory 1149.1 instruction which is to be executed whenever the instruction register is loaded with all 0s. Because EXTEST is not implemented in the TAP controller, this device is not 1149.1 standard compliant. The TAP controller recognizes an all-0 instruction. When an EXTEST instruction is loaded into the instruction register, the SRAM responds as if a SAMPLE/PRELOAD instruction has been loaded. There is a difference between the instructions, unlike the SAMPLE/PRELOAD instruction, EXTEST places the SRAM outputs in a High-Z state. IDCODE The IDCODE instruction causes a vendor-specific, 32bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO pins and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction is loaded into the instruction register upon power-up or whenever the TAP controller is given a test logic reset state. Bypass When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO pins. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. SAMPLE-Z Reserved The SAMPLE-Z instruction causes the boundary scan register to be connected between the TDI and TDO pins when the TAP controller is in a Shift-DR state. It also places all SRAM outputs into a High-Z state. These instructions are not implemented but are reserved for future use. Do not use these instructions. Integrated Silicon Solution, Inc. — www.issi.com Rev.  O 09/19/2011 25 IS61NLP25672/IS61NVP25672  IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418  Instruction Codes Code 000 Instruction EXTEST 001 IDCODE 010 SAMPLE-Z 011 100 RESERVED SAMPLE/PRELOAD 101 110 111 RESERVED RESERVED BYPASS Description Captures the Input/Output ring contents. Places the boundary scan register between the TDI and TDO. Forces all SRAM outputs to High-Z state. This instruction is not 1149.1 compliant. Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operation. Captures the Input/Output contents. Places the boundary scan register between TDI and TDO. Forces all SRAM output drivers to a High-Z state. Do Not Use: This instruction is reserved for future use. Captures the Input/Output ring contents. Places the boundary scan register between TDI and TDO. Does not affect the SRAM operation. This instruction does not implement 1149.1 preload function and is therefore not 1149.1 compliant. Do Not Use: This instruction is reserved for future use. Do Not Use: This instruction is reserved for future use. Places the bypass register between TDI and TDO. This operation does not affect SRAM operation. TAP CONTROLLER STATE DIAGRAM Test Logic Reset 1 0 Run Test/Idle 1 Select DR 0 0 1 1 1 Capture DR 0 Shift DR 1 Exit1 DR 0 Select IR 0 1 Exit1 IR 0 Pause DR 0 1 0 1 26 Exit2 DR 1 Update DR 0 Capture IR 0 Shift IR 1 0 Pause IR 1 0 1 1 0 1 0 Exit2 IR 1 Update IR 0 Integrated Silicon Solution, Inc. — www.issi.com Rev. O 09/19/2011 IS61NLP25672/IS61NVP25672  IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418  TAP Electrical Characteristics Over the Operating Range(1,2) Symbol Voh1 Voh2 Vol1 Vol2 Vih Vil Ix Notes: Parameter Output HIGH Voltage Output HIGH Voltage Output LOW Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current Test Conditions Ioh = –2.0 mA Ioh = –100 µA Iol = 2.0 mA Iol = 100 µA Vss ≤ V I ≤ Vddq Min. 1.7 2.1 — — 1.7 –0.3 –10 Max. — — 0.7 0.2 Vdd +0.3 0.7 10 Units V V V V V V µA 1. All Voltage referenced to Ground. 2. Overshoot: Vih (AC) ≤ Vdd +1.5V for t ≤ ttcyc/2, Undershoot: Vil (AC) ≤ 0.5V for t ≤ ttcyc/2, Power-up: Vih < 2.6V and Vdd < 2.4V and Vddq < 1.4V for t < 200 ms. TAP AC ELECTRICAL CHARACTERISTICS(1,2) (Over Operating Range) Symbol ttcyc ftf tth ttl ttmss ttdis tcs ttmsh ttdih tch ttdov ttdox Notes: Parameter Min. TCK Clock cycle time 100 TCK Clock frequency — TCK Clock HIGH 40 TCK Clock LOW 40 TMS setup to TCK Clock Rise 10 TDI setup to TCK Clock Rise 10 Capture setup to TCK Rise 10 TMS hold after TCK Clock Rise 10 TDI Hold after Clock Rise 10 Capture hold after Clock Rise 10 TCK LOW to TDO valid — TCK LOW to TDO invalid 0 Max. — 10 — — — — — — — — 20 — Unit ns MHz ns ns ns ns ns ns ns ns ns ns 1. Both tcs and tch refer to the set-up and hold time requirements of latching data from the boundary scan register. 2. Test conditions are specified using the load in TAP AC test conditions. tr/tf = 1 ns. Integrated Silicon Solution, Inc. — www.issi.com Rev.  O 09/19/2011 27 IS61NLP25672/IS61NVP25672  IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418  TAP AC TEST CONDITIONS (2.5V/3.3V) TAP Output Load Equivalent Input pulse levels 0 to 2.5V/0 to 3.0V Input rise and fall times 1ns Input timing reference levels 1.25V/1.5V Output reference levels 1.25V/1.5V Test load termination supply voltage 1.25V/1.5V Vtrig 1.25V/1.5V 50Ω Vtrig TDO Z0 = 50Ω 20 pF GND Tap timing 1 2 tTHTH 3 4 5 6 tTLTH TCK tTHTL tMVTH tTHMX TMS tDVTH tTHDX TDI tTLOV TDO tTLOX DON'T CARE UNDEFINED 28 Integrated Silicon Solution, Inc. — www.issi.com Rev. O 09/19/2011 IS61NLP25672/IS61NVP25672  IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418  209 Boundary Scan Order (256K X 72) Integrated Silicon Solution, Inc. — www.issi.com Rev.  O 09/19/2011 29 IS61NLP25672/IS61NVP25672  IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418  165 Pbga Boundary Scan Order (x 36) Signal Bump Bit # Name ID 1 MODE 1R 2 NC 6N 3 NC 11P 4 A 8P 5 A 8R 6 A 9R 7 A 9P 8 A 10P 9 A 10R 10 A 11R 11 ZZ 11H 12 DQa 11N 13 DQa 11M 14 DQa 11L 15 DQa 11K 16 DQa 11J 17 DQa 10M 18 DQa 10L 19 DQa 10K 20 DQa 10J 30 Bit # 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Signal Bump Name ID Bit # DQb 11G 41 DQb 11F 42 DQb 11E 43 DQb 11D 44 DQb 10G 45 DQb 10F 46 DQb 10E 47 DQb 10D 48 DQb 11C 49 NC 11A 50 A 10A 51 A 10B 52 A 9A 53 A 9B 54 ADV 8A 55 OE 8B 56 CKE 7A 57 WE 7B 58 CLK 6B 59 NC 11B 60 Signal Name NC CE2 BWa BWb BWc BWd CE2 CE A A NC DQc DQc DQc DQc DQc DQc DQc DQc DQc Bump ID 1A 6A 5B 5A 4A 4B 3B 3A 2A 2B 1B 1C 1D 1E 1F 1G 2D 2E 2F 2G Bit # 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 Signal Name DQd DQd DQd DQd DQd DQd DQd DQd DQd A A A A A1 A0 Bump ID 1J 1K 1L 1M 2J 2K 2L 2M 1N 3P 3R 4R 4P 6P 6R Integrated Silicon Solution, Inc. — www.issi.com Rev. O 09/19/2011 IS61NLP25672/IS61NVP25672  IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418  165 Pbga Boundary Scan Order (x 18) Signal Bump Bit # Name ID 1 MODE 1R 2 NC 6N 3 NC 11P 4 A 8P 5 A 8R 6 A 9R 7 A 9P 8 A 10P 9 A 10R 10 A 11R 11 ZZ 11H 12 NC 11N 13 NC 11M 14 NC 11L 15 NC 11K 16 NC 11J 17 DQa 10M 18 DQa 10L 19 DQa 10K 20 DQa 10J Bit # 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Signal Bump Name ID Bit # DQa 11G 41 DQa 11F 42 DQa 11E 43 DQa 11D 44 DQa 11C 45 NC 10F 46 NC 10E 47 NC 10D 48 NC 10G 49 A 11A 50 A 10A 51 A 10B 52 A 9A 53 A 9B 54 ADV 8A 55 OE 8B 56 CKE 7A 57 WE 7B 58 CLK 6B 59 NC 11B 60 Integrated Silicon Solution, Inc. — www.issi.com Rev.  O 09/19/2011 Signal Name NC CE2 BWa NC BWb NC CE2 CE A A NC NC NC NC NC NC DQb DQb DQb DQb Bump ID 1A 6A 5B 5A 4A 4B 3B 3A 2A 2B 1B 1C 1D 1E 1F 1G 2D 2E 2F 2G Bit # 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 Signal Name DQb DQb DQb DQb DQb NC NC NC NC A A A A A1 A0 Bump ID 1J 1K 1L 1M 1N 2K 2L 2M 2J 3P 3R 4R 4P 6P 6R 31 IS61NLP25672/IS61NVP25672  IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418  ORDERING INFORMATION (3.3V core/2.5V- 3.3V I/O) Commercial Range: 0°C to +70°C Configuration 256Kx72 512Kx36 1Mx18 Access Time Order Part Number Package 250 200 IS61NLP25672-250B1 IS61NLP25672-200B1 209 PBGA 209 PBGA 250 200 IS61NLP51236-250TQ IS61NLP51236-250TQL IS61NLP51236-250B3 IS61NLP51236-200TQ IS61NLP51236-200B3 100 TQFP 100 TQFP, Lead-free 165 PBGA 100 TQFP 165 PBGA 250 200 IS61NLP102418-250TQ IS61NLP102418-250B3 IS61NLP102418-200TQ IS61NLP102418-200B3 100 TQFP 165 PBGA 100 TQFP 165 PBGA Order Part Number Package 250 200 IS61NLP25672-250B1I IS61NLP25672-200B1I IS61NLP25672-200B1LI 209 PBGA 209 PBGA 209 PBGA, Lead-free 250 200 IS61NLP51236-250TQI IS61NLP51236-250TQLI IS61NLP51236-250B3I IS61NLP51236-200TQI IS61NLP51236-200TQLI IS61NLP51236-200B3I IS61NLP51236-200B3LI 100 TQFP 100 TQFP, Lead-free 165 PBGA 100 TQFP 100 TQFP, Lead-free 165 PBGA 165 PBGA, Lead-free 250 200 IS61NLP102418-250TQI IS61NLP102418-250B3I IS61NLP102418-200TQI IS61NLP102418-200TQLI IS61NLP102418-200B3I IS61NLP102418-200B3LI IS61NLP102418-200B2LI 100 TQFP 165 PBGA 100 TQFP 100 TQFP, Lead-free 165 PBGA 165 PBGA, Lead-free 119 PBGA, Lead-free Industrial Range: -40°C to +85°C 32 Configuration 256Kx72 512Kx36 1Mx18 Access Time Integrated Silicon Solution, Inc. — www.issi.com Rev. O 09/19/2011 IS61NLP25672/IS61NVP25672  IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418  ORDERING INFORMATION (2.5V core/2.5V I/O) Commercial Range: 0°C to +70°C Configuration 256Kx72 512Kx36 1Mx18 Access Time Order Part Number Package 250 200 IS61NVP25672-250B1 IS61NVP25672-200B1 209 PBGA 209 PBGA 250 200 IS61NVP51236-250TQ IS61NVP51236-250B3 IS61NVP51236-200TQ IS61NVP51236-200B3 100 TQFP 165 PBGA 100 TQFP 165 PBGA 250 200 IS61NVP102418-250TQ IS61NVP102418-250B3 IS61NVP102418-200TQ IS61NVP102418-200B3 100 TQFP 165 PBGA 100 TQFP 165 PBGA Industrial Range: -40°C to +85°C Configuration 256Kx72 512Kx36 1Mx18 Access Time Order Part Number Package 250 200 IS61NVP25672-250B1I IS61NVP25672-200B1I 209 PBGA 209 PBGA 250 200 IS61NVP51236-250TQI IS61NVP51236-250B3I IS61NVP51236-200TQI IS61NVP51236-200TQLI IS61NVP51236-200B3I 100 TQFP 165 PBGA 100 TQFP 100 TQFP, Lead-free 165 PBGA 250 200 IS61NVP102418-250TQI IS61NVP102418-250B3I IS61NVP102418-200TQI IS61NVP102418-200TQLI IS61NVP102418-200B3I IS61NVP102418-200B2LI 100 TQFP 165 PBGA 100 TQFP 100 TQFP, Lead-free 165 PBGA 119 PBGA, Lead-free Integrated Silicon Solution, Inc. — www.issi.com Rev.  O 09/19/2011 33 IS61NLP25672/IS61NVP25672  IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418  34 Integrated Silicon Solution, Inc. — www.issi.com Rev. O 09/19/2011 Integrated Silicon Solution, Inc. — www.issi.com Rev.  O 09/19/2011 Package Outline 1. CONTROLLING DIMENSION : MM . NOTE : 08/28/2008 IS61NLP25672/IS61NVP25672  IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418  35 12/10/2007 Package Outline 1. Controlling dimension : mm NOTE : IS61NLP25672/IS61NVP25672  IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418  36 Integrated Silicon Solution, Inc. — www.issi.com Rev. O 09/19/2011 Integrated Silicon Solution, Inc. — www.issi.com Rev.  O 09/19/2011 1. CONTROLLING DIMENSION : MM . 2. Reference document : JEDEC MS-028 NOTE : Package Outline 10/02/2008 IS61NLP25672/IS61NVP25672  IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418  37