IS61NVP12818A

IS61NLP6432A IS61NLP6436A/IS61NVP6436A IS61NLP12818A/IS61NVP12818A 64K x 32, 64K x 36, and 128K x 18 2Mb, PIPELINE 'NO WAIT' STATE BUS SRAM ISSI SEPTEMBER 2005 ® PRELIMINARY INFORMATION FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control using MODE input • Three chip enables for simple depth expansion and address pipelining • Power Down mode • Common data inputs and data outputs • CKE pin to enable clock and suspend operation • JEDEC 100-pin TQFP package • Power supply: NVP: VDD 2.5V (± 5%), VDDQ 2.5V (± 5%) NLP: VDD 3.3V (± 5%), VDDQ 3.3V/2.5V (± 5%) • Industrial temperature available • Lead-free available DESCRIPTION The 2 Meg 'NLP/NVP' product family feature high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, 'no wait' state, device for networking and communications applications. They are organized as 64K words by 32 bits, 64K words by 36 bits, and 128K words by 18 bits, fabricated with ISSI's advanced CMOS technology. Incorporating a 'no wait' state feature, wait cycles are eliminated when the bus switches from read to write, or write to read. This device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers are controlled by a positive-edge-triggered single clock input. Operations may be suspended and all synchronous inputs ignored when Clock Enable, CKE is HIGH. In this state the internal device will hold their previous values. All Read, Write and Deselect cycles are initiated by the ADV input. When the ADV is HIGH the internal burst counter is incremented. New external addresses can be loaded when ADV is LOW. Write cycles are internally self-timed and are initiated by the rising edge of the clock inputs and when WE is LOW. Separate byte enables allow individual bytes to be written. A burst mode pin (MODE) defines the order of the burst sequence. When tied HIGH, the interleaved burst sequence is selected. When tied LOW, the linear burst sequence is selected. FAST ACCESS TIME Symbol tKQ tKC Parameter Clock Access Time Cycle Time Frequency -250 2.6 4 250 -200 3.1 5 200 Units ns ns MHz Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. 00A 08/31/05 1 IS61NLP6432A IS61NLP6436A/IS61NVP6436A IS61NLP12818A/IS61NVP12818A BLOCK DIAGRAM ISSI A2-A15 or A2-A16 64Kx32; 64Kx36; 128Kx18 MEMORY ARRAY ® x 32/x 36: A [0:15] or x 18: A [0:16] ADDRESS REGISTER MODE A0-A1 BURST ADDRESS COUNTER A'0-A'1 K DATA-IN REGISTER CLK CKE CE CE2 CE2 ADV WE BWX Ÿ OE ZZ CONTROL LOGIC K WRITE ADDRESS REGISTER WRITE ADDRESS REGISTER K DATA-IN REGISTER } CONTROL REGISTER CONTROL LOGIC K OUTPUT REGISTER BUFFER (X=a,b,c,d or a,b) 32, 36 or 18 DQx/DQPx 2 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. 00A 08/31/05 IS61NLP6432A IS61NLP6436A/IS61NVP6436A IS61NLP12818A/IS61NVP12818A PIN CONFIGURATION 100-Pin TQFP ISSI BWd BWc BWb BWa CKE ® BWd BWc BWb BWa CKE OE ADV NC OE ADV NC CE2 CE2 VDD Vss CE2 CE2 VDD Vss CLK WE CLK WE NC NC CE CE A A A A A A DQPc DQc DQc VDDQ Vss DQc DQc DQc DQc Vss VDDQ DQc DQc NC VDD NC Vss DQd DQd VDDQ Vss DQd DQd DQd DQd Vss VDDQ DQd DQd DQPd 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 1 79 2 78 3 77 4 76 5 75 6 74 7 73 8 72 9 71 10 70 11 69 12 68 13 67 14 66 15 65 16 64 17 63 18 62 19 61 20 60 21 59 22 58 23 57 24 56 25 55 26 54 27 53 28 52 29 51 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 A A A A NC NC A1 A0 Vss MODE NC A A A A A A VDD NC NC DQPb DQb DQb VDDQ Vss DQb DQb DQb DQb Vss VDDQ DQb DQb Vss NC VDD ZZ DQa DQa VDDQ Vss DQa DQa DQa DQa Vss VDDQ DQa DQa DQPa NC DQc DQc VDDQ Vss DQc DQc DQc DQc Vss VDDQ DQc DQc NC VDD NC Vss DQd DQd VDDQ Vss DQd DQd DQd DQd Vss VDDQ DQd DQd NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 1 79 2 78 3 77 4 76 5 75 6 74 7 73 8 72 9 71 10 70 11 69 12 68 13 67 14 66 15 65 16 64 17 63 18 62 19 61 20 60 21 59 22 58 23 57 24 56 25 55 26 54 27 53 28 52 29 51 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 A A A A NC NC A1 A0 MODE Vss NC A A A A A VDD NC A NC A A NC DQb DQb VDDQ Vss DQb DQb DQb DQb Vss VDDQ DQb DQb Vss NC VDD ZZ DQa DQa VDDQ Vss DQa DQa DQa DQa Vss VDDQ DQa DQa NC 64K x 36 PIN DESCRIPTIONS A0, A1 Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus. Synchronous Address Inputs Synchronous Clock Synchronous Burst Address Advance Synchronous Byte Write Enable Write Enable Clock Enable Ground for Core Not Connected 64K x 32 CE, CE2, CE2 Synchronous Chip Enable OE DQa-DQd DQPa-DQPd MODE VDD VSS VDDQ ZZ Output Enable Synchronous Data Input/Output Parity Data I/O Burst Sequence Selection +3.3V/2.5V Power Supply Ground for output Buffer Isolated Output Buffer Supply: +3.3V/2.5V Snooze Enable A CLK ADV BWa-BWd WE CKE Vss NC Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. 00A 08/31/05 3 IS61NLP6432A IS61NLP6436A/IS61NVP6436A IS61NLP12818A/IS61NVP12818A PIN CONFIGURATION 100-Pin TQFP ISSI ® NC BWb BWa CKE ADV NC CE2 CE2 VDD Vss CLK WE OE NC NC CE A A NC NC NC VDDQ Vss NC NC DQb DQb Vss VDDQ DQb DQb NC VDD NC Vss DQb DQb VDDQ Vss DQb DQb DQPb NC Vss VDDQ NC NC NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 1 79 2 78 3 77 4 76 5 75 6 74 7 73 8 72 9 71 10 70 11 69 12 68 13 67 14 66 15 65 16 64 17 63 18 62 19 61 20 60 21 59 22 58 23 57 24 56 25 55 26 54 27 53 28 52 29 51 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 NC NC A MODE Vss VDD NC NC NC A A A A A1 A0 A A A A A A A A NC NC VDDQ Vss NC DQPa DQa DQa Vss VDDQ DQa DQa Vss NC VDD ZZ DQa DQa VDDQ Vss DQa DQa NC NC Vss VDDQ NC NC NC 128K x 18 PIN DESCRIPTIONS A0, A1 Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus. Synchronous Address Inputs Synchronous Clock Synchronous Burst Address Advance Synchronous Byte Write Enable Write Enable Clock Enable Ground for Core Not Connected CE, CE2, CE2 Synchronous Chip Enable OE DQa-DQd DQPa-DQPd MODE VDD VSS VDDQ ZZ Output Enable Synchronous Data Input/Output Parity Data I/O Burst Sequence Selection +3.3V/2.5V Power Supply Ground for output Buffer Isolated Output Buffer Supply: +3.3V/2.5V Snooze Enable A CLK ADV BWa-BWd WE CKE Vss NC 4 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. 00A 08/31/05 IS61NLP6432A IS61NLP6436A/IS61NVP6436A IS61NLP12818A/IS61NVP12818A STATE DIAGRAM READ BEGIN READ WRITE DS READ DS WRITE BEGIN WRITE ISSI WRITE ® READ READ BURST DS DESELECT BURST BURST WRITE DS BURST READ WRITE DS BURST WRITE BURST BURST READ SYNCHRONOUS TRUTH TABLE(1) Operation Not Selected Not Selected Not Selected Not Selected Continue Begin Burst Read Continue Burst Read NOP/Dummy Read Dummy Read Begin Burst Write Continue Burst Write NOP/Write Abort Write Abort Ignore Clock Notes: 1. 2. 3. 4. Address Used N/A N/A N/A N/A External Address Next Address External Address Next Address External Address Next Address N/A Next Address Current Address CE H X X X L X L X L X L X X CE2 X L X X H X H X H X H X X CE2 X X H X L X L X L X L X X ADV L L L H L H L H L H L H X WE X X X X H X H X L X L X X BWx X X X X X X X X L L H H X OE X X X X L L H H X X X X X CKE L L L L L L L L L L L L H CLK ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ "X" means don't care. The rising edge of clock is symbolized by ↑ A continue deselect cycle can only be entered if a deselect cycle is executed first. WE = L means Write operation in Write Truth Table. WE = H means Read operation in Write Truth Table. 5. Operation finally depends on status of asynchronous pins (ZZ and OE). Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. 00A 08/31/05 5 IS61NLP6432A IS61NLP6436A/IS61NVP6436A IS61NLP12818A/IS61NVP12818A ASYNCHRONOUS TRUTH TABLE(1) Operation Sleep Mode Read Write Deselected Notes: ZZ H L L L L OE X L H X X I/O STATUS High-Z DQ High-Z Din, High-Z High-Z ISSI ® 1. X means "Don't Care". 2. For write cycles following read cycles, the output buffers must be disabled with OE, otherwise data bus contention will occur. 3. Sleep Mode means power Sleep Mode where stand-by current does not depend on cycle time. 4. Deselected means power Sleep Mode where stand-by current depends on cycle time. WRITE TRUTH TABLE (x18) Operation READ WRITE BYTE a WRITE BYTE b WRITE ALL BYTEs WRITE ABORT/NOP Notes: WE H L L L L BWa X L H L H BW b X H L L H 1. X means "Don't Care". 2. All inputs in this table must beet setup and hold time around the rising edge of CLK. 6 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. 00A 08/31/05 IS61NLP6432A IS61NLP6436A/IS61NVP6436A IS61NLP12818A/IS61NVP12818A WRITE TRUTH TABLE (x32/x36) Operation READ WRITE BYTE a WRITE BYTE b WRITE BYTE c WRITE BYTE d WRITE ALL BYTEs WRITE ABORT/NOP Notes: WE H L L L L L L BWa X L H H H L H BWb X H L H H L H BWc X H H L H L H BW d X H H H L L H ISSI ® 1. X means "Don't Care". 2. All inputs in this table must beet setup and hold time around the rising edge of CLK. INTERLEAVED BURST ADDRESS TABLE (MODE = VDD or NC) External Address A1 A0 00 01 10 11 1st Burst Address A1 A0 01 00 11 10 2nd Burst Address A1 A0 10 11 00 01 3rd Burst Address A1 A0 11 10 01 00 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. 00A 08/31/05 7 IS61NLP6432A IS61NLP6436A/IS61NVP6436A IS61NLP12818A/IS61NVP12818A LINEAR BURST ADDRESS TABLE (MODE = VSS) ISSI ® 0,0 A1', A0' = 1,1 0,1 1,0 ABSOLUTE MAXIMUM RATINGS(1) Symbol TSTG PD IOUT VIN, VOUT VIN Parameter Storage Temperature Power Dissipation Output Current (per I/O) Voltage Relative to VSS for I/O Pins Voltage Relative to VSS for for Address and Control Inputs Value –65 to +150 1.6 100 –0.5 to VDDQ + 0.3 –0.3 to 4.6 Unit °C W mA V V Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. This device contains circuity to protect the inputs against damage due to high static voltages or electric fields; however, precautions may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. 3. This device contains circuitry that will ensure the output devices are in High-Z at power up. OPERATING RANGE (IS61NLPx) Range Commercial Industrial Ambient Temperature 0°C to +70°C -40°C to +85°C VDD 3.3V ± 5% 3.3V ± 5% VDDQ 3.3V / 2.5V ± 5% 3.3V / 2.5V ± 5% OPERATING RANGE (IS61NVPx) Range Commercial Industrial 8 Ambient Temperature 0°C to +70°C -40°C to +85°C VDD 2.5V ± 5% 2.5V ± 5% VDDQ 2.5V ± 5% 2.5V ± 5% Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. 00A 08/31/05 IS61NLP6432A IS61NLP6436A/IS61NVP6436A IS61NLP12818A/IS61NVP12818A DC ELECTRICAL CHARACTERISTICS (Over Operating Range) 3.3V Symbol VOH VOL VIH VIL ILI ILO Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current Output Leakage Current VSS ≤ VIN ≤ VDD(1) VSS ≤ VOUT ≤ VDDQ, OE = VIH Test Conditions IOH = –4.0 mA (3.3V) IOH = –1.0 mA (2.5V) IOL = 8.0 mA (3.3V) IOL = 1.0 mA (2.5V) Min. 2.4 — 2.0 –0.3 –5 –5 Max. — 0.4 VDD + 0.3 0.8 5 5 Min. 2.0 — 1.7 –0.3 –5 –5 2.5V ISSI Max. — 0.4 VDD + 0.3 0.7 5 5 Unit V V V V µA µA ® POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) -250 MAX x18 x32/x36 225 250 225 250 -200 MAX x18 x32/x36 200 210 200 210 Symbol Parameter ICC AC Operating Supply Current Test Conditions Temp. range Unit mA Device Selected, Com. OE = VIH, ZZ ≤ VIL, Ind. All Inputs ≤ 0.2V or ≥ VDD – 0.2V, Cycle Time ≥ tKC min. Device Deselected, VDD = Max., All Inputs ≤ VIL or ≥ VIH, ZZ ≤ VIL, f = Max. Device Deselected, VDD = Max., VIN ≤ VSS + 0.2V or ≥VDD – 0.2V f=0 ZZ>VIH Com. Ind. ISB Standby Current TTL Input 90 100 90 100 90 100 90 100 mA ISBI Standby Current CMOS Input Com. Ind. typ.(2) Com. Ind. typ.(2) 70 75 40 30 35 20 70 75 70 75 40 70 75 mA ISB2 Sleep Mode 30 35 30 35 20 30 35 mA Note: 1. MODE pin has an internal pullup and should be tied to VDD or VSS. It exhibits ±100µA maximum leakage current when tied to ≤ VSS + 0.2V or ≥ VDD – 0.2V. 2. Typical values are measured at VDD = 3.3V, TA = 25oC and not 100% tested. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. 00A 08/31/05 9 IS61NLP6432A IS61NLP6436A/IS61NVP6436A IS61NLP12818A/IS61NVP12818A CAPACITANCE(1,2) Symbol CIN COUT Parameter Input Capacitance Input/Output Capacitance Conditions VIN = 0V VOUT = 0V Max. 6 8 Unit pF pF ISSI ® Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25°C, f = 1 MHz, VDD = 3.3V. 3.3V I/O AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0V to 3.0V 1.5 ns 1.5V See Figures 1 and 2 3.3V I/O OUTPUT LOAD EQUIVALENT 317 Ω Zo= 50Ω OUTPUT +3.3V OUTPUT 50Ω 1.5V 351 Ω 5 pF Including jig and scope Figure 1 Figure 2 10 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. 00A 08/31/05 IS61NLP6432A IS61NLP6436A/IS61NVP6436A IS61NLP12818A/IS61NVP12818A 2.5V I/O AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0V to 2.5V 1.5 ns 1.25V See Figures 3 and 4 ISSI ® 2.5V I/O OUTPUT LOAD EQUIVALENT 1,667 Ω ZO = 50Ω OUTPUT +2.5V OUTPUT 50Ω 1,538 Ω 1.25V 5 pF Including jig and scope Figure 3 Figure 4 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. 00A 08/31/05 11 IS61NLP6432A IS61NLP6436A/IS61NVP6436A IS61NLP12818A/IS61NVP12818A READ/WRITE CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) Symbol fmax tKC tKH tKL tKQ tKQX (2) (2,3) ISSI -250 Min. Max. — 4.0 1.7 1.7 — 0.8 0.8 — — 0 — 1.2 1.2 1.2 1.2 1.2 1.2 0.3 0.3 0.3 0.3 0.3 0.3 — — 250 — — — 2.6 — — 2.6 2.8 — 2.6 — — — — — — — — — — — — 2 2 -200 Min. Max. — 5 2 2 — 1.5 1 — — 0 — 1.4 1.4 1.4 1.4 1.4 1.4 0.4 0.4 0.4 0.4 0.4 0.4 — — 200 — — — 3.1 — — 3.0 3.1 — 3.0 — — — — — — — — — — — — 2 2 Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns cyc cyc ® Parameter Clock Frequency Cycle Time Clock High Time Clock Low Time Clock Access Time Clock High to Output Invalid Clock High to Output Low-Z Clock High to Output High-Z Output Enable to Output Valid Output Enable to Output Low-Z Output Disable to Output High-Z Address Setup Time Read/Write Setup Time Chip Enable Setup Time Clock Enable Setup Time Address Advance Setup Time Data Setup Time Address Hold Time Clock Enable Hold Time Write Hold Time Chip Enable Hold Time Address Advance Hold Time Data Hold Time ZZ High to Power Down ZZ Low to Power Down tKQLZ tOEQ tOELZ tAS tWS tCES tSE tKQHZ(2,3) (2,3) (2,3) tOEHZ tADVS tDS tAH tHE tWH tCEH tADVH tDH tPDS tPUS Notes: 1. Configuration signal MODE is static and must not change during normal operation. 2. Guaranteed but not 100% tested. This parameter is periodically sampled. 3. Tested with load in Figure 2. 12 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. 00A 08/31/05 IS61NLP6432A IS61NLP6436A/IS61NVP6436A IS61NLP12818A/IS61NVP12818A SLEEP MODE ELECTRICAL CHARACTERISTICS Symbol ISB2 tPDS tPUS tZZI tRZZI Parameter Current during SLEEP MODE ZZ active to input ignored ZZ inactive to input sampled ZZ active to SLEEP current ZZ inactive to exit SLEEP current Conditions ZZ ≥ VIH 2 2 2 0 Min. Max. 35 ISSI Unit mA cycle cycle cycle ns ® SLEEP MODE TIMING CLK tPDS ZZ setup cycle tPUS ZZ recovery cycle ZZ tZZI Isupply ISB2 tRZZI All Inputs (except ZZ) Deselect or Read Only Deselect or Read Only Normal operation cycle Outputs (Q) High-Z Don't Care Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. 00A 08/31/05 13 IS61NLP6432A IS61NLP6436A/IS61NVP6436A IS61NLP12818A/IS61NVP12818A READ CYCLE TIMING ISSI ® tKH tKL CLK tADVS tADVH ADV tKC tAS tAH Address A1 A2 A3 tWS tWH WRITE tSE tHE CKE tCES tCEH CE OE tOEQ tOEHZ Data Out Q1-1 tOEHZ tDS Q2-1 tKQ tKQHZ Q2-2 Q2-3 Q2-4 Q3-1 Q3-2 Q3-3 Q3-4 NOTES: WRITE = L means WE = L and BWx = L WE = L and BWX = L CE = L means CE1 = L, CE2 = H and CE2 = L CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L Don't Care Undefined 14 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. 00A 08/31/05 IS61NLP6432A IS61NLP6436A/IS61NVP6436A IS61NLP12818A/IS61NVP12818A WRITE CYCLE TIMING tKH tKL CLK ISSI ® tKC ADV Address A1 A2 A3 WRITE tSE tHE CKE CE OE tDS Data In D1-1 D2-1 D2-2 D2-3 D2-4 D3-1 D3-2 tDH D3-3 D3-4 tOEHZ Data Out Q0-3 Q0-4 NOTES: WRITE = L means WE = L and BWx = L WE = L and BWX = L CE = L means CE1 = L, CE2 = H and CE2 = L CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L Don't Care Undefined Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. 00A 08/31/05 15 IS61NLP6432A IS61NLP6436A/IS61NVP6436A IS61NLP12818A/IS61NVP12818A SINGLE READ/WRITE CYCLE TIMING tKH tKL ISSI tKC ® CLK tSE tHE CKE Address A1 A2 A3 A4 A5 A6 A7 A8 A9 WRITE CE ADV OE tOEQ tOELZ Data Out Q1 tDS tDH Q3 Q4 Q6 Q7 Data In D2 NOTES: WRITE = L means WE = L and BWx = L CE = L means CE1 = L, CE2 = H and CE2 = L CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L D5 Don't Care Undefined 16 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. 00A 08/31/05 IS61NLP6432A IS61NLP6436A/IS61NVP6436A IS61NLP12818A/IS61NVP12818A CKE OPERATION TIMING tKH tKL ISSI ® CLK tSE tHE tKC CKE Address A1 A2 A3 A4 A5 A6 WRITE CE ADV OE tKQ tKQLZ tKQHZ Data Out Q1 tDS tDH Q3 Q4 Data In NOTES: WRITE = L means WE = L and BWx = L CE = L means CE1 = L, CE2 = H and CE2 = L CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L D2 Don't Care Undefined Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. 00A 08/31/05 17 IS61NLP6432A IS61NLP6436A/IS61NVP6436A IS61NLP12818A/IS61NVP12818A CE OPERATION TIMING tKH tKL ISSI tKC ® CLK tSE tHE CKE Address A1 A2 A3 A4 A5 WRITE CE ADV OE tOEQ tOELZ tKQHZ tKQ tKQLZ Data Out Q1 Q2 tDS tDH Q4 Data In D3 NOTES: WRITE = L means WE = L and BWx = L CE = L means CE1 = L, CE2 = H and CE2 = L CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L D5 Don't Care Undefined 18 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. 00A 08/31/05 IS61NLP6432A IS61NLP6436A/IS61NVP6436A IS61NLP12818A/IS61NVP12818A ORDERING INFORMATION (VDD = 3.3V/VDDQ = 2.5V/3.3V) Commercial Range: 0°C to +70°C Access Time 250 200 250 200 250 200 Order Part Number 64Kx32 IS61NLP6432A-250TQ IS61NLP6432A-200TQ 64Kx36 IS61NLP6436A-250TQ IS61NLP6436A-200TQ 128Kx18 IS61NLP12818A-250TQ IS61NLP12818A-200TQ 100 TQFP 100 TQFP 100 TQFP 100 TQFP 100 TQFP 100 TQFP Package ISSI ® Industrial Range: -40°C to +85°C Access Time 250 200 200 250 200 250 200 200 Order Part Number 64Kx32 IS61NLP6432A-250TQI IS61NLP6432A-200TQI IS61NLP6432A-200TQLI 64Kx36 IS61NLP6436A-250TQI IS61NLP6436A-200TQI 128Kx18 IS61NLP12818A-250TQI IS61NLP12818A-200TQI IS61NLP12818A-200TQLI 100 TQFP 100 TQFP 100 TQFP, Lead-free 100 TQFP 100 TQFP 100 TQFP 100 TQFP 100 TQFP, Lead-free Package Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. 00A 08/31/05 19 IS61NLP6432A IS61NLP6436A/IS61NVP6436A IS61NLP12818A/IS61NVP12818A ORDERING INFORMATION (VDD = 2.5V/VDDQ = 2.5V) Commercial Range: 0°C to +70°C Access Time 250 200 250 200 Order Part Number 64Kx36 IS61NVP6436A-250TQ IS61NVP6436A-200TQ 128Kx18 IS61NVP12818A-250TQ IS61NVP12818A-200TQ 100 TQFP 100 TQFP 100 TQFP 100 TQFP Package ISSI ® Industrial Range: -40°C to +85°C Access Time 250 200 250 200 Order Part Number 64Kx36 IS61NVP6436A-250TQI IS61NVP6436A-200TQI 128Kx18 IS61NVP12818A-250TQI IS61NVP12818A-200TQI 100 TQFP 100 TQFP 100 TQFP 100 TQFP Package 20 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. 00A 08/31/05 PACKAGING INFORMATION TQFP (Thin Quad Flat Pack Package) Package Code: TQ ISSI D D1 ® E E1 N 1 C e SEATING PLANE L1 L A2 A1 b A Millimeters Symbol Min Max Ref. Std. No. Leads (N) 100 A — 1.60 — 0.063 A1 0.05 0.15 0.002 0.006 A2 1.35 1.45 0.053 0.057 b 0.22 0.38 0.009 0.015 D 21.90 22.10 0.862 0.870 D1 19.90 20.10 0.783 0.791 E 15.90 16.10 0.626 0.634 E1 13.90 14.10 0.547 0.555 e 0.65 BSC 0.026 BSC L 0.45 0.75 0.018 0.030 L1 1.00 REF. 0.039 REF. C 0o 7o 0o 7o Thin Quad Flat Pack (TQ) Inches Millimeters Min Max Min Max 128 — 1.60 0.05 0.15 1.35 1.45 0.17 0.27 21.80 22.20 19.90 20.10 15.80 16.20 13.90 14.10 0.50 BSC 0.45 0.75 1.00 REF. 0o 7o Inches Min Max — 0.063 0.002 0.006 0.053 0.057 0.007 0.011 0.858 0.874 0.783 0.791 0.622 0.638 0.547 0.555 0.020 BSC 0.018 0.030 0.039 REF. 0o 7o Notes: 1. All dimensioning and tolerancing conforms to ANSI Y14.5M-1982. 2. Dimensions D1 and E1 do not include mold protrusions. Allowable protrusion is 0.25 mm per side. D1 and E1 do include mold mismatch and are determined at datum plane -H-. 3. Controlling dimension: millimeters. Integrated Silicon Solution, Inc. — 1-800-379-4774 PK13197LQ Rev. D 05/08/03