IS61NVP25618A

IS61NLP12832B IS61NLP12836B/IS61NVP12836B IS61NLP25618A/IS61NVP25618A 128K x 32, 128K x 36, and 256K x 18 4Mb, PIPELINE 'NO WAIT' STATE BUS SRAM SEPTEMBER 2007 FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control DESCRIPTION The 4 Meg 'NLP/NVP' product family feature high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, 'no wait' state, device for networking and communications applications. They are organized as 128K words by 32 bits, 128K words by 36 bits, and 256K words by 18 bits, fabricated with ISSI's advanced CMOS technology. Incorporating a 'no wait' state feature, wait cycles are eliminated when the bus switches from read to write, or write to read. This device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers are controlled by a positive-edge-triggered single clock input. Operations may be suspended and all synchronous inputs ignored when Clock Enable, CKE is HIGH. In this state the internal device will hold their previous values. All Read, Write and Deselect cycles are initiated by the ADV input. When the ADV is HIGH the internal burst counter is incremented. New external addresses can be loaded when ADV is LOW. Write cycles are internally self-timed and are initiated by the rising edge of the clock inputs and when WE is LOW. Separate byte enables allow individual bytes to be written. A burst mode pin (MODE) defines the order of the burst sequence. When tied HIGH, the interleaved burst sequence is selected. When tied LOW, the linear burst sequence is selected. • Interleaved or linear burst sequence control using MODE input • Three chip enables for simple depth expansion and address pipelining • Power Down mode • Common data inputs and data outputs • CKE pin to enable clock and suspend operation • JEDEC 100-pin TQFP, 165-ball PBGA and 119ball PBGA packages • Power supply: NVP: Vdd 2.5V (± 5%), Vddq 2.5V (± 5%) NLP: Vdd 3.3V (± 5%), Vddq 3.3V/2.5V (± 5%) • Industrial temperature available • Lead-free available FAST ACCESS TIME Symbol tkq tkc Parameter Clock Access Time Cycle Time Frequency -250 2.6 4 250 -200 3.1 5 200 Units ns ns MHz Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — www.issi.com Rev. D 09/10/07 1 IS61NLP12832B IS61NLP12836B/IS61NVP12836B IS61NLP25618A/IS61NVP25618A BLOCK DIAGRAM x 32/x 36: A [0:16] or x 18: A [0:17] ADDRESS REGISTER A2-A16 or A2-A17 128Kx32; 128Kx36; 256Kx18 MEMORY ARRAY K DATA-IN REGISTER MODE A0-A1 BURST ADDRESS COUNTER A'0-A'1 CLK CKE CONTROL LOGIC K WRITE ADDRESS REGISTER WRITE ADDRESS REGISTER K DATA-IN REGISTER CE CE2 CE2 ADV WE BWX Ÿ OE ZZ DQx/DQPx } CONTROL REGISTER CONTROL LOGIC K OUTPUT REGISTER BUFFER (X=a,b,c,d or a,b) 32, 36 or 18 2 Integrated Silicon Solution, Inc. — www.issi.com Rev. D 09/10/07 IS61NLP12832B IS61NLP12836B/IS61NVP12836B IS61NLP25618A/IS61NVP25618A 165-Ball, 13 mm x 15mm BGA 1 mm Ball Pitch, 11 x 15 Ball Array Bottom View 119-Ball, 14 mm x 22 mm BGA 1 mm Ball Pitch, 7 x 17 Ball Array Bottom View Integrated Silicon Solution, Inc. — www.issi.com Rev. D 09/10/07 3 IS61NLP12832B IS61NLP12836B/IS61NVP12836B IS61NLP25618A/IS61NVP25618A PIN CONFIgURATION — 128K x 36, 165-Ball PBgA (TOP VIEW) 1 2 3 4 5 6 7 A B C D E F G H J K L M N P R NC NC DQPc DQc DQc DQc DQc NC DQd DQd DQd DQd DQPd NC MODE A A NC DQc DQc DQc DQc NC DQd DQd DQd DQd NC NC NC CE CE2 Vddq Vddq Vddq Vddq Vddq NC Vddq Vddq Vddq Vddq Vddq A A BWc BWd VSS Vdd Vdd Vdd Vdd Vdd Vdd Vdd Vdd Vdd VSS A A BWb BWa VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC NC NC CE2 CLK VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC A1* A0* CKE WE VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC NC NC 8 9 NC NC Vddq Vddq Vddq Vddq Vddq NC Vddq Vddq Vddq Vddq Vddq A A 10 A A NC DQb DQb DQb DQb NC DQa DQa DQa DQa NC A A 11 NC NC DQPb DQb DQb DQb DQb ZZ DQa DQa DQa DQa DQPa NC A ADV OE VSS Vdd Vdd Vdd Vdd Vdd Vdd Vdd Vdd Vdd VSS A A Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired. PIN DESCRIPTIONS Symbol A A0, A1 ADV Pin Name Address Inputs Synchronous Burst Address Inputs Synchronous Burst Address Advance/ Load WE Synchronous Read/Write Control Input CLK Synchronous Clock CKE Clock Enable CE, CE2, CE2 Synchronous Chip Enable BWx (x=a-d) Synchronous Byte Write Inputs OE Output Enable ZZ Power Sleep Mode MODE VDD NC DQx DQPx VDDQ VSS Burst Sequence Selection 3.3V/2.5V Power Supply No Connect Data Inputs/Outputs Parity Data I/O Isolated output Power Supply 3.3V/2.5V Ground 4 Integrated Silicon Solution, Inc. — www.issi.com Rev. D 09/10/07 IS61NLP12832B IS61NLP12836B/IS61NVP12836B IS61NLP25618A/IS61NVP25618A 119-PIN PBgA PACKAgE CONFIGURATION 1 2 3 128K x 36 (TOP VIEW) 4 5 6 7 A B C D E F VDDQ NC NC DQc DQc VDDQ DQc DQc VDDQ DQd DQd VDDQ DQd DQd NC NC VDDQ A CE2 A DQPc DQc DQc DQc DQc VDD DQd DQd DQd DQd DQPd A NC NC A A A VSS VSS VSS BWc VSS NC VSS BWd VSS VSS VSS MODE A NC NC ADV VDD NC CE OE NC WE VDD CLK NC CKE A 1* A0* VDD A NC A A A Vss Vss Vss BWb Vss NC Vss BWa Vss Vss Vss NC A NC A CE2 A DQPb DQb DQb DQb DQb VDD DQa DQa DQa DQa DQPa A NC NC VDDQ NC NC DQb DQb VDDQ DQb DQb VDDQ DQa DQa VDDQ DQa DQa NC ZZ VDDQ G H J K L M N P R T U Note: A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired. PIN DESCRIPTIONS Symbol A A0, A1 ADV WE CLK CKE CE CE2 CE2 BWx (x=a-d) Pin Name Address Inputs Synchronous Burst Address Inputs Synchronous Burst Address Advance/ Load Synchronous Read/Write Control Input Synchronous Clock Clock Enable Synchronous Chip Select Synchronous Chip Select Synchronous Chip Select Synchronous Byte Write Inputs OE ZZ MODE Vdd VSS NC DQa-DQd DQPa-Pd Vddq Output Enable Power Sleep Mode Burst Sequence Selection Power Supply Ground No Connect Data Inputs/Outputs Parity Data I/O Output Power Supply Integrated Silicon Solution, Inc. — www.issi.com Rev. D 09/10/07 5 IS61NLP12832B IS61NLP12836B/IS61NVP12836B IS61NLP25618A/IS61NVP25618A 165-PIN PBgA PACKAgE CONFIGURATION 1 2 3 4 5 256K x 18 (TOP VIEW) 6 7 8 9 10 11 A B C D E F NC NC NC NC NC NC NC NC DQb DQb DQb DQb DQPb NC MODE A A NC DQb DQb DQb DQb CE CE2 VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A BWb NC Vss VDD VDD VDD VDD VDD VDD VDD VDD VDD Vss A A NC BWa Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss NC NC NC CE2 CLK Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss NC A1* A0* CKE WE Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss NC NC NC ADV OE Vss VDD VDD VDD VDD VDD VDD VDD VDD VDD Vss A A NC NC VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A A A NC NC NC NC NC NC DQa DQa DQa DQa NC A A A NC DQPa DQa DQa DQa DQa ZZ NC NC NC NC NC NC A G H J NC NC NC NC NC NC NC NC K L M N P R Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired. PIN DESCRIPTIONS Symbol A A0, A1 ADV Pin Name Address Inputs Synchronous Burst Address Inputs Synchronous Burst Address Advance/ Load WE Synchronous Read/Write Control Input CLK Synchronous Clock CKE Clock Enable CE, CE2, CE2 Synchronous Chip Enable BWx (x=a,b) Synchronous Byte Write Inputs OE Output Enable ZZ Power Sleep Mode MODE VDD NC DQx DQPx VDDQ VSS Burst Sequence Selection 3.3V/2.5V Power Supply No Connect Data Inputs/Outputs Parity Data I/O Isolated output Power Supply 3.3V/2.5V Ground 6 Integrated Silicon Solution, Inc. — www.issi.com Rev. D 09/10/07 IS61NLP12832B IS61NLP12836B/IS61NVP12836B IS61NLP25618A/IS61NVP25618A 119-PIN PBgA PACKAgE CONFIGURATION 1 2 3 256K x 18 (TOP VIEW) 4 5 6 7 A B C D E F VDDQ NC NC DQb NC VDDQ NC DQb VDDQ NC DQb VDDQ DQb NC NC NC VDDQ A CE2 A NC DQb NC DQb NC VDD DQb NC DQb NC DQPb A A NC A A A VSS VSS VSS BWb VSS NC VSS NC VSS VSS VSS MODE A NC NC ADV VDD NC CE OE NC WE VDD CLK NC CKE A 1* A0* VDD NC NC A A A Vss Vss Vss NC Vss NC Vss BWa Vss Vss Vss NC A NC A CE2 A DQPa NC DQa NC DQa VDD NC DQa NC DQa NC A A NC VDDQ NC NC NC DQa VDDQ DQa NC VDDQ DQa NC VDDQ NC DQa NC ZZ VDDQ G H J K L M N P R T U Note: A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired. PIN DESCRIPTIONS Symbol A A0, A1 ADV WE CLK CKE CE CE2 CE2 BWx (x=a,b) Pin Name Address Inputs Synchronous Burst Address Inputs Synchronous Burst Address Advance/ Load Synchronous Read/Write Control Input Synchronous Clock Clock Enable Synchronous Chip Select Synchronous Chip Select Synchronous Chip Select Synchronous Byte Write Inputs OE ZZ MODE Vdd VSS NC DQa-DQb DQPa-Pb Vddq Output Enable Power Sleep Mode Burst Sequence Selection Power Supply Ground No Connect Data Inputs/Outputs Parity Data I/O Output Power Supply Integrated Silicon Solution, Inc. — www.issi.com Rev. D 09/10/07 7 IS61NLP12832B IS61NLP12836B/IS61NVP12836B IS61NLP25618A/IS61NVP25618A PIN CONFIGURATION 100-Pin TQFP BWd BWc BWb BWa BWd BWc BWb BWa CKE CKE OE ADV NC OE ADV NC CE2 CE2 VDD Vss CE2 CE2 VDD Vss CLK WE CLK WE NC NC CE CE A A A A A A DQPc DQc DQc VDDQ Vss DQc DQc DQc DQc Vss VDDQ DQc DQc NC VDD NC Vss DQd DQd VDDQ Vss DQd DQd DQd DQd Vss VDDQ DQd DQd DQPd 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 10 71 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Vss A A A A A1 A0 NC NC MODE VDD NC NC A A A A A A A DQPb DQb DQb VDDQ Vss DQb DQb DQb DQb Vss VDDQ DQb DQb Vss NC VDD ZZ DQa DQa VDDQ Vss DQa DQa DQa DQa Vss VDDQ DQa DQa DQPa NC DQc DQc VDDQ Vss DQc DQc DQc DQc Vss VDDQ DQc DQc NC VDD NC Vss DQd DQd VDDQ Vss DQd DQd DQd DQd Vss VDDQ DQd DQd NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 10 71 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 MODE Vss A A A A A1 A0 NC NC VDD NC NC A A A A A A A A A NC DQb DQb VDDQ Vss DQb DQb DQb DQb Vss VDDQ DQb DQb Vss NC VDD ZZ DQa DQa VDDQ Vss DQa DQa DQa DQa Vss VDDQ DQa DQa NC 128K x 36 PIN DESCRIPTIONS A0, A1 Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus. Synchronous Address Inputs Synchronous Clock Synchronous Burst Address Advance Synchronous Byte Write Enable Write Enable Clock Enable Ground for Core Not Connected CE, CE2, CE2 OE DQa-DQd DQPa-DQPd MODE Vdd VSS Vddq ZZ 128K x 32 A CLK ADV BWa-BWd WE CKE Vss NC Synchronous Chip Enable Output Enable Synchronous Data Input/Output Parity Data I/O Burst Sequence Selection +3.3V/2.5V Power Supply Ground for output Buffer Isolated Output Buffer Supply: +3.3V/2.5V Snooze Enable 8 Integrated Silicon Solution, Inc. — www.issi.com Rev. D 09/10/07 IS61NLP12832B IS61NLP12836B/IS61NVP12836B IS61NLP25618A/IS61NVP25618A PIN CONFIGURATION 100-Pin TQFP NC BWb BWa CKE ADV NC CE2 CE2 VDD Vss CLK WE OE NC NC CE A A NC NC NC VDDQ Vss NC NC DQb DQb Vss VDDQ DQb DQb NC VDD NC Vss DQb DQb VDDQ Vss DQb DQb DQPb NC Vss VDDQ NC NC NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 10 71 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 VDD NC NC A A A A A MODE A1 A0 NC NC Vss A A A A A A A A A NC NC VDDQ Vss NC DQPa DQa DQa Vss VDDQ DQa DQa Vss NC VDD ZZ DQa DQa VDDQ Vss DQa DQa NC NC Vss VDDQ NC NC NC 256K x 18 PIN DESCRIPTIONS A0, A1 Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus. Synchronous Address Inputs Synchronous Clock Synchronous Burst Address Advance Synchronous Byte Write Enable Write Enable Clock Enable Ground for Core Not Connected CE, CE2, CE2 OE DQa-DQd DQPa-DQPd MODE Vdd VSS Vddq ZZ Synchronous Chip Enable Output Enable Synchronous Data Input/Output Parity Data I/O Burst Sequence Selection +3.3V/2.5V Power Supply Ground for output Buffer Isolated Output Buffer Supply: +3.3V/2.5V Snooze Enable A CLK ADV BWa-BWd WE CKE Vss NC Integrated Silicon Solution, Inc. — www.issi.com Rev. D 09/10/07 9 IS61NLP12832B IS61NLP12836B/IS61NVP12836B IS61NLP25618A/IS61NVP25618A STATE DIAGRAM READ BEGIN READ WRITE DS READ DS WRITE BEGIN WRITE READ WRITE READ BURST DS DS DESELECT BURST DS BURST WRITE BURST BURST READ WRITE READ BURST WRITE BURST SYNCHRONOUS TRUTH TABLE(1) Operation Not Selected Not Selected Not Selected Not Selected Continue Begin Burst Read Continue Burst Read NOP/Dummy Read Dummy Read Begin Burst Write Continue Burst Write NOP/Write Abort Write Abort Ignore Clock Notes: Address Used N/A N/A N/A N/A External Address Next Address External Address Next Address External Address Next Address N/A Next Address Current Address CE H X X X L X L X L X L X X CE2 X L X X H X H X H X H X X CE2 X X H X L X L X L X L X X ADV L L L H L H L H L H L H X WE X X X X H X H X L X L X X BWx X X X X X X X X L L H H X OE X X X X L L H H X X X X X CKE L L L L L L L L L L L L H CLK ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ 1. "X" means don't care. 2. The rising edge of clock is symbolized by ↑ 3. A continue deselect cycle can only be entered if a deselect cycle is executed first. 4. WE = L means Write operation in Write Truth Table. WE = H means Read operation in Write Truth Table. 5. Operation finally depends on status of asynchronous pins (ZZ and OE). 10 Integrated Silicon Solution, Inc. — www.issi.com Rev. D 09/10/07 IS61NLP12832B IS61NLP12836B/IS61NVP12836B IS61NLP25618A/IS61NVP25618A ASYNCHRONOUS TRUTH TABLE(1) Operation Sleep Mode Read Write Deselected Notes: ZZ H L L L L OE X L H X X I/O STATUS High-Z DQ High-Z Din, High-Z High-Z 1. X means "Don't Care". 2. For write cycles following read cycles, the output buffers must be disabled with OE, otherwise data bus contention will occur. 3. Sleep Mode means power Sleep Mode where stand-by current does not depend on cycle time. 4. Deselected means power Sleep Mode where stand-by current depends on cycle time. WRITE TRUTH TABLE (x18) Operation READ WRITE BYTE a WRITE BYTE b WRITE ALL BYTEs WRITE ABORT/NOP Notes: WE H L L L L BWa X L H L H BWb X H L L H 1. X means "Don't Care". 2. All inputs in this table must beet setup and hold time around the rising edge of CLK. Integrated Silicon Solution, Inc. — www.issi.com Rev. D 09/10/07 11 IS61NLP12832B IS61NLP12836B/IS61NVP12836B IS61NLP25618A/IS61NVP25618A WRITE TRUTH TABLE (x32/x36) Operation READ WRITE BYTE a WRITE BYTE b WRITE BYTE c WRITE BYTE d WRITE ALL BYTEs WRITE ABORT/NOP Notes: WE H L L L L L L BWa X L H H H L H BWb X H L H H L H BWc X H H L H L H BWd X H H H L L H 1. X means "Don't Care". 2. All inputs in this table must beet setup and hold time around the rising edge of CLK. INTERLEAVED BURST ADDRESS TABLE (MODE = Vdd or NC) External Address A1 A0 00 01 10 11 1st Burst Address A1 A0 01 00 11 10 2nd Burst Address A1 A0 10 11 00 01 3rd Burst Address A1 A0 11 10 01 00 12 Integrated Silicon Solution, Inc. — www.issi.com Rev. D 09/10/07 IS61NLP12832B IS61NLP12836B/IS61NVP12836B IS61NLP25618A/IS61NVP25618A LINEAR BURST ADDRESS TABLE (MODE = VSS) 0,0 A1', A0' = 1,1 0,1 1,0 ABSOLUTE MAXIMUM RATINgS(1) Symbol TSTG Pd IouT VIn, VouT VIn Parameter Storage Temperature Power Dissipation Output Current (per I/O) Voltage Relative to VSS for I/O Pins Voltage Relative to VSS for for Address and Control Inputs Value –65 to +150 1.6 100 –0.5 to Vddq + 0.5 –0.5 to 4.6 Unit °C W mA V V Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. This device contains circuity to protect the inputs against damage due to high static voltages or electric fields; however, precautions may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. 3. This device contains circuitry that will ensure the output devices are in High-Z at power up. OPERATINg RANgE (IS61NLPx) Range Commercial Industrial Ambient Temperature 0°C to +70°C -40°C to +85°C VDD 3.3V ± 5% 3.3V ± 5% VDDq 3.3V / 2.5V ± 5% 3.3V / 2.5V ± 5% OPERATINg RANgE (IS61NVPx) Range Commercial Industrial Ambient Temperature 0°C to +70°C -40°C to +85°C VDD 2.5V ± 5% 2.5V ± 5% VDDq 2.5V ± 5% 2.5V ± 5% Integrated Silicon Solution, Inc. — www.issi.com Rev. D 09/10/07 13 IS61NLP12832B IS61NLP12836B/IS61NVP12836B IS61NLP25618A/IS61NVP25618A DC ELECTRICAL CHARACTERISTICS (Over Operating Range) 3.3V Symbol Voh Vol VIh(1) VIl(1) IlI Ilo Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current Output Leakage Current Test Conditions Ioh = –4.0 mA (3.3V) Ioh = –1.0 mA (2.5V) Iol = 8.0 mA (3.3V) Iol = 1.0 mA (2.5V) VSS ≤ VIn ≤ Vdd(1) VSS ≤ VouT ≤ Vddq, OE = VIh Min. 2.4 — 2.0 –0.3 –5 –5 Max. — 0.4 Vdd + 0.3 0.8 5 5 Min. 2.0 — 1.7 –0.3 –5 –5 2.5V Max. — 0.4 Vdd + 0.3 0.7 5 5 Unit V V V V µA µA Note: 1. Overshoot: VIh (AC) < Vdd + 2.0V (Pulse width less than tkc/2). Undershoot: VIl (AC) > -2V (Pulse width less than tkc/2). POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) Symbol Icc ISb Parameter AC Operating Supply Current Standby Current TTL Input Test Conditions Temp. range Device Selected, Com. OE = VIh, ZZ ≤ VIl, Ind. All Inputs ≤ 0.2V or ≥ Vdd – 0.2V, Cycle Time ≥ tkc min. Device Deselected, Com. Vdd = Max., Ind. All Inputs ≤ VIl or ≥ VIh, ZZ ≤ VIl, f = Max. Device Deselected, Com. Vdd = Max., Ind. VIn ≤ VSS + 0.2V or ≥Vdd – 0.2V typ.(2) f = 0 ZZ>VIh Com. Ind. typ.(2) -250 MAX x18 x32/x36 225 225 250 250 -200 MAX x18 x32/x36 200 200 210 210 Unit mA 90 90 100 100 90 90 100 100 mA ISbI ISb2 Standby Current cMoS Input Sleep Mode 70 70 75 75 40 30 30 35 35 20 70 70 75 75 mA 30 30 35 35 mA Note: 1. MODE pin has an internal pullup and should be tied to Vdd or VSS. It exhibits ±100µA maximum leakage current when tied to ≤ VSS + 0.2V or ≥ Vdd – 0.2V. 2. Typical values are measured at Vdd = 3.3V, TA = 25oC and not 100% tested. 14 Integrated Silicon Solution, Inc. — www.issi.com Rev. D 09/10/07 IS61NLP12832B IS61NLP12836B/IS61NVP12836B IS61NLP25618A/IS61NVP25618A CAPACITANCE(1,2) Symbol cIn couT Parameter Input Capacitance Input/Output Capacitance Conditions VIn = 0V VouT = 0V Max. 6 8 Unit pF pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25°c, f = 1 MHz, Vdd = 3.3V. 3.3V I/O AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0V to 3.0V 1.5 ns 1.5V See Figures 1 and 2 3.3V I/O OUTPUT LOAD EQUIVALENT 317 Ω OUTPUT Zo= 50Ω 50Ω 1.5V +3.3V OUTPUT 351 Ω 5 pF Including jig and scope Figure 1 Figure 2 Integrated Silicon Solution, Inc. — www.issi.com Rev. D 09/10/07 15 IS61NLP12832B IS61NLP12836B/IS61NVP12836B IS61NLP25618A/IS61NVP25618A 2.5V I/O AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0V to 2.5V 1.5 ns 1.25V See Figures 3 and 4 2.5V I/O OUTPUT LOAD EQUIVALENT 1,667 Ω ZO = 50Ω OUTPUT +2.5V OUTPUT 50Ω 1,538 Ω 1.25V 5 pF Including jig and scope Figure 3 Figure 4 16 Integrated Silicon Solution, Inc. — www.issi.com Rev. D 09/10/07 IS61NLP12832B IS61NLP12836B/IS61NVP12836B IS61NLP25618A/IS61NVP25618A READ/WRITE CYCLE SWITCHINg CHARACTERISTICS(1) (Over Operating Range) Symbol fmax tkc tkh tkl tkq tkqx(2) tkqlZ(2,3) tkqhZ(2,3) toeq toelZ(2,3) toehZ(2,3) tAS twS tceS tSe tAdVS tdS tAh the twh tceh tAdVh tdh tPdS tPuS Notes: Parameter Clock Frequency Cycle Time Clock High Time Clock Low Time Clock Access Time Clock High to Output Invalid Clock High to Output Low-Z Clock High to Output High-Z Output Enable to Output Valid Output Enable to Output Low-Z Output Disable to Output High-Z Address Setup Time Read/Write Setup Time Chip Enable Setup Time Clock Enable Setup Time Address Advance Setup Time Data Setup Time Address Hold Time Clock Enable Hold Time Write Hold Time Chip Enable Hold Time Address Advance Hold Time Data Hold Time ZZ High to Power Down ZZ Low to Power Down -250 Min. — 4.0 1.7 1.7 — 0.8 0.8 — — 0 — 1.2 1.2 1.2 1.2 1.2 1.2 0.3 0.3 0.3 0.3 0.3 0.3 — — Max. 250 — — — 2.6 — — 2.6 2.8 — 2.6 — — — — — — — — — — — — 2 2 -200 Min. Max. — 200 5 — 2 — 2 — — 3.1 1.5 — 1 — — 3.0 — 3.1 0 — — 3.0 1.4 — 1.4 — 1.4 — 1.4 — 1.4 — 1.4 — 0.4 — 0.4 — 0.4 — 0.4 — 0.4 — 0.4 — — 2 — 2 Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns cyc cyc 1. Configuration signal MODE is static and must not change during normal operation. 2. Guaranteed but not 100% tested. This parameter is periodically sampled. 3. Tested with load in Figure 2. Integrated Silicon Solution, Inc. — www.issi.com Rev. D 09/10/07 17 IS61NLP12832B IS61NLP12836B/IS61NVP12836B IS61NLP25618A/IS61NVP25618A SLEEP MODE ELECTRICAL CHARACTERISTICS Symbol ISb2 tPdS tPuS tZZI trZZI Parameter Current during SLEEP MODE ZZ active to input ignored ZZ inactive to input sampled ZZ active to SLEEP current ZZ inactive to exit SLEEP current Conditions ZZ ≥ VIh Min. 2 2 2 0 Max. 35 Unit mA cycle cycle cycle ns SLEEP MODE TIMINg CLK tPDS ZZ setup cycle tPUS ZZ recovery cycle ZZ tZZI Isupply ISB2 tRZZI All Inputs (except ZZ) Deselect or Read Only Deselect or Read Only Normal operation cycle Outputs (Q) High-Z Don't Care 18 Integrated Silicon Solution, Inc. — www.issi.com Rev. D 09/10/07 IS61NLP12832B IS61NLP12836B/IS61NVP12836B IS61NLP25618A/IS61NVP25618A READ CYCLE TIMINg tKH tKL CLK tADVS tADVH ADV tKC tAS tAH Address A1 A2 A3 tWS tWH WRITE tSE tHE CKE tCES tCEH CE OE tOEQ tOEHZ Data Out Q1-1 tOEHZ tKQX Q2-1 tKQ Q2-2 Q2-3 Q2-4 Q3-1 Q3-2 Q3-3 tKQHZ Q3-4 NOTES: WRITE = L means WE = L and BWx = L WE = L and BWX = L CE = L means CE1 = L, CE2 = H and CE2 = L CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L Don't Care Undefined Integrated Silicon Solution, Inc. — www.issi.com Rev. D 09/10/07 19 IS61NLP12832B IS61NLP12836B/IS61NVP12836B IS61NLP25618A/IS61NVP25618A WRITE CYCLE TIMINg tKH tKL CLK tKC ADV Address A1 A2 A3 WRITE tSE tHE CKE CE OE tDS Data In D1-1 D2-1 D2-2 D2-3 D2-4 D3-1 D3-2 tDH D3-3 D3-4 tOEHZ Data Out Q0-3 Q0-4 NOTES: WRITE = L means WE = L and BWx = L WE = L and BWX = L CE = L means CE1 = L, CE2 = H and CE2 = L CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L Don't Care Undefined 20 Integrated Silicon Solution, Inc. — www.issi.com Rev. D 09/10/07 IS61NLP12832B IS61NLP12836B/IS61NVP12836B IS61NLP25618A/IS61NVP25618A SINgLE READ/WRITE CYCLE TIMINg tKH tKL CLK tSE tHE tKC CKE Address A1 A2 A3 A4 A5 A6 A7 A8 A9 WRITE CE ADV OE tOEQ Data Out tOELZ Q1 tDS tDH Q3 Q4 Q6 Q7 Data In D2 NOTES: WRITE = L means WE = L and BWx = L CE = L means CE1 = L, CE2 = H and CE2 = L CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L D5 Don't Care Undefined Integrated Silicon Solution, Inc. — www.issi.com Rev. D 09/10/07 21 IS61NLP12832B IS61NLP12836B/IS61NVP12836B IS61NLP25618A/IS61NVP25618A CKE OPERATION TIMINg tKH tKL CLK tSE tHE tKC CKE Address A1 A2 A3 A4 A5 A6 WRITE CE ADV OE tKQ tKQHZ Data Out tKQLZ Q1 tDS tDH Q3 Q4 Data In NOTES: WRITE = L means WE = L and BWx = L CE = L means CE1 = L, CE2 = H and CE2 = L CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L D2 Don't Care Undefined 22 Integrated Silicon Solution, Inc. — www.issi.com Rev. D 09/10/07 IS61NLP12832B IS61NLP12836B/IS61NVP12836B IS61NLP25618A/IS61NVP25618A CE OPERATION TIMINg tKH tKL CLK tSE tHE tKC CKE Address A1 A2 A3 A4 A5 WRITE CE ADV OE tOEQ tKQHZ tKQ tKQLZ tOELZ Data Out Q1 Q2 tDS tDH Q4 Data In D3 NOTES: WRITE = L means WE = L and BWx = L CE = L means CE1 = L, CE2 = H and CE2 = L CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L D5 Don't Care Undefined Integrated Silicon Solution, Inc. — www.issi.com Rev. D 09/10/07 23 IS61NLP12832B IS61NLP12836B/IS61NVP12836B IS61NLP25618A/IS61NVP25618A ORDERINg INFORMATION (VDD = 3.3V/VDDq = 2.5V/3.3V) Commercial Range: 0°C to +70°C Access Time 250 200 250 200 250 200 Order Part Number 128Kx32 IS61NLP12832B-250TQ IS61NLP12832B-250B3 IS61NLP12832B-250B2 IS61NLP12832B-200TQ IS61NLP12832B-200B3 IS61NLP12832B-200B2 128Kx36 IS61NLP12836B-250TQ IS61NLP12836B-250B3 IS61NLP12836B-250B2 IS61NLP12836B-200TQ IS61NLP12836B-200B3 IS61NLP12836B-200B2 256Kx18 IS61NLP25618A-250TQ IS61NLP25618A-250B3 IS61NLP25618A-250B2 IS61NLP25618A-200TQ IS61NLP25618A-200B3 IS61NLP25618A-200B2 Package 100 TQFP 165 PBGA 119 PBGA 100 TQFP 165 PBGA 119 PBGA 100 TQFP 165 PBGA 119 PBGA 100 TQFP 165 PBGA 119 PBGA 100 TQFP 165 PBGA 119 PBGA 100 TQFP 165 PBGA 119 PBGA 24 Integrated Silicon Solution, Inc. — www.issi.com Rev. D 09/10/07 IS61NLP12832B IS61NLP12836B/IS61NVP12836B IS61NLP25618A/IS61NVP25618A ORDERINg INFORMATION (VDD = 3.3V/VDDq = 2.5V/3.3V) Industrial Range: -40°C to +85°C Access Time 250 200 250 200 250 200 Order Part Number 128Kx32 IS61NLP12832B-250TQI IS61NLP12832B-250B3I IS61NLP12832B-250B2I IS61NLP12832B-200TQI IS61NLP12832B-200TQLI IS61NLP12832B-200B3I IS61NLP12832B-200B2I 128Kx36 IS61NLP12836B-250TQI IS61NLP12836B-250B3I IS61NLP12836B-250B2I IS61NLP12836B-200TQI IS61NLP12836B-200TQLI IS61NLP12836B-200B3I IS61NLP12836B-200B2I IS61NLP12836B-200B2LI 256Kx18 IS61NLP25618A-250TQI IS61NLP25618A-250B3I IS61NLP25618A-250B2I IS61NLP25618A-200TQI IS61NLP25618A-200TQLI IS61NLP25618A-200B3I IS61NLP25618A-200B3LI IS61NLP25618A-200B2I Package 100 TQFP 165 PBGA 119 PBGA 100 TQFP 100 TQFP, Lead-free 165 PBGA 119 PBGA 100 TQFP 165 PBGA 119 PBGA 100 TQFP 100 TQFP, Lead-free 165 PBGA 119 PBGA 119 PBGA, Lead-free 100 TQFP 165 PBGA 119 PBGA 100 TQFP 100 TQFP, Lead-free 165 PBGA 165 PBGA, Lead-free 119 PBGA Integrated Silicon Solution, Inc. — www.issi.com Rev. D 09/10/07 25 IS61NLP12832B IS61NLP12836B/IS61NVP12836B IS61NLP25618A/IS61NVP25618A ORDERINg INFORMATION (VDD = 2.5V/VDDq = 2.5V) Commercial Range: 0°C to +70°C Access Time 250 200 250 200 Order Part Number 128Kx36 IS61NVP12836B-250TQ IS61NVP12836B-250B3 IS61NVP12836B-250B2 IS61NVP12836B-200TQ IS61NVP12836B-200B3 IS61NVP12836B-200B2 256Kx18 IS61NVP25618A-250TQ IS61NVP25618A-250B3 IS61NVP25618A-250B2 IS61NVP25618A-200TQ IS61NVP25618A-200B3 IS61NVP25618A-200B2 Package 100 TQFP 165 PBGA 119 PBGA 100 TQFP 165 PBGA 119 PBGA 100 TQFP 165 PBGA 119 PBGA 100 TQFP 165 PBGA 119 PBGA Industrial Range: -40°C to +85°C Access Time 250 200 250 200 Order Part Number 128Kx36 IS61NVP12836B-250TQI IS61NVP12836B-250B3I IS61NVP12836B-250B2I IS61NVP12836B-200TQI IS61NVP12836B-200B3I IS61NVP12836B-200B2I 256Kx18 IS61NVP25618A-250TQI IS61NVP25618A-250B3I IS61NVP25618A-250B2I IS61NVP25618A-200TQI IS61NVP25618A-200B3I IS61NVP25618A-200B2I Package 100 TQFP 165 PBGA 119 PBGA 100 TQFP 165 PBGA 119 PBGA 100 TQFP 165 PBGA 119 PBGA 100 TQFP 165 PBGA 119 PBGA 26 Integrated Silicon Solution, Inc. — www.issi.com Rev. D 09/10/07 PACKAGING INFORMATION Plastic Ball Grid Array Package Code: B (119-pin) φ b (119X) E A 7 6 5 4 32 1 A B C D E F G H J K L M N P R T U 30ϒ D D2 D1 e A2 E2 A3 A1 E1 A4 SEATING PLANE MILLIMETERS Sym. N0. Leads A A1 A2 A3 A4 b D D1 D2 E E1 E2 e — 0.50 0.80 1.30 0.60 21.80 19.40 13.80 11.90 INCHES Min. Max. Notes: Min. 119 Max. 2.41 0.70 1.00 1.70 0.90 22.20 19.60 14.20 12.10 — 0.020 0.032 0.051 0.024 0.858 0.764 0.543 0.469 0.095 0.028 0.039 0.067 0.035 0.874 0.772 0.559 0.476 1. Controlling dimension: millimeters, unless otherwise specified. 2. BSC = Basic lead spacing between centers. 3. Dimensions D1 and E do not include mold flash protrusion and should be measured from the bottom of the package. 4. Formed leads shall be planar with respect to one another within 0.004 inches at the seating plane. 0.56 BSC 0.022 BSC 20.32 BSC 0.800 BSC 7.62 BSC 1.27 BSC 0.300 BSC 0.050 BSC Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B 02/12/03 PACKAGING INFORMATION Ball Grid Array Package Code: B (165-pin) TOP VIEW A1 CORNER 1 A B C D E F G H J K L M N P R φ b (165X) BOTTOM VIEW A1 CORNER 9 8 7 6 5 4 3 2 1 A B C D 2 3 4 5 6 7 8 9 10 11 11 10 e E F G D D1 H J K L M N P R E1 E A2 A1 A e BGA - 13mm x 15mm MILLIMETERS Sym. N0. Leads A A1 A2 D D1 E E1 e b — 0.25 — 14.90 13.90 12.90 9.90 — 0.40 INCHES Min. Nom. Max. 165 Notes: 1. Controlling dimensions are in millimeters. Min. Nom. Max. 165 — 0.33 0.79 15.00 14.00 13.00 10.00 1.20 0.40 — 15.10 14.10 13.10 10.10 — 0.50 — 0.010 — 0.587 0.547 0.508 0.390 — 0.016 — 0.031 0.591 0.551 0.512 0.394 0.039 0.018 0.047 — 0.594 0.555 0.516 0.398 — 0.020 0.013 0.016 1.00 0.45 Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A 06/11/03 PACKAGING INFORMATION TQFP (Thin Quad Flat Pack Package) Package Code: TQ D D1 E E1 N 1 C e SEATING PLANE L1 L A2 A1 b A Symbol Ref. Std. No. Leads (N) 100 A — 1.60 — 0.063 A1 0.05 0.15 0.002 0.006 A2 1.35 1.45 0.053 0.057 b 0.22 0.38 0.009 0.015 D 21.90 22.10 0.862 0.870 D1 19.90 20.10 0.783 0.791 E 15.90 16.10 0.626 0.634 E1 13.90 14.10 0.547 0.555 e 0.65 BSC 0.026 BSC L 0.45 0.75 0.018 0.030 L1 1.00 REF. 0.039 REF. o o C 0 7 0o 7o Millimeters Min Max Thin Quad Flat Pack (TQ) Inches Millimeters Min Max Min Max 128 — 1.60 0.05 0.15 1.35 1.45 0.17 0.27 21.80 22.20 19.90 20.10 15.80 16.20 13.90 14.10 0.50 BSC 0.45 0.75 1.00 REF. 0o 7o Inches Min Max — 0.063 0.002 0.006 0.053 0.057 0.007 0.011 0.858 0.874 0.783 0.791 0.622 0.638 0.547 0.555 0.020 BSC 0.018 0.030 0.039 REF. 0o 7o Notes: 1. All dimensioning and tolerancing conforms to ANSI Y14.5M-1982. 2. Dimensions D1 and E1 do not include mold protrusions. Allowable protrusion is 0.25 mm per side. D1 and E1 do include mold mismatch and are determined at datum plane -H-. 3. Controlling dimension: millimeters. Integrated Silicon Solution, Inc. — 1-800-379-4774 PK13197LQ Rev. D 05/08/03