IS61NVP51236B-200B3I

IS61NLP51236(32)B/IS61NVP51236(32)B/IS61NVVP51236(32)B IS61NLP102418B/IS61NVP102418B/IS61NVVP102418B 512K x36 and 1024K x18 18Mb, PIPELINE 'NO WAIT' STATE BUS SYNCHRONOUS SRAM AUGUST 2019 FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control using MODE input • Three chip enables for simple depth expansion and address pipelining • Power Down mode • Common data inputs and data outputs • /CKE pin to enable clock and suspend operation • JEDEC 100-pin QFP, 165-ball BGA and 119ball BGA packages • Power supply: NLP: VDD 3.3V (± 5%), VDDQ 3.3V/2.5V (± 5%) NVP: VDD 2.5V (± 5%), VDDQ 2.5V (± 5%) NVVP: VDD 1.8V (± 5%), VDDQ 1.8V (± 5%) • JTAG Boundary Scan for BGA packages • Commercial, Industrial and Automotive (x36) temperature support • Lead-free available • For leaded option, please contact ISSI. FAST ACCESS TIME Symbol tKQ tKC Parameter Clock Access Time Cycle time Frequency DESCRIPTION The 18Meg product family features high-speed, lowpower synchronous static RAMs designed to provide a burstable, high-performance, 'no wait' state, device for networking and communications applications. They are organized as 512K words by 36 bits and 1024K words by 18 bits, fabricated with ISSI's advanced CMOS technology. Incorporating a 'no wait' state feature, wait cycles are eliminated when the bus switches from read to write, or write to read. This device integrates a 2-bit burst counter, high-speed SRAM core, and highdrive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers are controlled by a positive-edge-triggered single clock input. Operations may be suspended and all synchronous inputs ignored when Clock Enable, /CKE is HIGH. In this state the internal device will hold their previous values. All Read, Write and Deselect cycles are initiated by the ADV input. When the ADV is HIGH the internal burst counter is incremented. New external addresses can be loaded when ADV is LOW. Write cycles are internally self-timed and are initiated by the rising edge of the clock inputs and when /WE is LOW. Separate byte enables allow individual bytes to be written. A burst mode pin (MODE) defines the order of the burst sequence. When tied HIGH, the interleaved burst sequence is selected. When tied LOW, the linear burst sequence is selected. -250 2.6 4 250 -200 3.0 5 200 Units ns ns MHz Copyright © 2019 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc.- www.issi.com Rev. D2 08/12/2019 1 IS61NLP51236(32)B/IS61NVP51236(32)B/IS61NVVP51236(32)B IS61NLP102418B/IS61NVP102418B/IS61NVVP102418B BLOCK DIAGRAM (X= a,b,c,d or Integrated Silicon Solution, Inc.- www.issi.com Rev. D2 08/12/2019 2 IS61NLP51236(32)B/IS61NVP51236(32)B/IS61NVVP51236(32)B IS61NLP102418B/IS61NVP102418B/IS61NVVP102418B PIN CONFIGURATION 512K x 36, 165-Ball BGA (Top View) A B C D E F G H J K L M N P R 1 2 3 4 5 6 7 8 9 10 11 NC NC DQPc DQc DQc DQc DQc NC DQd DQd DQd DQd DQPd NC MODE A A NC DQc DQc DQc DQc NC DQd DQd DQd DQd NC NC NC /CE CE2 VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A /BWc /BWd VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A A /BWb /BWa VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDI TMS /CE2 CLK VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC A1* A0* /CKE /WE VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDO TCK ADV /OE VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A A A A A A NC DQb DQb DQb DQb NC DQa DQa DQa DQa NC A A NC NC DQPb DQb DQb DQb DQb ZZ DQa DQa DQa DQa DQPa NC A VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired. PIN DESCRIPTIONS Symbol CLK /CKE A0,A1 A ADV MODE /CE,CE2,/CE2 /WE Bottom View 165-Ball, 13 mm x 15mm BGA Integrated Silicon Solution, Inc.- www.issi.com Rev. D2 08/12/2019 /BWx (x=a-d) /OE DQx DQPx TCK,TDI, TDO,TMS ZZ NC VDD VDDQ VSS Pin Name Synchronous Clock Clock Enable Synchronous Burst Address Inputs Address Inputs Synchronous Burst Address Advance/Load Burst Sequence Selection Synchronous Chip Enable Synchronous Read/Write Control Input Synchronous Byte Write Inputs Output Enable Data Inputs/Outputs Parity Data I/O JTAG Pins Power Sleep Mode No Connect Power Supply I/O Power Supply Ground 3 IS61NLP51236(32)B/IS61NVP51236(32)B/IS61NVVP51236(32)B IS61NLP102418B/IS61NVP102418B/IS61NVVP102418B 512K x 32, 165-Ball BGA (Top View) A B C D E F G H J K L M N P R 1 2 3 4 5 6 7 8 9 10 11 NC NC NC DQc DQc DQc DQc NC DQd DQd DQd DQd NC NC MODE A A NC DQc DQc DQc DQc NC DQd DQd DQd DQd NC NC NC /CE CE2 VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A /BWc /BWd VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A A /BWb /BWa VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDI TMS /CE2 CLK VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC A1* A0* /CKE /WE VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDO TCK ADV /OE VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A A A A A A NC DQb DQb DQb DQb NC DQa DQa DQa DQa NC A A NC NC NC DQb DQb DQb DQb ZZ DQa DQa DQa DQa NC NC A VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired. PIN DESCRIPTIONS Symbol CLK /CKE A0,A1 A ADV MODE /CE,CE2,/CE2 /WE Bottom View 165-Ball, 13 mm x 15mm BGA Integrated Silicon Solution, Inc.- www.issi.com Rev. D2 08/12/2019 /BWx (x=a-d) /OE DQx TCK,TDI, TDO,TMS ZZ NC VDD VDDQ VSS Pin Name Synchronous Clock Clock Enable Synchronous Burst Address Inputs Address Inputs Synchronous Burst Address Advance/Load Burst Sequence Selection Synchronous Chip Enable Synchronous Read/Write Control Input Synchronous Byte Write Inputs Output Enable Data Inputs/Outputs JTAG Pins Power Sleep Mode No Connect Power Supply I/O Power Supply Ground 4 IS61NLP51236(32)B/IS61NVP51236(32)B/IS61NVVP51236(32)B IS61NLP102418B/IS61NVP102418B/IS61NVVP102418B 1024K x 18, 165-Ball BGA (Top View) A B C D E F G H J K L M N P R 1 2 3 4 5 6 7 8 9 10 11 NC NC NC NC NC NC NC NC DQb DQb DQb DQb DQPb NC MODE A A NC DQb DQb DQb DQb NC NC NC NC NC NC NC NC /CE CE2 VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A /BWb NC VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A A NC /BWa VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDI TMS /CE2 CLK VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC A1* A0* /CKE /WE VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDO TCK ADV /OE VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A A A A A A NC NC NC NC NC NC DQa DQa DQa DQa NC A A A NC DQPa DQa DQa DQa DQa ZZ NC NC NC NC NC NC A VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired. PIN DESCRIPTIONS Symbol CLK /CKE A0,A1 A /BWx (x=a-b) /OE Pin Name Synchronous Clock Clock Enable Synchronous Burst Address Inputs Address Inputs Synchronous Burst Address Advance/Load Burst Sequence Selection Synchronous Chip Enable Synchronous Read/Write Control Input Synchronous Byte Write Inputs Output Enable DQx Data Inputs/Outputs DQPx TCK,TDI, TDO,TMS ZZ NC VDD VDDQ VSS Parity Data I/O ADV MODE /CE,CE2,/CE2 /WE Bottom View 165-Ball, 13 mm x 15mm BGA Integrated Silicon Solution, Inc.- www.issi.com Rev. D2 08/12/2019 JTAG Pins Power Sleep Mode No Connect Power Supply I/O Power Supply Ground 5 IS61NLP51236(32)B/IS61NVP51236(32)B/IS61NVVP51236(32)B IS61NLP102418B/IS61NVP102418B/IS61NVVP102418B 512K x 36, 119-Ball BGA (Top View) A B C D E F G H J K L M N P R T U 1 2 3 4 5 6 7 VDDQ NC NC DQc DQc VDDQ DQc DQc VDDQ DQd DQd VDDQ DQd DQd NC NC VDDQ A CE2 A DQPc DQc DQc DQc DQc VDD DQd DQd DQd DQd DQPd A NC TMS A A A VSS VSS VSS /BWc VSS NC VSS /BWd VSS VSS VSS MODE A TDI A ADV VDD NC /CE /OE A /WE VDD CLK NC /CKE A1* A0* VDD A TCK A A A VSS VSS VSS /BWb VSS NC VSS /BWa VSS VSS VSS NC A TDO A /CE2 A DQPb DQb DQb DQb DQb VDD DQa DQa DQa DQa DQPa A NC NC VDDQ NC NC DQb DQb VDDQ DQb DQb VDDQ DQa DQa VDDQ DQa DQa NC ZZ VDDQ Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired. PIN DESCRIPTIONS Symbol CLK /CKE A0,A1 A ADV MODE /CE,CE2,/CE2 /WE Bottom View 119-Ball, 14 mm x 22 mm BGA Integrated Silicon Solution, Inc.- www.issi.com Rev. D2 08/12/2019 /BWx (x=a-d) /OE DQx DQPx TCK,TDI, TDO,TMS ZZ NC VDD VDDQ VSS Pin Name Synchronous Clock Clock Enable Synchronous Burst Address Inputs Address Inputs Synchronous Burst Address Advance/Load Burst Sequence Selection Synchronous Chip Enable Synchronous Read/Write Control Input Synchronous Byte Write Inputs Output Enable Data Inputs/Outputs Parity Data I/O JTAG Pins Power Sleep Mode No Connect Power Supply I/O Power Supply Ground 6 IS61NLP51236(32)B/IS61NVP51236(32)B/IS61NVVP51236(32)B IS61NLP102418B/IS61NVP102418B/IS61NVVP102418B 512K x 32, 119-Ball BGA (Top View) A B C D E F G H J K L M N P R T U 1 2 3 4 5 6 7 VDDQ NC NC DQc DQc VDDQ DQc DQc VDDQ DQd DQd VDDQ DQd DQd NC NC VDDQ A CE2 A NC DQc DQc DQc DQc VDD DQd DQd DQd DQd NC A NC TMS A A A VSS VSS VSS /BWc VSS NC VSS /BWd VSS VSS VSS MODE A TDI A ADV VDD NC /CE /OE A /WE VDD CLK NC /CKE A1* A0* VDD A TCK A A A VSS VSS VSS /BWb VSS NC VSS /BWa VSS VSS VSS NC A TDO A /CE2 A NC DQb DQb DQb DQb VDD DQa DQa DQa DQa NC A NC NC VDDQ NC NC DQb DQb VDDQ DQb DQb VDDQ DQa DQa VDDQ DQa DQa NC ZZ VDDQ Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired. PIN DESCRIPTIONS Symbol CLK /CKE A0,A1 A ADV MODE /CE,CE2,/CE2 /WE Bottom View 119-Ball, 14 mm x 22 mm BGA Integrated Silicon Solution, Inc.- www.issi.com Rev. D2 08/12/2019 /BWx (x=a-d) /OE DQx TCK,TDI, TDO,TMS ZZ NC VDD VDDQ VSS Pin Name Synchronous Clock Clock Enable Synchronous Burst Address Inputs Address Inputs Synchronous Burst Address Advance/Load Burst Sequence Selection Synchronous Chip Enable Synchronous Read/Write Control Input Synchronous Byte Write Inputs Output Enable Data Inputs/Outputs JTAG Pins Power Sleep Mode No Connect Power Supply I/O Power Supply Ground 7 IS61NLP51236(32)B/IS61NVP51236(32)B/IS61NVVP51236(32)B IS61NLP102418B/IS61NVP102418B/IS61NVVP102418B 1024K x 18, 119-Ball BGA (Top View) A B C D E F G H J K L M N P R T U 1 2 3 4 5 6 7 VDDQ NC NC DQb NC VDDQ NC DQb VDDQ NC DQb VDDQ DQb NC NC NC VDDQ A CE2 A NC DQb NC DQb NC VDD DQb NC DQb NC DQPb A A TMS A A A VSS VSS VSS /BWb VSS NC VSS NC VSS VSS VSS MODE A TDI A ADV VDD NC /CE /OE A /WE VDD CLK NC /CKE A1* A0* VDD NC TCK A A A VSS VSS VSS NC VSS NC VSS /BWa VSS VSS VSS NC A TDO A /CE2 A DQPa NC DQa NC DQa VDD NC DQa NC DQa NC A A NC VDDQ NC NC NC DQa VDDQ DQa NC VDDQ DQa NC VDDQ NC DQa NC ZZ VDDQ Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired. PIN DESCRIPTIONS Symbol CLK /CKE A0,A1 A ADV MODE /CE,CE2,/CE2 /WE Bottom View 119-Ball, 14 mm x 22 mm BGA Integrated Silicon Solution, Inc.- www.issi.com Rev. D2 08/12/2019 /BWx (x=a-b) /OE DQx DQPx TCK,TDI, TDO,TMS ZZ NC VDD VDDQ VSS Pin Name Synchronous Clock Clock Enable Synchronous Burst Address Inputs Address Inputs Synchronous Burst Address Advance/Load Burst Sequence Selection Synchronous Chip Enable Synchronous Read/Write Control Input Synchronous Byte Write Inputs Output Enable Data Inputs/Outputs Parity Data I/O JTAG Pins Power Sleep Mode No Connect Power Supply I/O Power Supply Ground 8 IS61NLP51236(32)B/IS61NVP51236(32)B/IS61NVVP51236(32)B IS61NLP102418B/IS61NVP102418B/IS61NVVP102418B 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 A A /CE CE2 /BWd /BWc /BWb /BWa /CE2 VDD VSS CLK /WE /CKE /OE ADV A A A A 512K x 36, 100PIN QFP (Top View) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 512K x 36 DQPb DQb DQb VDDQ VSS DQb DQb DQb DQb VSS VDDQ DQb DQb VSS NC VDD ZZ DQa DQa VDDQ VSS DQa DQa DQa DQa VSS VDDQ DQa DQa DQPa MODE A A A A A1 A0 NC NC VSS VDD NC NC A A A A A A A 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 DQPc DQc DQc VDDQ VSS DQc DQc DQc DQc VSS VDDQ DQc DQc NC VDD NC VSS DQd DQd VDDQ VSS DQd DQd DQd DQd VSS VDDQ DQd DQd DQPd Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired. PIN DESCRIPTIONS Symbol A A0,A1 ADV /WE CLK /CKE /CE,CE2,/CE2 /BWx (x=a-d) /OE Pin Name Address Inputs Synchronous Burst Address Inputs Synchronous Burst Address Advance/Load Synchronous Read/Write Control Input Synchronous Clock Clock Enable Synchronous Chip Enable Synchronous Byte Write Inputs Output Enable Integrated Silicon Solution, Inc.- www.issi.com Rev. D2 08/12/2019 Symbol ZZ MODE VDD NC DQx DQPx VDDQ VSS Pin Name Power Sleep Mode Burst Sequence Selection Power Supply No Connect Data Inputs/Outputs Parity Data I/O; NC for x32 option I/O Power Supply Ground 9 IS61NLP51236(32)B/IS61NVP51236(32)B/IS61NVVP51236(32)B IS61NLP102418B/IS61NVP102418B/IS61NVVP102418B 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 A A /CE CE2 /BWd /BWc /BWb /BWa /CE2 VDD VSS CLK /WE /CKE /OE ADV A A A A 512K x 32, 100PIN QFP (Top View) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 512K x 32 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 NC DQb DQb VDDQ VSS DQb DQb DQb DQb VSS VDDQ DQb DQb VSS NC VDD ZZ DQa DQa VDDQ VSS DQa DQa DQa DQa VSS VDDQ DQa DQa NC MODE A A A A A1 A0 NC NC VSS VDD NC NC A A A A A A A 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 NC DQc DQc VDDQ VSS DQc DQc DQc DQc VSS VDDQ DQc DQc NC VDD NC VSS DQd DQd VDDQ VSS DQd DQd DQd DQd VSS VDDQ DQd DQd NC Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired. PIN DESCRIPTIONS Symbol A A0,A1 ADV /WE CLK /CKE /CE,CE2,/CE2 /BWx (x=a-d) /OE Pin Name Address Inputs Synchronous Burst Address Inputs Synchronous Burst Address Advance/Load Synchronous Read/Write Control Input Synchronous Clock Clock Enable Synchronous Chip Enable Synchronous Byte Write Inputs Output Enable Integrated Silicon Solution, Inc.- www.issi.com Rev. D2 08/12/2019 Symbol ZZ MODE VDD NC DQx DQPx VDDQ VSS Pin Name Power Sleep Mode Burst Sequence Selection Power Supply No Connect Data Inputs/Outputs Parity Data I/O; NC for x32 option I/O Power Supply Ground 10 IS61NLP51236(32)B/IS61NVP51236(32)B/IS61NVVP51236(32)B IS61NLP102418B/IS61NVP102418B/IS61NVVP102418B 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 A A /CE CE2 NC NC /BWb /BWa /CE2 VDD VSS CLK /WE /CKE /OE ADV A A A A 1024K x 18, 100PIN QFP (Top View) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1024K x 18 A NC NC VDDQ VSS NC DQPa DQa DQa VSS VDDQ DQa DQa VSS NC VDD ZZ DQa DQa VDDQ VSS DQa DQa NC NC VSS VDDQ NC NC NC MODE A A A A A1 A0 NC NC VSS VDD NC NC A A A A A A A 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 NC NC NC VDDQ VSS NC NC DQb DQb VSS VDDQ DQb DQb NC VDD NC VSS DQb DQb VDDQ VSS DQb DQb DQPb NC VSS VDDQ NC NC NC Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired. PIN DESCRIPTIONS Symbol A A0,A1 ADV /WE CLK /CKE /CE,CE2,/CE2 /BWx (x=a-b) /OE Pin Name Address Inputs Synchronous Burst Address Inputs Synchronous Burst Address Advance/Load Synchronous Read/Write Control Input Synchronous Clock Clock Enable Synchronous Chip Enable Synchronous Byte Write Inputs Output Enable Integrated Silicon Solution, Inc.- www.issi.com Rev. D2 08/12/2019 Symbol ZZ MODE VDD NC DQx DQPx VDDQ VSS Pin Name Power Sleep Mode Burst Sequence Selection Power Supply No Connect Data Inputs/Outputs Parity Data I/O I/O Power Supply Ground 11 IS61NLP51236(32)B/IS61NVP51236(32)B/IS61NVVP51236(32)B IS61NLP102418B/IS61NVP102418B/IS61NVVP102418B STATE DIAGRAM READ WRITE BEGIN READ READ READ BURST DS READ WRITE DESELECT BURST BURST READ BEGIN WRITE DS WRITE BURST DS BURST DS DS WRITE WRITE BURST WRITE BURST READ TRUTH TABLE SYNCHRONOUS TRUTH TABLE Operation Address Used Not Selected N/A Not Selected N/A Not Selected N/A Not Selected Continue N/A Begin Burst Read External Address Continue Burst Read Next Address NOP/Dummy Read External Address Dummy Read Next Address Begin Burst Write External Address Continue Burst Write Next Address NOP/Write Abort N/A Write Abort Next Address Ignore Clock Current Address /CE H X X X L X L X L X L X X CE2 X L X X H X H X H X H X X /CE2 X X H X L X L X L X L X X ADV L L L H L H L H L H L H X /WE X X X X H X H X L X L X X /BWx X X X X X X X X L L H H X /OE X X X X L L H H X X X X X /CKE L L L L L L L L L L L L H CLK ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ Notes: 1. "X" means don't care. 2. The rising edge of clock is symbolized by ↑ 3. A continue deselect cycle can only be entered if a deselect cycle is executed first. 4. /WE = L means Write operation in Write Truth Table. 5. /WE = H means Read operation in Write Truth Table. 6. Operation finally depends on status of asynchronous pins (ZZ and /OE). Integrated Silicon Solution, Inc.- www.issi.com Rev. D2 08/12/2019 12 IS61NLP51236(32)B/IS61NVP51236(32)B/IS61NVVP51236(32)B IS61NLP102418B/IS61NVP102418B/IS61NVVP102418B ASYNCHRONOUS TRUTH TABLE Operation Sleep Mode Read Write Deselected ZZ H L L L L /OE X L H X X I/O STATUS High-Z DQ High-Z Din, High-Z High-Z Notes: 1. X means "Don't Care". 2. For write cycles following read cycles, the output buffers must be disabled with /OE, otherwise data bus contention will occur. 3. Sleep Mode means power Sleep Mode where stand-by current does not depend on cycle time. 4. Deselected means power Sleep Mode where stand-by current depends on cycle time. WRITE TRUTH TABLE (x18) Operation READ WRITE BYTE a WRITE BYTE b WRITE ALL BYTEs WRITE ABORT/NOP /WE H L L L L /BWa X L H L H /BWb X H L L H Notes: 1. X means "Don't Care". 2. All inputs in this table must beet setup and hold time around the rising edge of CLK. WRITE TRUTH TABLE (x36) Operation READ WRITE BYTE a WRITE BYTE b WRITE BYTE c WRITE BYTE d WRITE ALL BYTEs WRITE ABORT/NOP /WE H L L L L L L /BWa X L H H H L H /BWb X H L H H L H /BWc X H H L H L H /BWd X H H H L L H Notes: 1. X means "Don't Care". 2. All inputs in this table must beet setup and hold time around the rising edge of CLK. Integrated Silicon Solution, Inc.- www.issi.com Rev. D2 08/12/2019 13 IS61NLP51236(32)B/IS61NVP51236(32)B/IS61NVVP51236(32)B IS61NLP102418B/IS61NVP102418B/IS61NVVP102418B ADDRESS SEQUENCE IN BURST MODE INTERLEAVED BURST ADDRESS TABLE (MODE = VDD or NC) External Address 1st Burst Address 2nd Burst Address A1 A0 A1 A0 A1 A0 00 01 10 01 00 11 10 11 00 11 10 01 3rd Burst Address A1 A0 11 10 01 00 LINEAR BURST ADDRESS TABLE (MODE = Vss ) 0,0 A1', A0' = 1,1 0,1 1,0 Integrated Silicon Solution, Inc.- www.issi.com Rev. D2 08/12/2019 14 IS61NLP51236(32)B/IS61NVP51236(32)B/IS61NVVP51236(32)B IS61NLP102418B/IS61NVP102418B/IS61NVVP102418B ABSOLUTE MAXIMUM RATINGS AND OPERATING RANGE ABSOLUTE MAXIMUM RATINGS Symbol Parameter Tstg Storage Temperature NLP Value –65 to +150 NVP/NVVP Value –65 to +150 Unit °C Pd Power Dissipation 1.6 1.6 W Iout Output Current (per I/O) 20 20 mA –0.5 to VDDQ +0.3 –0.3 to VDD +0.5 –0.5 to VDDQ + 0.3 –0.3 to VDD + 0.3 V V Vin, Vout Voltage Relative to Vss for I/O Pins Vin Voltage Relative to Vss for Address and Control Inputs Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, precautions may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. 3. This device contains circuitry that will ensure the output devices are in High-Z at power up. OPERATING RANGE (IS61NLPx) Range Ambient Temperature Commercial 0°C to +70°C Industrial -40°C to +85°C Automotive -40°C to +125°C VDD VDDQ 3.3V ± 5% 3.3V ± 5% 3.3V ± 5% 3.3V / 2.5V ± 5% 3.3V / 2.5V ± 5% 3.3V / 2.5V ± 5% VDD VDDQ OPERATING RANGE (IS61NVPx) Range Commercial Industrial Automotive Ambient Temperature 0°C to +70°C -40°C to +85°C OPERATING RANGE (IS61NVVPx) Range Ambient Temperature Commercial 0°C to +70°C Industrial -40°C to +85°C Automotive Integrated Silicon Solution, Inc.- www.issi.com Rev. D2 08/12/2019 2.5V ± 5% 2.5V ± 5% 2.5V ± 5% 2.5V ± 5% *Please contact ISSI VDD VDDQ 1.8V ± 5% 1.8V ± 5% 1.8V ± 5% 1.8V ± 5% *Please contact ISSI 15 IS61NLP51236(32)B/IS61NVP51236(32)B/IS61NVVP51236(32)B IS61NLP102418B/IS61NVP102418B/IS61NVVP102418B CHARACTERISTICS DC ELECTRICAL CHARACTERISTICS (Over operating temperature range) Symbol Parameter Voh Output HIGH Voltage Vol Vih Vil Ili Ilo Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current Output Leakage Current Test Conditions 3.3V 2.5V Min. Max. 1.8V Min. Max. VDDQ — -0.4 Unit Min. Max. 2.4 — 2.0 — — 0.4 — 0.4 — 0.4 2.0 VDD +0.3 1.7 VDD +0.3 0.7* VDD –0.3 0.8 –0.3 0.7 –0.3 VDD +0.3 0.3* VDD Vss≤Vin≤ VDD –1 1 –1 1 –1 1 μA Vss≤Vout≤ VDDQ,/OE=Vih –1 1 –1 1 –1 1 μA Ioh=-4.0 mA(3.3V) Ioh=–1.0 mA(2.5V,1.8V) Iol=8.0 mA(3.3V) Iol=1.0 mA(2.5V,1.8V) V V V V Notes: 1. All voltages referenced to ground. 2. Overshoot: 3.3V and 2.5V: Vih (AC) ≤ VDD + 1.5V (Pulse width less than tkc /2) 1.8V: Vih (AC) ≤ VDD + 0.5V (Pulse width less than tkc /2) 3. Undershoot: 3.3V and 2.5V: Vil (AC) ≥ -1.5V (Pulse width less than tkc /2) 1.8V: Vil (AC) ≥ -0.5V (Pulse width less than tkc /2) 4. MODE pin has an internal pull-up and should be tied to VDD or Vss . It exhibits ±100μA maximum leakage current when tied to ≤Vss+0.2V or ≥ VDD– 0.2V. 5. ZZ pin has an internal pull-down and should be tied to VDD or Vss . It exhibits ±100μA maximum leakage current when tied to ≤Vss+0.2V or ≥ VDD–0.2V. POWER SUPPLY CHARACTERISTICS (Over Operating Range) Symbol Icc Isb Isb1 Temp. range -250 Max x18 x36 270 270 -200 Max x18 x36 220 220 Parameter Test Conditions AC Operating, Supply Current Standby Current TTL Input Standby Current CMOS Input Device Selected, OE = Vih, ZZ ≤ Vil,All Inputs ≤ 0.2V or ≥ VDD – 0.2V,Cycle Time ≥ tkc min. Com. Ind. 290 290 240 240 Device Deselected, VDD = Max.,All Inputs ≤ Vil or ≥ Vih,ZZ ≤ Vil, f = Max. Com. 80 80 70 70 Ind. 90 90 80 80 Device Deselected, VDD = Max.,Vin ≤ Vss + 0.2V or ≥ VDD – 0.2V,f = 0 Com. 60 60 60 60 Ind. 70 70 70 70 Unit mA mA mA Note: 1. Power-up assumes a linear ramp from 0V to VDD (min) within 200ms. During this time Vih < VDD and VDDQ < VDD Integrated Silicon Solution, Inc.- www.issi.com Rev. D2 08/12/2019 16 IS61NLP51236(32)B/IS61NVP51236(32)B/IS61NVVP51236(32)B IS61NLP102418B/IS61NVP102418B/IS61NVVP102418B CAPACITANCE Symbol Cin Cout Parameter Input Capacitance Input/Output Capacitance Conditions Vin = 0V Vout = 0V Max. 6 8 Unit pF pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: Ta = 25°C, f = 1 MHz, VDD = 3.3V. READ/WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range) Symbol Parameter fmax tkc tkh tkl tkq tkqx(2) tkqlz(2,3) tkqhz(2,3) toeq toelz(2,3) toehz(2,3) tas tws tces tse tadvs tds tah the twh tceh tadvh tdh Clock Frequency Cycle Time Clock High Time Clock Low Time Clock Access Time Clock High to Output Invalid Clock High to Output Low-Z Clock High to Output High-Z Output Enable to Output Valid Output Enable to Output Low-Z Output Disable to Output High-Z Address Setup Time Read/Write Setup Time Chip Enable Setup Time Clock Enable Setup Time Address Advance Setup Time Data Setup Time Address Hold Time Clock Enable Hold Time Write Hold Time Chip Enable Hold Time Address Advance Hold Time Data Hold Time -250 Min. — 4 1.7 1.7 — 0.8 0.8 — — 0 — 1.2 1.2 1.2 1.2 1.2 1.2 0.3 0.3 0.3 0.3 0.3 0.3 -200 Max. 250 — — — 2.6 — — 2.6 2.6 — 2.6 — — — — — — — — — — — — Min. — 5 2 2 — 1.5 1 — — 0 — 1.4 1.4 1.4 1.4 1.4 1.4 0.4 0.4 0.4 0.4 0.4 0.4 Unit Max. 200 — — — 3.0 — — 3.0 3.0 — 3.0 — — — — — — — — — — — — MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Notes: 1. Configuration signal MODE is static and must not change during normal operation. 2. Guaranteed but not 100% tested. This parameter is periodically sampled. 3. Tested with load in Figure 2. Integrated Silicon Solution, Inc.- www.issi.com Rev. D2 08/12/2019 17 IS61NLP51236(32)B/IS61NVP51236(32)B/IS61NVVP51236(32)B IS61NLP102418B/IS61NVP102418B/IS61NVVP102418B 3.3V I/O AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level VTT VLOAD R1, R2 Output Load Unit 0V to 3.0V 1.5 ns 1.5V 1.5V 3.3V 317Ω, 351Ω See Figures 1 and 2 2.5V I/O AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level VTT VLOAD R1, R2 Output Load Unit 0V to 2.5V 1.5 ns 1.25V 1.25V 2.5V 1667Ω, 1538Ω See Figures 1 and 2 1.8V I/O AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level VTT VLOAD R1, R2 Output Load Unit 0V to 1.8V 1.5 ns 0.9V 0.9V 1.8V 1KΩ, 1KΩ See Figures 1 and 2 I/O OUTPUT LOAD EQUIVALENT R1 VLOAD OUTPUT ZO =50Ω OUTPUT 50Ω R2 5 pF Including jig and scope VTT Figure1 Integrated Silicon Solution, Inc.- www.issi.com Rev. D2 08/12/2019 Figure2 18 IS61NLP51236(32)B/IS61NVP51236(32)B/IS61NVVP51236(32)B IS61NLP102418B/IS61NVP102418B/IS61NVVP102418B READ CYCLE TIMING tKH tKL CLK tKC tADVS tADVH ADV tAS tAH Address A2 A1 A3 tWS tWH /WRITE tSE tHE /CKE tCES tCEH /CE /OE tOEQ tOELZ Data Out tOEHZ tKQX Q1-1 Q2-1 tKQ Q2-2 tKQHZ Q2-3 Q2-4 Q3-1 NOTES: /WRITE = L means /WE = L and /BW X =L /CE = L means /CE1 = L, CE2 = H and /CE2 = L /CE = H means /CE1 = H, or /CE1 = L and /CE2 = H, or /CE1 = L and CE2 = L Integrated Silicon Solution, Inc.- www.issi.com Rev. D2 08/12/2019 Q3-2 Q3-3 Q3-4 Don't Care Undefined 19 IS61NLP51236(32)B/IS61NVP51236(32)B/IS61NVVP51236(32)B IS61NLP102418B/IS61NVP102418B/IS61NVVP102418B WRITE CYCLE TIMING tKH tKL CLK tKC ADV Address A1 A2 A3 /WRITE tSE tHE /CKE /CE /OE tDS tDH Data In D1-1 D2-1 D2-2 D2-3 D2-4 D3-1 D3-2 D3-3 D3-4 tOEHZ Data Out Q0-3 Q0-4 NOTES: /WRITE = L means /WE = L and /BW X = L /CE = L means /CE1 = L, CE2 = H and /CE2 = L /CE = H means /CE1= H, or /CE1 = L and /CE2 = H, or /CE1 = L and CE2 = L Integrated Silicon Solution, Inc.- www.issi.com Rev. D2 08/12/2019 Don't Care Undefined 20 IS61NLP51236(32)B/IS61NVP51236(32)B/IS61NVVP51236(32)B IS61NLP102418B/IS61NVP102418B/IS61NVVP102418B SINGLE READ/WRITE CYCLE TIMING tKH tKL CLK tSE tHE tKC CKE Address A1 A2 A3 A4 Q1 Q3 A5 A6 A7 A8 A9 /WRITE /CE ADV /OE tOEQ Data Out tOELZ Q4 Q6 Q7 tDS tDH Data In D2 D5 NOTES: /WRITE = L means /WE = L and /BW X = L /CE = L means /CE1 = L, CE2 = H and /CE2 = L /CE = H means /CE1= H, or /CE1 = L and /CE2 = H, or /CE1 = L and CE2 = L Integrated Silicon Solution, Inc.- www.issi.com Rev. D2 08/12/2019 Don't Care Undefined 21 IS61NLP51236(32)B/IS61NVP51236(32)B/IS61NVVP51236(32)B IS61NLP102418B/IS61NVP102418B/IS61NVVP102418B /CKE OPERATION TIMING tKH tKL CLK tSE tHE tKC CKE Address A1 A2 A3 A4 A5 A6 /WRITE /CE ADV /OE tKQ Data Out tKQLZ tKQHZ Q1 Q3 Q4 tDS tDH Data In D2 NOTES: /WRITE = L means /WE = L and /BW X = L /CE = L means /CE1 = L, CE2 = H and /CE2 = L /CE = H means /CE1= H, or /CE1 = L and /CE2 = H, or /CE1 = L and CE2 = L Integrated Silicon Solution, Inc.- www.issi.com Rev. D2 08/12/2019 Don't Care Undefined 22 IS61NLP51236(32)B/IS61NVP51236(32)B/IS61NVVP51236(32)B IS61NLP102418B/IS61NVP102418B/IS61NVVP102418B /CE OPERATION TIMING tKH tKL CLK tSE tHE tKC CKE Address A1 A2 A3 A4 A5 /WRITE /CE ADV /OE tOEQ Data Out tOELZ tKQHZ Q1 tKQ tKQLZ Q2 Q4 tDS tDH Data In D3 D5 Don't Care Undefined NOTES: /WRITE = L means /WE = L and /BW X = L /CE = L means /CE1 = L, CE2 = H and /CE2 = L /CE = H means /CE1= H, or /CE1 = L and /CE2 = H, or /CE1 = L and CE2 = L SNOOZE MODE ELECTRICAL CHARACTERISTICS Symbol Parameter Conditions ISB2 Current during SNOOZE MODE tPDS tPUS tZZI tRZZI ZZ active to input ignored ZZ inactive to input sampled ZZ active to SNOOZE current ZZ inactive to exit SNOOZE current Integrated Silicon Solution, Inc.- www.issi.com Rev. D2 08/12/2019 ZZ ≥ Vih Temperature Range Com. Ind. Auto. — — — — Min. — — — — 2 — 0 Max. 40 50 TBD 2 — 2 — Unit mA cycle cycle cycle ns 23 IS61NLP51236(32)B/IS61NVP51236(32)B/IS61NVVP51236(32)B IS61NLP102418B/IS61NVP102418B/IS61NVVP102418B SLEEP MODE TIMING CLK tPDS ZZ setup cycle tPUS ZZ recovery cycle ZZ tZZI Isupply ISB2 tRZZI All Inputs (except ZZ) Deselect or Read Only Deselect or Read Only Normal operation cycle Outputs (Q) High-Z Don't Care Integrated Silicon Solution, Inc.- www.issi.com Rev. D2 08/12/2019 24 IS61NLP51236(32)B/IS61NVP51236(32)B/IS61NVVP51236(32)B IS61NLP102418B/IS61NVP102418B/IS61NVVP102418B IEEE 1149.1 TAP and Boundary Scan The SRAM provides a limited set of JTAG functions to test the interconnection between SRAM I/Os and printed circuit board traces or other components. There is no multiplexer in the path from I/O pins to the RAM core. In conformance with IEEE Standard 1149.1, the SRAM contains a TAP controller, instruction register, boundary scan register, bypass register, and ID register. The TAP controller has a standard 16-state machine that resets internally on power-up. Therefore, a TRST signal is not required Disabling the JTAG feature The SRAM can operate without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be left disconnected. They may alternately be connected to VDD through a pull-up resistor. TDO should be left disconnected. On power-up, the device will come up in a reset state, which will not interfere with device operation. Test Access Port Signal List: 1. Test Clock (TCK) This signal uses VDD as a power supply. The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK. 2. Test Mode Select (TMS) This signal uses VDD as a power supply. The TMS input is used to send commands to the TAP controller and is sampled on the rising edge of TCK. 3. Test Data-In (TDI) This signal uses VDD as a power supply. The TDI input is used to serially input test instructions and information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. TDI is connected to the most significant bit (MSB) of any register. For more information regarding instruction register loading, please see the TAP Controller State Diagram. 4. Test Data-Out (TDO) This signal uses VDD as a power supply. The TDO output ball is used to serially clock test instructions and data out from the registers. The TDO output driver is only active during the Shift-IR and Shift-DR TAP controller states. In all other states, the TDO pin is in a High-Z state. The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register. For more information, please see the TAP Controller State Diagram. Integrated Silicon Solution, Inc.- www.issi.com Rev. D2 08/12/2019 25 IS61NLP51236(32)B/IS61NVP51236(32)B/IS61NVVP51236(32)B IS61NLP102418B/IS61NVP102418B/IS61NVVP102418B TAP Controller State and Block Diagram ... Boundary Scan Register (75 90 bits) TDI Bypass Register (1 bit) Identification Register (32 bits) TDO Instruction Register (3 bits) Control Signals TMS TAP Controller TCK TAP Controller State Machine 1 Test Logic Reset 0 Run Test Idle 1 Select DR 1 Select IR 0 1 0 0 1 1 Capture DR 0 Capture IR 0 0 Shift DR 1 1 1 1 Exit1 DR Exit1 IR 0 0 0 Pause DR 1 Exit2 DR 0 Exit2 IR 1 0 1 Update DR Integrated Silicon Solution, Inc.- www.issi.com Rev. D2 08/12/2019 0 Pause IR 1 1 0 Shift IR Update IR 0 1 0 26 IS61NLP51236(32)B/IS61NVP51236(32)B/IS61NVVP51236(32)B IS61NLP102418B/IS61NVP102418B/IS61NVVP102418B Performing a TAP Reset A Reset is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. RESET may be performed while the SRAM is operating and does not affect its operation. At power-up, the TAP is internally reset to ensure that TDO comes up in a high-Z state. TAP Registers Registers are connected between the TDI and TDO pins and allow data to be scanned into and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction registers. Data is serially loaded into the TDI pin on the rising edge of TCK and output on the TDO pin on the falling edge of TCK. 1. Instruction Register This register is loaded during the update-IR state of the TAP controller. At power-up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section. When the TAP controller is in the capture-IR state, the two LSBs are loaded with a binary “01” pattern to allow for fault isolation of the board-level serial test data path. 2. Bypass Register The bypass register is a single-bit register that can be placed between the TDI and TDO balls. This allows data to be shifted through the SRAM with minimal delay. The bypass register is set LOW (VSS) when the BYPASS instruction is executed. 3. Boundary Scan Register The boundary scan register is connected to all the input and bidirectional balls on the SRAM. Several balls are also included in the scan register to reserved balls. The boundary scan register is loaded with the contents of the SRAM Input and Output ring when the TAP controller is in the capture-DR state and is then placed between the TDI and TDO balls when the controller is moved to the shift-DR state. Each bit corresponds to one of the balls on the SRAM package. The MSB of the register is connected to TDI, and the LSB is connected to TDO. 4. Identification (ID) Register The ID register is loaded with a vendor-specific, 32-bit code during the capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the shift-DR state. Scan Register Sizes Register Name Instruction Bypass ID Boundary Scan Bit Size 3 1 32 90 TAP Instruction Set Many instructions are possible with an eight-bit instruction register and all valid combinations are listed in the TAP Instruction Code Table. All other instruction codes that are not listed on this table are reserved and should not be used. Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted from the instruction register through the Integrated Silicon Solution, Inc.- www.issi.com Rev. D2 08/12/2019 27 IS61NLP51236(32)B/IS61NVP51236(32)B/IS61NVVP51236(32)B IS61NLP102418B/IS61NVP102418B/IS61NVVP102418B TDI and TDO pins. To execute an instruction once it is shifted in, the TAP controller must be moved into the Update-IR state. 1. EXTEST The EXTEST instruction allows circuitry external to the component package to be tested. Boundary-scan register cells at output balls are used to apply a test vector, while those at input balls capture test results. Typically, the first test vector to be applied using the EXTEST instruction will be shifted into the boundary scan register using the PRELOAD instruction. Thus, during the update-IR state of EXTEST, the output driver is turned on, and the PRELOAD data is driven onto the output balls. 2. IDCODE The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO balls and allows the IDCODE to be shifted out of the device when the TAP controller enters the shift-DR state. The IDCODE instruction is loaded into the instruction register upon power-up or whenever the TAP controller is given a test logic reset state. 3. SAMPLE Z If the SAMPLE-Z instruction is loaded in the instruction register, all SRAM outputs are forced to an inactive drive state (high-Z), moving the TAP controller into the capture-DR state loads the data in the SRAMs input into the boundary scan register, and the boundary scan register is connected between TDI and TDO when the TAP controller is moved to the shift-DR state. 4. SAMPLE/PRELOAD When the SAMPLE/PRELOAD instruction is loaded into the instruction register and the TAP controller is in the capture-DR state, a snapshot of data on the inputs and bidirectional balls is captured in the boundary scan register. The user must be aware that the TAP controller clock can only operate at a frequency up to 10 MHz, while the SRAM clock operates significantly faster. Because there is a large difference between the clock frequencies, it is possible that during the capture-DR state, an input or output will undergo a transition. The TAP may then try to capture a signal while in transition. This will not harm the device, but there is no guarantee as to the value that will be captured. Repeatable results may not be possible. To ensure that the boundary scan register will capture the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller’s capture setup plus hold time. The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/ PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the value of the CLK captured in the boundary scan register. Once the data is captured, it is possible to shift out the data by putting the TAP into the shift-DR state. This places the boundary scan register between the TDI and TDO balls. 6. BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a shift-DR state, the bypass register is placed between TDI and TDO. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. 7. PRIVATE Do not use these instructions. They are reserved for future use and engineering mode. Integrated Silicon Solution, Inc.- www.issi.com Rev. D2 08/12/2019 28 IS61NLP51236(32)B/IS61NVP51236(32)B/IS61NVVP51236(32)B IS61NLP102418B/IS61NVP102418B/IS61NVVP102418B JTAG DC Operating Characteristics (Over the Operating Temperature Range, 2.5V and 3.3V Option) Parameter Symbol Min JTAG Input High Voltage VIH1 1.7 JTAG Input Low Voltage VIL1 –0.3 JTAG Output High Voltage VOH1 1.7 JTAG Output Low Voltage VOL1 JTAG Output High Voltage VOH2 2.1 JTAG Output Low Voltage VOL2 JTAG Input Leakage Current ILIJTAG -10 JTAG Output Leakage Current ILOJTAG -10 Max VDD+0.3 0.7 0.7 0.2 +10 +10 Units V V V V V V µA µA Notes |IOH1|=2mA IOL1=2mA |IOH2|=100µA IOL2=100µA 0 ≤ Vin ≤ VDD 0 ≤ Vout ≤ VDD Notes: 1. All voltages referenced to VSS (GND); All JTAG inputs and outputs are LVTTL-compatible. JTAG DC Operating Characteristics (Over the Operating Temperature Range, 1.8V Option) Parameter Symbol Min JTAG Input High Voltage VIH1 TBD JTAG Input Low Voltage VIL1 TBD JTAG Output High Voltage VOH1 TBD JTAG Output Low Voltage VOL1 TBD JTAG Input Leakage Current ILIJTAG TBD JTAG Output Leakage Current ILOJTAG TBD Max TBD TBD TBD TBD TBD TBD Units V V V V µA µA Notes Notes: 1. All voltages referenced to VSS (GND); All JTAG inputs and outputs are LVTTL-compatible. JTAG AC Test Conditions (Over the Operating Temperature Range) Parameter Input Pulse High Level Input Pulse Low Level Input rise and fall time Test load termination supply voltage Input and Output Timing Reference Level Symbol 1.8V Option 2.5V Option VIH1 VIL1 TR1 VREF VREF TBD TBD TBD TBD TBD 2.5 0 1.5 1.25 1.25 3.3V Option 3.0 0 1.5 1.5 1.5 Units V V ns V V TAP Output Load Equivalent VREF 50Ω 50Ω Output 20pF Test Comparator VREF Integrated Silicon Solution, Inc.- www.issi.com Rev. D2 08/12/2019 29 IS61NLP51236(32)B/IS61NVP51236(32)B/IS61NVVP51236(32)B IS61NLP102418B/IS61NVP102418B/IS61NVVP102418B JTAG AC Characteristics (Over the Operating Temperature Range) Parameter TCK cycle time TCK high pulse width TCK low pulse width TMS Setup TMS Hold TDI Setup TDI Hold TCK Low to Valid Data Symbol tTHTH tTHTL tTLTH tMVTH tTHMX tDVTH tTHDX tTLOV Min 100 40 40 10 10 10 10 – Max – – – – – – – 20 Units ns ns ns ns ns ns ns ns JTAG Timing Diagram tTHTL tTHTH tTLTH TCK tMVTH tTHMX tDVTH tTHDX TMS TDI tTLOV TDO Integrated Silicon Solution, Inc.- www.issi.com Rev. D2 08/12/2019 30 IS61NLP51236(32)B/IS61NVP51236(32)B/IS61NVVP51236(32)B IS61NLP102418B/IS61NVP102418B/IS61NVVP102418B Instruction Set Code Instruction TDO Output Notes 000 001 010 EXTEST IDCODE SAMPLE-Z Boundary Scan Register 32-bit Identification Register Boundary Scan Register 2, 6 011 PRIVATE Do Not Use 5 100 SAMPLE(/PRELOAD) Boundary Scan Register 4 101 PRIVATE Do Not Use 5 110 PRIVATE Do Not Use 5 111 BYPASS Bypass Register 3 1, 2 Notes: 1. Places DQs in high-Z in order to sample all input data, regardless of other SRAM inputs. 2. TDI is sampled as an input to the first ID register to allow for the serial shift of the external TDI data. 3. BYPASS register is initiated to VSS when BYPASS instruction is invoked. The BYPASS register also holds the last serially loaded TDI when exiting the shift-DR state. 4. SAMPLE instruction does not place DQs in high-Z. 5. This instruction is reserved. Invoking this instruction will cause improper SRAM functionality. 6. By default, it places DQs in high-Z. If the internal register on the scan chain is set high, DQs will be updated with information loaded via a previous SAMPLE instruction. The actual transfer occurs during the update IR state after EXTEST is loaded. The value of the internal register can be changed during SAMPLE and EXTEST only. ID Register Definition Instruction Field Revision Number (31:28) Description Reserved for version number. 512K x 36 xxxx 1024K x 18 xxxx Device Depth (27:23) Defines depth of SRAM. 512K or 1024K 00111 01000 Device Width (22:18) Defines Width of the SRAM. x36 or x18 00100 00011 ISSI Device ID (17:12) Reserved for future use. xxxxxx xxxxxx ISSI JEDEC ID (11:1) Allows unique identification of SRAM vendor. Indicate the presence of an ID register. 00001010101 00001010101 1 1 ID Register Presence (0) Integrated Silicon Solution, Inc.- www.issi.com Rev. D2 08/12/2019 31 IS61NLP51236(32)B/IS61NVP51236(32)B/IS61NVVP51236(32)B IS61NLP102418B/IS61NVP102418B/IS61NVVP102418B Boundary Scan Order (TBA – 119 BGA) 165 BGA Bit # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 X36 Bump ID N6 N7 N10 P11 P8 R8 R9 P9 P10 R10 R11 H11 N11 M11 L11 M10 L10 K11 J11 K10 J10 H9 H10 G11 F11 G10 E11 D11 F10 E10 D10 C11 A11 B11 A10 B10 A9 Signal NC NC NC NC A18 A17 A16 A15 A14 A13 A12 ZZ DQa0 DQa1 DQa2 DQa3 DQa4 DQa5 DQa6 DQa7 DQa8 NC NC DQb8 DQb7 DQb6 DQb5 DQb4 DQb3 DQb2 DQb1 DQb0 NC NC A11 A10 A9 X18 Bump ID N6 N7 N10 P11 P8 R8 R9 P9 P10 R10 R11 H11 N11 M11 L11 M10 L10 K11 J11 K10 J10 H9 H10 G11 F11 G10 E11 D11 C11 E10 D10 F10 A11 B11 A10 B10 A9 Signal NC NC NC NC A18 A17 A16 A15 A14 A13 A12 ZZ NC NC NC DQa8 DQa7 NC NC DQa6 DQa5 NC NC DQa4 DQa3 NC DQa2 DQa1 DQa0 NC NC NC A19 NC A11 A10 A9 Continued on next page Integrated Silicon Solution, Inc.- www.issi.com Rev. D2 08/12/2019 32 IS61NLP51236(32)B/IS61NVP51236(32)B/IS61NVVP51236(32)B IS61NLP102418B/IS61NVP102418B/IS61NVVP102418B 165 BGA Bit # 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 X36 Bump ID B9 C10 A8 B8 A7 B7 B6 A6 B5 A5 A4 B4 B3 A3 A2 B2 C2 B1 A1 C1 D1 E1 D2 E2 F1 G1 F2 G2 H1 H2 H3 J1 K1 J2 L1 M1 K2 L2 M2 N1 N2 P1 Signal A8 NC ADV /OE /CKE /WE CLK /CE2 /Bwa /Bwb /Bwc /Bwd CE2 /CE1 A7 A6 NC NC NC DQc0 DQc1 DQc2 DQc3 DQc4 DQc5 DQc6 DQc7 DQc8 NC NC NC DQd8 DQd7 DQd6 DQd5 DQd4 DQd3 DQd2 DQd1 DQd0 NC NC X18 Bump ID B9 C10 A8 B8 A7 B7 B6 A6 B5 A5 A4 B4 B3 A3 A2 B2 C2 B1 A1 C1 D1 E1 D2 E2 F1 G1 F2 G2 H1 H2 H3 J1 K1 J2 L1 M1 N1 L2 M2 K2 N2 P1 Signal A8 NC ADV /OE /CKE /WE CLK /CE2 /Bwa NC /Bwb NC CE2 /CE1 A7 A6 NC NC NC NC NC NC DQb8 DQb7 NC NC DQb6 DQb5 NC NC NC DQb4 DQb3 NC DQb2 DQb1 DQb0 NC NC NC NC NC Continued on next page Integrated Silicon Solution, Inc.- www.issi.com Rev. D2 08/12/2019 33 IS61NLP51236(32)B/IS61NVP51236(32)B/IS61NVVP51236(32)B IS61NLP102418B/IS61NVP102418B/IS61NVVP102418B 165 BGA X36 Bit # 80 81 82 83 84 85 86 87 88 89 90 Bump ID R1 R2 P3 R3 P2 P4 R4 N5 P6 R6 * X18 Signal MODE NC A5 A4 NC A2 A3 NC A1 A0 Int Bump ID R1 R2 P3 R3 P2 P4 R4 N5 P6 R6 * Signal MODE NC A5 A4 NC A2 A3 NC A1 A0 Int Integrated Silicon Solution, Inc.- www.issi.com Rev. D2 08/12/2019 34 IS61NLP51236(32)B/IS61NVP51236(32)B/IS61NVVP51236(32)B IS61NLP102418B/IS61NVP102418B/IS61NVVP102418B ORDERING INFORMATION Commercial Range: 0°C to +70°C VDD Speed 250MHz VDD=3.3V, VDDQ=2.5V/3.3V 200MHz X36 IS61NLP51236B-250TQ IS61NLP51236B-250B3 IS61NLP51236B-250B2 IS61NLP51236B-250TQL IS61NLP51236B-250B3L IS61NLP51236B-250B2L IS61NLP51236B-200TQ IS61NLP51236B-200B3 IS61NLP51236B-200B2 IS61NLP51236B-200TQL IS61NLP51236B-200B3L IS61NLP51236B-200B2L VDD=1.8V, VDDQ=1.8V 200MHz Package 100 QFP 165 BGA 119 BGA 100 QFP, Lead-free 165 BGA, Lead-free 119 BGA, Lead-free 100 QFP 165 BGA 119 BGA 100 QFP, Lead-free 165 BGA, Lead-free 119 BGA, Lead-free *Please contact ISSI Marketing 250MHz VDD=2.5V, VDDQ=2.5V X18 IS61NLP102418B-250TQ IS61NLP102418B-250B3 IS61NLP102418B-250B2 IS61NLP102418B-250TQL IS61NLP102418B-250B3L IS61NLP102418B-250B2L IS61NLP102418B-200TQ IS61NLP102418B-200B3 IS61NLP102418B-200B2 IS61NLP102418B-200TQL IS61NLP102418B-200B3L IS61NLP102418B-200B2L IS61NVP51236B-200TQ IS61NVP102418B-200TQ 100 QFP IS61NVP51236B-200B3 IS61NVP102418B-200B3 165 BGA IS61NVP51236B-200TQL IS61NVP102418B-200TQL 100 QFP, Lead-free IS61NVP51236B-200B3L IS61NVP102418B-200B3L 165 BGA, Lead-free 250MHz *Please contact ISSI Marketing 200MHz *Please contact ISSI Marketing Integrated Silicon Solution, Inc.- www.issi.com Rev. D2 08/12/2019 35 IS61NLP51236(32)B/IS61NVP51236(32)B/IS61NVVP51236(32)B IS61NLP102418B/IS61NVP102418B/IS61NVVP102418B Industrial Range: -40°C to +85°C VDD Speed 250MHz VDD=3.3V, VDDQ=2.5V/3.3V 200MHz 250MHz VDD=2.5V, VDDQ=2.5V VDD=1.8V, VDDQ=1.8V X36 X18 IS61NLP51236B-250TQI IS61NLP102418B-250TQI IS61NLP51236B-250B3I IS61NLP102418B-250B3I IS61NLP51236B-250B2I IS61NLP102418B-250B2I IS61NLP51236B-250TQLI IS61NLP102418B-250TQLI IS61NLP51236B-250B3LI IS61NLP102418B-250B3LI IS61NLP51236B-250B2LI IS61NLP102418B-250B2LI IS61NLP51236B-200TQI IS61NLP102418B-200TQI IS61NLP51236B-200B3I IS61NLP102418B-200B3I IS61NLP51236B-200B2I IS61NLP102418B-200B2I IS61NLP51236B-200TQLI IS61NLP102418B-200TQLI IS61NLP51236B-200B3LI IS61NLP102418B-200B3LI IS61NLP51236B-200B2LI IS61NLP102418B-200B2LI *Please contact ISSI Marketing Package 100 QFP 165 BGA 119 BGA 100 QFP, Lead-free 165 BGA, Lead-free 119 BGA, Lead-free 100 QFP 165 BGA 119 BGA 100 QFP, Lead-free 165 BGA, Lead-free 119 BGA, Lead-free IS61NVP51236B-200TQI IS61NVP102418B-200TQI 100 QFP IS61NVP51236B-200B3I IS61NVP102418B-200B3I 165 BGA IS61NVP51236B-200TQLI IS61NVP102418B-200TQLI 100 QFP, Lead-free IS61NVP51236B-200B3LI IS61NVP102418B-200B3LI 165 BGA, Lead-free 200MHz 250MHz *Please contact ISSI Marketing 200MHz *Please contact ISSI Marketing ORDERING INFORMATION Automotive (A3) Range: -40°C to +125°C VDD Speed 250MHz VDD=3.3V, VDDQ=2.5V/3.3V 200MHz X36 IS64NLP51236B-250TQLA3 IS64NLP51236B-250B3LA3 IS64NLP51236B-250B2LA3 IS64NLP51236B-200TQLA3 IS64NLP51236B-200B3LA3 IS64NLP51236B-200B2LA3 Package 100 QFP, Lead-free 165 BGA, Lead-free 119 BGA, Lead-free 100 QFP, Lead-free 165 BGA, Lead-free 119 BGA, Lead-free *For all other voltages and options in automotive grade, please contact ISSI. Integrated Silicon Solution, Inc.- www.issi.com Rev. D2 08/12/2019 36 IS61NLP51236(32)B/IS61NVP51236(32)B/IS61NVVP51236(32)B IS61NLP102418B/IS61NVP102418B/IS61NVVP102418B Integrated Silicon Solution, Inc.- www.issi.com Rev. D2 08/12/2019 37 IS61NLP51236(32)B/IS61NVP51236(32)B/IS61NVVP51236(32)B IS61NLP102418B/IS61NVP102418B/IS61NVVP102418B Integrated Silicon Solution, Inc.- www.issi.com Rev. D2 08/12/2019 38 IS61NLP51236(32)B/IS61NVP51236(32)B/IS61NVVP51236(32)B IS61NLP102418B/IS61NVP102418B/IS61NVVP102418B Integrated Silicon Solution, Inc.- www.issi.com Rev. D2 08/12/2019 39