IS61QDPB21M36A-333M3L

IS61QDPB22M18A/A1/A2 IS61QDPB21M36A/A1/A2 2Mx18, 1Mx36 36Mb QUADP (Burst 2) Synchronous SRAM DECEMBER 2014 (2.5 CYCLE READ LATENCY) FEATURES                      1Mx36 and 2Mx18 configuration available. On-chip Delay-Locked Loop (DLL) for wide data valid window. Separate independent read and write ports with concurrent read and write operations. Synchronous pipeline read with EARLY write operation. Double Data Rate (DDR) interface for read and write input ports. 2.5 Cycle read latency. Fixed 2-bit burst for read and write operations. Clock stop support. Two input clocks (K and K#) for address and control registering at rising edges only. Two echo clocks (CQ and CQ#) that are delivered simultaneously with data. Data valid pin (QVLD). +1.8V core power supply and 1.5, 1.8V VDDQ, used with 0.75, 0.9V VREF. HSTL input and output interface. Registered addresses, write and read controls, byte writes, data in, and data outputs. Full data coherency. Boundary scan using limited set of JTAG 1149.1 functions. Byte Write capability. Fine ball grid array (FBGA) package option: 13mmx15mm and 15mmx17mm body size 165-ball (11 x 15) array Programmable impedance output drivers via 5x user-supplied precision resistor. ODT (On Die Termination) feature is supported optionally on data input, K/K#, and BWx#. The end of top mark (A/A1/A2) is to define options. IS61QDPB21M36A : Don’t care ODT function and pin connection IS61QDPB21M36A1 : Option1 IS61QDPB21M36A2 : Option2 Refer to more detail description at page 6 for each ODT option. DESCRIPTION The and are synchronous, highperformance CMOS static random access memory (SRAM) devices. These SRAMs have separate I/Os, eliminating the need for high-speed bus turnaround. The rising edge of K clock initiates the read/write operation, and all internal operations are self-timed. Refer to the for a description of the basic operations of these SRAMs. Read and write addresses are registered on alternating rising edges of the K clock. Read and write performed in double data rate. The following are registered internally on the rising edge of the K clock:  Read address  Read enable  Write enable  Data-in for early writes The following are registered on the rising edge of the K# clock:  Write address  Byte writes  Data-in for second burst addresses Byte writes can change with the corresponding data-in to enable or disable writes on a per-byte basis. An internal write buffer enables the data-ins to be registered half a cycle earlier than the write address. The first data-in burst is clocked at the same time as the write command signal, and the second burst is timed to the following rising edge of the K# clock. During the burst read operation, the data-outs from the first bursts are updated from output registers of the second rising edge of the K# clock (starting two and half cycles later after read command). The data-outs from the second bursts are updated with the third rising edge of the K clock. The K and K# clocks are used to time the data-outs. The device is operated with a single +1.8V power supply and is compatible with HSTL I/O interface. Copyright © 2014 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc.- www.issi.com Rev. B 12/15/2014 1 IS61QDPB22M18A/A1/A2 IS61QDPB21M36A/A1/A2 Package ballout and description x36 FBGA Ball Configuration (Top View) 1 2 3 4 5 6 7 8 9 10 11 A CQ# NC/SA1 NC/SA1 W# BW2# K# BW1# R# SA NC/SA1 CQ B Q27 Q18 D18 SA BW3# K BW0# SA D17 Q17 Q8 C D27 Q28 D19 VSS SA SA SA VSS D16 Q7 D8 D D28 D20 Q19 VSS VSS VSS VSS VSS Q16 D15 D7 E Q29 D29 Q20 VDDQ VSS VSS VSS VDDQ Q15 D6 Q6 F Q30 Q21 D21 VDDQ VDD VSS VDD VDDQ D14 Q14 Q5 G D30 D22 Q22 VDDQ VDD VSS VDD VDDQ Q13 D13 D5 H Doff# VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ J D31 Q31 D23 VDDQ VDD VSS VDD VDDQ D12 Q4 D4 K Q32 D32 Q23 VDDQ VDD VSS VDD VDDQ Q12 D3 Q3 L Q33 Q24 D24 VDDQ VSS VSS VSS VDDQ D11 Q11 Q2 M D33 Q34 D25 VSS VSS VSS VSS VSS D10 Q1 D2 N D34 D26 Q25 VSS SA SA SA VSS Q10 D9 D1 P Q35 D35 Q26 SA SA QVLD SA SA Q9 D0 Q0 R TDO TCK SA SA SA ODT SA SA SA TMS TDI Notes: The following balls are reserved for higher densities: 3A for 72M, 10A for 144Mb, and 2A for 288Mb. x18 FBGA Ball Configuration (Top View) 1 2 3 1 4 5 6 7 8 1 9 10 11 1 A CQ# NC/SA SA W# BW1# K# NC/SA R# SA NC/SA B NC Q9 D9 SA NC K BW0# SA NC NC CQ Q8 C NC NC D10 VSS SA SA SA VSS NC Q7 D8 D NC D11 Q10 VSS VSS VSS VSS VSS NC NC D7 E NC NC Q11 VDDQ VSS VSS VSS VDDQ NC D6 Q6 F NC Q12 D12 VDDQ VDD VSS VDD VDDQ NC NC Q5 G NC D13 Q13 VDDQ VDD VSS VDD VDDQ NC NC D5 H Doff# VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ J NC NC D14 VDDQ VDD VSS VDD VDDQ NC Q4 D4 K NC NC Q14 VDDQ VDD VSS VDD VDDQ NC D3 Q3 L NC Q15 D15 VDDQ VSS VSS VSS VDDQ NC NC Q2 M NC NC D16 VSS VSS VSS VSS VSS NC Q1 D2 N NC D17 Q16 VSS SA SA SA VSS NC NC D1 P NC NC Q17 SA SA QVLD SA SA NC D0 Q0 TDO TCK SA SA SA ODT SA SA SA TMS TDI R Notes: 1. The following balls are reserved for higher densities: 10A for 72M, 2A for 144Mb, and 7A for 288Mb. Integrated Silicon Solution, Inc.- www.issi.com Rev. B 12/15/2014 2 IS61QDPB22M18A/A1/A2 IS61QDPB21M36A/A1/A2 Ball Description Symbol Type K, K# Input CQ, CQ# Output Doff# Input QVLD Output SA Input D0 - Dn Input Q0 - Qn Output W# Input R# Input BWx# Input Description Input clock: This input clock pair registers address and control inputs on the rising edge of K, and registers data on the rising edge of K and the rising edge of K#. K# is ideally 180 degrees out of phase with K. All synchronous inputs must meet setup and hold times around the clock rising edges. These balls cannot remain VREF level. Synchronous echo clock outputs: The edges of these outputs are tightly matched to the synchronous data outputs and can be used as a data valid indication. These signals are free running clocks and do not stop when Q tri-states. DLL disable and reset input : when low, this input causes the DLL to be bypassed and reset the previous DLL information. When high, DLL will start operating and lock the frequency after tCK lock time. The device behaves in one clock read latency mode when the DLL is turned off. In this mode, the device can be operated at a frequency of up to 167 MHz. Valid output indicator: The Q Valid indicates valid output data. QVLD is edge aligned with CQ and CQ#. Synchronous address inputs: These inputs are registered and must meet the setup and hold times around the rising edge of K. These inputs are ignored when device is deselected. Synchronous data inputs: Input data must meet setup and hold times around the rising edges of K and K# during WRITE operations. See BALL CONFIGURATION figures for ball site location of individual signals. The x18 device uses D0~D17. D18~D35 should be treated as NC pin. The x36 device uses D0~D35. Synchronous data outputs: Output data is synchronized to the respective CQ and CQ#, or to the respective K and K# if C and /C are tied to high. This bus operates in response to R# commands. See BALL CONFIGURATION figures for ball site location of individual signals. The x18 device uses Q0~Q17. Q18~Q35 should be treated as NC pin. The x36 device uses Q0~Q35. Synchronous write: When low, this input causes the address inputs to be registered and a WRITE cycle to be initiated. This input must meet setup and hold times around the rising edge of K. Synchronous read: When low, this input causes the address inputs to be registered and a READ cycle to be initiated. This input must meet setup and hold times around the rising edge of K. Synchronous byte writes: When low, these inputs cause their respective byte to be registered and written during WRITE cycles. These signals are sampled on the same edge as the corresponding data and must meet setup and hold times around the rising edges of K and #K for each of the two rising edges comprising the WRITE cycle. See Write Truth Table for signal to data relationship. HSTL input reference voltage: Nominally VDDQ/2, but may be adjusted to improve system noise margin. Provides a reference voltage for the HSTL input buffers. Power supply: 1.8 V nominal. See DC Characteristics and Operating Conditions for range. VDD Input reference Power VDDQ Power Power supply: Isolated output buffer supply. Nominally 1.5 V. See DC Characteristics and Operating Conditions for range. VSS Ground Ground of the device ZQ Input Output impedance matching input: This input is used to tune the device outputs to the system data bus impedance. Q and CQ output impedance are set to 0.2xRQ, where RQ is a resistor from this ball to ground. This ball can be connected directly to VDDQ, which enables the minimum impedance mode. This ball cannot be connected directly to VSS or left unconnected. In ODT (On Die Termination) enable devices, the ODT termination values tracks the value of RQ. The ODT range is selected by ODT control input. TMS, TDI, TCK Input IEEE1149.1 input pins for JTAG. TDO Output IEEE1149.1 output pins for JTAG. NC N/A No connect: These signals should be left floating or connected to ground to improve package heat dissipation. ODT Input ODT control; Refer to SRAM features for the details. VREF Integrated Silicon Solution, Inc.- www.issi.com Rev. B 12/15/2014 3 IS61QDPB22M18A/A1/A2 IS61QDPB21M36A/A1/A2 SRAM Features description Block Diagram 36 (18) D (Data-In) Data Register 36 (18) 36 (18) Write Driver 72 (36) Output Register R# W# 4 (2) 72 (36) Output Driver 1M x 36 (2M x 18) Memory Array Output Select 19 (20) Sense Amplifiers 36 (18) Address Register Address Decoder 19 (20) Address Q (Data-out) 2 CQ, CQ# (Echo Clocks) Control Logic BWx# K K# C C# Clock Generator Select Output Control Doff# Note: Numerical values in parentheses refer to the x18 device configuration. Read Operations The SRAM operates continuously in a burst-of-two mode. Read cycles are started by registering R# in active low state at the rising edge of the K clock. R# can be activated every other cycle because two full cycles are required to complete the burst of two in DDR mode. A set of free-running echo clocks, CQ and CQ#, are produced internally with timings identical to the data-outs. The echo clocks can be used as data capture clocks by the receiver device. The data corresponding to the first address is clocked two and half cycles later by the rising edge of the K# clock. The data corresponding to the second burst is clocked three cycles later by the following rising edge of the K clock. A NOP operation (R# is high) does not terminate the previous read. Write Operations Write operations can also be initiated at every rising edge of the K clock with first data whenever W# is low. The write address is provided half cycle with second data later, registered by the rising edge of K#, so the write always occurs in bursts of two. The write data is provided in an ‘early write’ mode; that is, the data-in corresponding to the first address of the burst, is presented half cycle before the rising edge of the following K clock. The data-in corresponding to the second write burst address follows next, registered by the rising edge of K#. The data-in provided for writing is initially kept in write buffers. The information in these buffers is written into the array on the third write cycle. A read cycle to the last write address produces data from the write buffers. Similarly, a read address followed by the same write address produces the latest write data. The SRAM maintains data coherency. During a write, the byte writes independently control which byte of any of the four burst addresses is written (see X18/X36 Write Truth Tables and Timing Reference Diagram for Truth Table). Integrated Silicon Solution, Inc.- www.issi.com Rev. B 12/15/2014 4 IS61QDPB22M18A/A1/A2 IS61QDPB21M36A/A1/A2 Whenever a write is disabled (W# is high at the rising edge of K), data is not written into the memory. RQ Programmable Impedance An external resistor, RQ, must be connected between the ZQ pin on the SRAM and VSS to enable the SRAM to adjust its output driver impedance. The value of RQ must be 5x the value of the intended line impedance driven by the SRAM. For example, an RQ of 250Ω results in a driver impedance of 50Ω. The allowable range of RQ to guarantee impedance matching is between 175Ω and 350Ω at VDDQ=1.5V. The RQ resistor should be placed less than two inches away from the ZQ ball on the SRAM module. The capacitance of the loaded ZQ trace must be less than 7.5pF. The ZQ pin can also be directly connected to VDDQ to obtain a minimum impedance setting. ZQ must never be connected to VSS. Programmable Impedance and Power-Up Requirements Periodic readjustment of the output driver impedance is necessary as the impedance is greatly affected by drifts in supply voltage and temperature. During power-up, the driver impedance is in the middle of allowable impedances value. The final impedance value is achieved within 1024 clock cycles. Depth Expansion Separate input and output ports enable easy depth expansion, as each port can be selected and deselected independently. Read and write operations can occur simultaneously without affecting each other. Also, all pending read and write transactions are always completed prior to deselecting the corresponding port. Valid Data Indicator (QVLD) A data valid pin (QVLD) is available to assist in high-speed data output capture. This output signal is edge-aligned with the echo clock and is asserted HIGH half a cycle before valid read data is available and asserted LOW half a cycle before the final valid read data arrives. Delay Locked Loop (DLL) Delay Locked Loop (DLL) is a new system to align the output data coincident with clock rising or falling edge to enhance the output valid timing characteristics. It is locked to the clock frequency and is constantly adjusted to match the clock frequency. Therefore device can have stable output over the temperature and voltage variation. DLL has a limitation of locking range and jitter adjustment which are specified as tKHKH and tKCvar respectively in the AC timing characteristics. In order to turn this feature off, applying logic low to the Doff# pin will bypass this. In the DLL off mode, the device behaves with one clock cycle latency and a longer access time which is known in DDR-I or legacy QUAD mode. The DLL can also be reset without power down by toggling Doff# pin low to high or stopping the input clocks K and K# for a minimum of 30ns.(K and K# must be stayed either at higher than VIH or lower than VIL level. Remaining Vref is not permitted.) DLL reset must be issued when power up or when clock frequency changes abruptly. After DLL being reset, it gets locked after 2048 cycles of stable clock. ODT (On Die Termination) On Die Termination (ODT) is a feature that allows a SRAM to change input resistive termination condition by ODT pin which function can have three status, High, Low, and Floating. Each status can have different ODT termination value Integrated Silicon Solution, Inc.- www.issi.com Rev. B 12/15/2014 5 IS61QDPB22M18A/A1/A2 IS61QDPB21M36A/A1/A2 that tracks the value of RQ (Refer to the table of Fig1) and ODT of QUADP is always turned on during the read and write function after ODT level to connect with ODT resistor is forced. Fig1. Functional representation of ODT SRAM In/Out Buffer VDDQ VDDQ ODT=L ODT=H R1x2 R2x2 ODT=Floating R3x2 PAD R1x2 R2x2 ODT=L ODT=H VSS Option1 VDDQ 3 Option24 VSS R1 0.3x RQ1 ODT disable R3x2 ODT=Floating VSS R2 0.6x RQ2 0.6x RQ2 R3 0.6x RQ2 ODT disable Notes 1. Allowable range of RQ to guarantee impedance matching a tolerance of ±20% is 175Ω