IS61VPS102436A-166TQL

IS61vPS102436A IS61lPS102436A IS61vPS204818A IS61lPS204818A 1Mb x 36, 2Mb x 18 36Mb SYNCHRONOUS PIPELINED, Single CYCLE DESELECT STATIC RAM FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs and data outputs • Auto Power-down during deselect • Single cycle deselect • Snooze MODE for reduced-power standby • Power Supply LPS: Vdd 3.3V + 5%, Vddq 3.3V/2.5V + 5% VPS: Vdd 2.5V + 5%, Vddq 2.5V + 5% • JEDEC 100-Pin TQFP and 165-ball PBGA packages • Lead-free available JUNE 2010 DESCRIPTION The  ISSI IS61LPS/VPS102436A and IS61LPS/VPS 204818A are high-speed, low-power synchronous static RAMs designed to provide burstable, high-performance memory for communication and networking applications. The IS61LPS/VPS102436A is organized as 1,048,476 words by 36 bits.The IS61LPS/VPS204818A is organized as 2M-word by 18 bits. Fabricated with ISSI's advanced CMOS technology, the device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers controlled by a positiveedge-triggered single clock input. Write cycles are internally self-timed and are initiated by the rising edge of the clock input. Write cycles can be one to four bytes wide as controlled by the write control inputs. Separate byte enables allow individual bytes to be written. The byte write operation is performed by using the byte write enable (BWE) input combined with one or more individual byte write signals (BWx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the byte write controls. Bursts can be initiated with either ADSP (Address Status Processor) or ADSC (Address Status Cache Controller) input pins. Subsequent burst addresses can be generated internally and controlled by the ADV (burst address advance) input pin. The mode pin is used to select the burst sequence order, Linear burst is achieved when this pin is tied LOW. Interleave burst is achieved when this pin is tied HIGH or left floating. FAST ACCESS TIME Symbol tkq tkc Parameter Clock Access Time Cycle Time Frequency 200 3.1 5 200 166 3.5 6 166 Units ns ns MHz Copyright © 2010 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc. Rev.  C 05/27/2010 1 IS61VPS102436A,  IS61LPS102436A, IS61VPS204818A, IS61LPS204818A BLOCK DIAGRAM MODE Q0 CLK CLK A0 BINARY COUNTER ADSC ADSP A Q1 CE ADV A1 A0' A1' 1Mx36; 2Mx18 MEMORY ARRAY CLR 20/21 D Q 18/19 20/21 ADDRESS REGISTER CE CLK 36, or 18 D GW BWE BW(a-h) x18: a,b x36: a-d 36, or 18 Q DQ(a-h) BYTE WRITE REGISTERS CLK CE 2/4/8 CE2 D Q ENABLE REGISTER CE2 INPUT REGISTERS CLK OUTPUT REGISTERS CLK 36, or 18 DQa - DQd OE CE CLK D ZZ POWER DOWN Q ENABLE DELAY REGISTER CLK OE 2 Integrated Silicon Solution, Inc. Rev.  C 05/27/2010 IS61VPS102436A,  IS61LPS102436A, IS61VPS204818A, IS61LPS204818A 165-pin BGA 165-Ball, 13x15 mm BGA 1mm Ball Pitch, 11x15 Ball Array Bottom view Integrated Silicon Solution, Inc. Rev.  C 05/27/2010 3 IS61VPS102436A,  IS61LPS102436A, IS61VPS204818A, IS61LPS204818A 165 PBGA PACKAGE PIN CONFIGURATION 1M x 36 (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 A NC A CE BWc BWb CE2 BWE ADSC ADV A NC B NC A CE2 BWd BWa CLK GW OE ADSP A NC C DQPc NC Vddq Vss Vss Vss Vss Vss Vddq NC DQPb D DQc DQc Vddq Vdd Vss Vss Vss Vdd Vddq DQb DQb E DQc DQc Vddq Vdd Vss Vss Vss Vdd Vddq DQb DQb F DQc DQc Vddq Vdd Vss Vss Vss Vdd Vddq DQb DQb G DQc DQc Vddq Vdd Vss Vss Vss Vdd Vddq DQb DQb H NC NC NC Vdd Vss Vss Vss Vdd NC NC ZZ J DQd DQd Vddq Vdd Vss Vss Vss Vdd Vddq DQa DQa K DQd DQd Vddq Vdd Vss Vss Vss Vdd Vddq DQa DQa L DQd DQd Vddq Vdd Vss Vss Vss Vdd Vddq DQa DQa M DQd DQd Vddq Vdd Vss Vss Vss Vdd Vddq DQa DQa N DQPd NC Vddq Vss NC A NC Vss Vddq NC DQPa P NC NC A A NC A1* NC A A A A R MODE A A A NC A 0* NC A A A A Note: * A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired. PIN DESCRIPTIONS Symbol A Pin Name Address Inputs Symbol Pin Name BWE Byte Write Enable A0, A1 ADV ADSP Synchronous Burst Address Inputs Synchronous Burst Address Advance Address Status Processor OE Output Enable ZZ Power Sleep Mode MODE Burst Sequence Selection ADSC GW Address Status Controller Global Write Enable CLK CE, CE2, CE2 Synchronous Clock Synchronous Chip Select NC DQx DQPx Vdd Vddq No Connect Data Inputs/Outputs Data Inputs/Outputs 3.3V/2.5V Power Supply BWx (x=a,b,c,d) Synchronous Byte Write Controls 4 Isolated Output Power Supply 3.3V/2.5V Vss Ground Integrated Silicon Solution, Inc. Rev.  C 05/27/2010 IS61VPS102436A,  IS61LPS102436A, IS61VPS204818A, IS61LPS204818A 165 PBGA PACKAGE PIN CONFIGURATION 2M x 18 (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 A NC A CE BWb NC CE2 BWE ADSC ADV A A B NC A CE2 NC BWa CLK GW OE ADSP A NC C NC NC Vddq Vss Vss Vss Vss Vss Vddq NC DQPa D NC DQb Vddq Vdd Vss Vss Vss Vdd Vddq NC DQa E NC DQb Vddq Vdd Vss Vss Vss Vdd Vddq NC DQa DQa F NC DQb Vddq Vdd Vss Vss Vss Vdd Vddq NC G NC DQb Vddq Vdd Vss Vss Vss Vdd Vddq NC DQa H NC NC NC Vdd Vss Vss Vss Vdd NC NC ZZ J DQb NC Vddq Vdd Vss Vss Vss Vdd Vddq DQa NC K DQb NC Vddq Vdd Vss Vss Vss Vdd Vddq DQa NC L DQb NC Vddq Vdd Vss Vss Vss Vdd Vddq DQa NC M DQb NC Vddq Vdd Vss Vss Vss Vdd Vddq DQa NC N DQPb NC Vddq Vss NC A NC Vss Vddq NC NC P NC NC A A NC A1* NC A A A A R MODE A A A NC A0* NC A A A A Note: * A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired. PIN DESCRIPTIONS Symbol A Pin Name Address Inputs Symbol BWE Byte Write Enable A0, A1 ADV ADSP Synchronous Burst Address Inputs Synchronous Burst Address Advance Address Status Processor OE Output Enable ZZ Power Sleep Mode MODE Burst Sequence Selection ADSC GW Address Status Controller Global Write Enable CLK CE, CE2, CE2 Synchronous Clock Synchronous Chip Select No Connect Data Inputs/Outputs Data Inputs/Outputs 3.3V/2.5V Power Supply BWx (x=a,b) Synchronous Byte Write Controls NC DQx DQPx Vdd Vddq Integrated Silicon Solution, Inc. Rev.  C 05/27/2010 Pin Name Isolated Output Power Supply 3.3V/2.5V Vss Ground 5 IS61VPS102436A,  IS61LPS102436A, IS61VPS204818A, IS61LPS204818A PIN CONFIGURATION A A CE CE2 BWd BWc BWb BWa CE2 VDD VSS CLK GW BWE OE ADSC ADSP ADV A A 100-Pin TQFP DQPc DQPb DQb DQb VDDQ VSS DQb DQb DQb DQb VSS VDDQ DQb DQb VSS NC VDD ZZ DQa DQa VDDQ VSS DQa DQa DQa DQa VSS VDDQ DQa DQa DQPa MODE A A A A A1 A0 NC A VSS VDD A A A A A A A A A DQc DQc VDDQ VSS DQc DQc DQc DQc VSS VDDQ DQc DQc NC VDD NC VSS DQd DQd VDDQ VSS DQd DQd DQd DQd VSS VDDQ DQd DQd DQPd 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 10 71 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 1M x 36 PIN DESCRIPTIONS A0, A1 A Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus. Synchronous Address Inputs ADSC Synchronous Controller Address Status ADSP Synchronous Processor Address Status ADV Synchronous Burst Address Advance BWa-BWd Synchronous Byte Write Enable BWE Synchronous Byte Write Enable CE, CE2, CE2 Synchronous Chip Enable CLK 6 DQa-DQd Synchronous Data Input/Output DQPa-DQPd Parity Data Input/Output GW MODE Synchronous Global Write Enable Burst Sequence Mode Selection OE Output Enable Vdd 3.3V/2.5V Power Supply Vddq Isolated Output Buffer Supply: 3.3V/2.5V Ground Snooze Enable Vss ZZ Synchronous Clock Integrated Silicon Solution, Inc. Rev.  C 05/27/2010 IS61VPS102436A,  IS61LPS102436A, IS61VPS204818A, IS61LPS204818A PIN CONFIGURATION A A CE CE2 NC NC BWb BWa CE2 VDD VSS CLK GW BWE OE ADSC ADSP ADV A A 100-Pin TQFP 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 10 71 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 A NC NC VDDQ VSS NC DQPa DQa DQa VSS VDDQ DQa DQa VSS NC VDD ZZ DQa DQa VDDQ VSS DQa DQa NC NC VSS VDDQ NC NC NC MODE A A A A A1 A0 NC A VSS VDD A A A A A A A A A NC NC NC VDDQ VSS NC NC DQb DQb VSS VDDQ DQb DQb NC VDD NC VSS DQb DQb VDDQ VSS DQb DQb DQPb NC VSS VDDQ NC NC NC 2M x 18 PIN DESCRIPTIONS A0, A1 Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus. A Synchronous Address Inputs Synchronous Controller Address Status ADSC ADSP Synchronous Processor Address Status ADV Synchronous Burst Address Advance BWa-BWb Synchronous Byte Write Enable BWE Synchronous Byte Write Enable CE, CE2, CE2 Synchronous Chip Enable CLK Synchronous Clock DQa-DQb Synchronous Data Input/Output Integrated Silicon Solution, Inc. Rev.  C 05/27/2010 DQPa-DQPb Parity Data I/O; DQPa is parity for DQa1-8; DQPb is parity for DQb1-8 GW MODE Synchronous Global Write Enable Burst Sequence Mode Selection OE Vdd Vddq Vss ZZ Output Enable 3.3V/2.5V Power Supply Isolated Output Buffer Supply: 3.3V/2.5V Ground Snooze Enable 7 IS61VPS102436A,  IS61LPS102436A, IS61VPS204818A, IS61LPS204818A TRUTH TABLE(1-8)  (3CE option) OPERATION Deselect Cycle, Power-Down Deselect Cycle, Power-Down Deselect Cycle, Power-Down Deselect Cycle, Power-Down Deselect Cycle, Power-Down Snooze Mode, Power-Down Read Cycle, Begin Burst Read Cycle, Begin Burst Write Cycle, Begin Burst Read Cycle, Begin Burst Read Cycle, Begin Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Write Cycle, Continue Burst Write Cycle, Continue Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Write Cycle, Suspend Burst Write Cycle, Suspend Burst ADDRESS CE None H None L None L None L None L None X External L External L External L External L External L Next X Next X Next H Next H Next X Next H Current X Current X Current H Current H Current X Current H CE2 X X H X H X L L L L L X X X X X X X X X X X X CE2 X L X L X X H H H H H X X X X X X X X X X X X ZZ L L L L L H L L L L L L L L L L L L L L L L L ADSP ADSC ADV WRITE OE X L X X X L X X X X L X X X X H L X X X H L X X X X X X X X L X X X L L X X X H H L X L X H L X H L H L X H H H H L H L H H L H H X H L H L X H L H H H H L L X X H L L X H H H H L H H H H H X H H H L X H H H H H H H L X X H H L X CLK L-H L-H L-H L-H L-H X L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H DQ High-Z High-Z High-Z High-Z High-Z High-Z Q High-Z D Q High-Z Q High-Z Q High-Z D D Q High-Z Q High-Z D D NOTE: 1. X means “Don’t Care.” H means logic HIGH. L means logic LOW. 2. For WRITE, L means one or more byte write enable signals (BWa-h) and BWE are LOW or GW is LOW. WRITE = H for all BWx, BWE, GW HIGH. 3. BWa enables WRITEs to DQa’s and DQPa. BWb enables WRITEs to DQb’s and DQPb. BWc enables WRITEs to DQc’s  and DQPc. BWd enables WRITEs to DQd’s and DQPd. DQPa-DQPd are available on the x36 version. 4. All inputs except OE and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK. 5. Wait states are inserted by suspending burst. 6. For a WRITE operation following a READ operation, OE must be HIGH before the input data setup time and held HIGH during the input data hold time. 7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up. 8. ADSP LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more byte write enable signals and BWE LOW or GW LOW for the subsequent L-H edge of CLK. See WRITE timing diagram for clarification. 8 Integrated Silicon Solution, Inc. Rev.  C 05/27/2010 IS61VPS102436A,  IS61LPS102436A, IS61VPS204818A, IS61LPS204818A TRUTH TABLE(1-8)  (1CE option) NEXT CYCLE Deselected Read, Begin Burst Read, Begin Burst Write, Begin Burst Read, Begin Burst Read, Begin Burst Read, Continue Burst Read, Continue Burst Read, Continue Burst Read, Continue Burst Write, Continue Burst Write, Continue Burst Read, Suspend Burst Read, Suspend Burst Read, Suspend Burst Read, Suspend Burst Write, Suspend Burst Write, Suspend Burst ADDRESS None External External External External External Next Next Next Next Next Next Current Current Current Current Current Current CE H L L L L L X X H H X H X X H H X H ADSP X L L H H H H H X X H X H H X X H X ADSC L X X L L L H H H H H H H H H H H H ADV X X X X X X L L L L L L H H H H H H WRITE X X X L H H H H H H L L H H H H L L OE X L H X L H L H L H X X L H L H X X DQ High-Z Q High-Z D Q High-Z Q High-Z Q High-Z D D Q High-Z Q High-Z D D NOTE: 1. X means “Don’t Care.” H means logic HIGH. L means logic LOW. 2. For WRITE, L means one or more byte write enable signals (BWa-h) and BWE are LOW or GW is LOW. WRITE = H for all BWx, BWE, GW HIGH. 3. BWa enables WRITEs to DQa’s and DQPa. BWb enables WRITEs to DQb’s and DQPb. BWc enables WRITEs to DQc’s  and DQPc. BWd enables WRITEs to DQd’s and DQPd. DQPa-DQPd are available on the x36 version. 4. All inputs except OE and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK. 5. Wait states are inserted by suspending burst. 6. For a WRITE operation following a READ operation, OE must be HIGH before the input data setup time and held HIGH during the input data hold time. 7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up. 8. ADSP LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more byte write enable signals and BWE LOW or GW LOW for the subsequent L-H edge of CLK. See WRITE timing diagram for clarification. PARTIAL TRUTH TABLE Function Read Read Write Byte 1 Write All Bytes Write All Bytes GW H H H H L BWE H L L L X Integrated Silicon Solution, Inc. Rev.  C 05/27/2010 BWa X H L L X BWb X H H L X BWc X H H L X BWd X H H L X 9 IS61VPS102436A,  IS61LPS102436A, IS61VPS204818A, IS61LPS204818A INTERLEAVED BURST ADDRESS TABLE (MODE = Vdd or No Connect) External Address A1  A0 00 01 10 11 1st Burst Address A1  A0 01 00 11 10 2nd Burst Address A1  A0 10 11 00 01 3rd Burst Address A1  A0 11 10 01 00 LINEAR BURST ADDRESS TABLE (MODE = Vss) 0,0 A1', A0' = 1,1     0,1 1,0 ABSOLUTE MAXIMUM RATINGS(1) Symbol Tstg Pd Iout Vin, Vout Vin Vdd Parameter Value Unit Storage Temperature –55 to +150 °C Power Dissipation 1.6 W Output Current (per I/O) 100 mA Voltage Relative to Vss for I/O Pins –0.5 to Vddq + 0.5 V Voltage Relative to Vss for –0.5 to Vdd + 0.5 V for Address and Control Inputs Voltage on Vdd Supply Relative to Vss –0.5 to 4.6 V Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. This device contains circuity to protect the inputs against damage due to high static voltages or electric fields; however, precautions may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. 3. This device contains circuitry that will ensure the output devices are in High-Z at power up. 10 Integrated Silicon Solution, Inc. Rev.  C 05/27/2010 IS61VPS102436A,  IS61LPS102436A, IS61VPS204818A, IS61LPS204818A OPERATING RANGE (IS61LPSXXXXX) Range Commercial Ambient Temperature Vdd Vddq 0°C to +70°C 3.3V + 5% 3.3V / 2.5V + 5% Industrial –40°C to +85°C 3.3V + 5% 3.3V / 2.5V + 5% OPERATING RANGE (IS61VPSXXXXX) Range Commercial Ambient Temperature Vdd Vddq 0°C to +70°C 2.5V + 5% 2.5V + 5% Industrial –40°C to +85°C 2.5V + 5% 2.5V + 5% DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Symbol Parameter Test Conditions Voh Output HIGH Voltage Ioh = –4.0 mA (3.3V) Ioh = –1.0 mA (2.5V) Vol Output LOW Voltage Iol = 8.0 mA (3.3V) Iol = 1.0 mA (2.5V) Vih Input HIGH Voltage Vil Input LOW Voltage Ili Input Leakage Current Vss ≤ Vin ≤ Vdd(1) Ilo Output Leakage Current Vss ≤ Vout ≤ Vddq, OE = Vih 3.3V Min. Max. 2.4 — — 0.4 2.0 -0.3 -5 -5 Vdd + 0.3 0.8 5 5 2.5V Min. Max. 2.0 — — Unit V 0.4 V 1.7 Vdd + 0.3 -0.3 0.7 -5 5 -5 5 V V µA µA POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter Icc AC Operating Supply Current Isb Standby Current TTL Input Isbi Standby Current CMOS Input -200 MAX Test Conditions Temp. range x18 x36 Device Selected, Com. 450 450 OE = Vih, ZZ ≤ Vil, Ind. 475 475 All Inputs ≤ 0.2V or ≥ Vdd – 0.2V, typ.(2) 390 Cycle Time ≥ tkc min. Device Deselected, Com. 150 150 Vdd = Max., Ind. 160 160 All Inputs ≤ Vil or ≥ Vih, ZZ ≤ Vil, f = Max. Device Deselected, Com. 110 110 Vdd = Max., Ind. 140 140 Vin ≤ Vss + 0.2V or ≥Vdd – 0.2V typ.(2) 75 f=0 -166 MAX x18 x36 400 400 mA 450 450 340 140 150 140 150 Unit mA 110 110 140 140 75 mA Note: 1. MODE pin has an internal pullup and should be tied to Vdd or Vss. It exhibits ±100µA maximum leakage current when tied to ≤ Vss + 0.2V or ≥ Vdd – 0.2V. 2. Typical values are measured at Vcc = 3.3V, Ta = 25oC and not 100% tested. Integrated Silicon Solution, Inc. Rev.  C 05/27/2010 11 IS61VPS102436A,  IS61LPS102436A, IS61VPS204818A, IS61LPS204818A CAPACITANCE(1,2) Symbol Cin Cout Parameter Input Capacitance Input/Output Capacitance Conditions Vin = 0V Vout = 0V Max. 6 8 Unit pF pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: Ta = 25°C, f = 1 MHz, Vdd = 3.3V. 3.3V I/O AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0V to 3.0V 1.5 ns 1.5V See Figures 1 and 2 AC TEST LOADS 317 Ω 3.3V ZO = 50Ω Output 50Ω 1.5V Figure 1 12 OUTPUT 5 pF Including jig and scope 351 Ω Figure 2 Integrated Silicon Solution, Inc. Rev.  C 05/27/2010 IS61VPS102436A,  IS61LPS102436A, IS61VPS204818A, IS61LPS204818A 2.5V I/O AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0V to 2.5V 1.5 ns 1.25V See Figures 3 and 4 2.5 I/O OUTPUT LOAD EQUIVALENT 317 Ω 2.5V ZO = 50Ω Output 50Ω 1.25V Figure 3 Integrated Silicon Solution, Inc. Rev.  C 05/27/2010 OUTPUT 5 pF Including jig and scope 351 Ω Figure 4 13 IS61VPS102436A,  IS61LPS102436A, IS61VPS204818A, IS61LPS204818A READ/WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range) Symbol Parameter fmax Clock Frequency tkc Cycle Time tkh Clock High Time tkl Clock Low Time tkq Clock Access Time tkqx(2) Clock High to Output Invalid tkqlz(2,3) Clock High to Output Low-Z tkqhz(2,3) Clock High to Output High-Z toeq Output Enable to Output Valid toeqx(2) Output Disable to Output Invalid toelz(2,3) Output Enable to Output Low-Z toehz Output Disable to Output High-Z tas Address Setup Time tss Address Status Setup Time tws Read/Write Setup Time tces Chip Enable Setup Time tavs Address Advance Setup Time tds Data Setup Time tah Address Hold Time tsh Address Status Hold Time twh Write Hold Time tceh Chip Enable Hold Time tavh Address Advance Hold Time tdh Data Hold Time tpds ZZ High to Power Down tpus ZZ Low to Power Down (2,3) -200 Min. Max. — 200 5 — 2 — 2 — — 3.1 1.5 — 1 — — 3.0 — 3.1 0 — 0 — 1.4 1.4 1.4 1.4 1.4 1.4 0.4 0.4 0.4 0.4 0.4 0.4 — — — 3.0 — — — — — — — — — — — — 2 2 -166 Min. — 6 2.4 2.4 — 1.5 1 — — 0 Max. 166 — — — 3.5 — — 3.4 3.5 — Unit MHz ns ns ns ns ns ns ns ns ns 0 — 1.5 1.5 1.5 1.5 1.5 1.5 0.5 0.3 0.5 0.5 0.5 0.5 — — — 3.4 — — — — — — — — — — — — 2 2 ns ns ns ns ns ns ns ns ns ns ns ns ns ns cyc cyc Note: 1. Configuration signal MODE is static and must not change during normal operation. 2. Guaranteed but not 100% tested. This parameter is periodically sampled. 3. Tested with load in Figure 2. 14 Integrated Silicon Solution, Inc. Rev.  C 05/27/2010 IS61VPS102436A,  IS61LPS102436A, IS61VPS204818A, IS61LPS204818A READ/WRITE CYCLE TIMING tKC CLK tSS tSH tKH tKL ADSP is blocked by CE inactive ADSP tSS tSH ADSC initiate read ADSC tAVH tAVS Suspend Burst ADV tAS Address tAH RD1 RD3 RD2 tWS tWH tWS tWH GW BWE BWx tCES tCEH tCES tCEH tCES tCEH CE Masks ADSP CE Unselected with CE2 CE2 and CE2 only sampled with ADSP or ADSC CE2 CE2 tOEHZ tOEQ OE DATAOUT tKQX tOEQX tOELZ High-Z 1a 2a 2b 2c tKQLZ 2d tKQHZ tKQ DATAIN High-Z Pipelined Read Single Read Integrated Silicon Solution, Inc. Rev.  C 05/27/2010 Burst Read Unselected 15 IS61VPS102436A,  IS61LPS102436A, IS61VPS204818A, IS61LPS204818A WRITE CYCLE TIMING tKC CLK tSS tSH tKH tKL ADSP is blocked by CE inactive ADSP ADSC initiate Write ADSC ADV must be inactive for ADSP Write tAVS tAVH ADV tAS Address tAH WR1 WR3 WR2 tWS tWH tWS tWH tWS tWH GW BWE WR1 BWx tCES tCEH tCES tCEH tCES tCEH tWS tWH WR2 WR3 CE Masks ADSP CE Unselected with CE2 CE2 and CE2 only sampled with ADSP or ADSC CE2 CE2 OE DATAOUT High-Z tDS DATAIN High-Z Single Write 16 tDH 1a BW4-BW1 only are applied to first cycle of WR2 2a 2b 2c 2d Burst Write 3a Write Unselected Integrated Silicon Solution, Inc. Rev.  C 05/27/2010 IS61VPS102436A,  IS61LPS102436A, IS61VPS204818A, IS61LPS204818A SNOOZE MODE ELECTRICAL CHARACTERISTICS Symbol Isb2 tpds tpus tzzi trzzi Parameter Temperature Current during SNOOZE MODE Com. Ind. ZZ active to input ignored ZZ inactive to input sampled ZZ active to SNOOZE current ZZ inactive to exit SNOOZE current Conditions ZZ ≥ Vih Min. — — — 2 — 0 Max. 60 90 2 — 2 — Unit mA cycle cycle cycle ns SNOOZE MODE TIMING CLK tPDS ZZ setup cycle tPUS ZZ recovery cycle ZZ tZZI Isupply ISB2 tRZZI All Inputs (except ZZ) Deselect or Read Only Deselect or Read Only Normal operation cycle Outputs (Q) High-Z Don't Care Integrated Silicon Solution, Inc. Rev.  C 05/27/2010 17 IS61VPS102436A,  IS61LPS102436A, IS61VPS204818A, IS61LPS204818A ORDERING INFORMATION (3.3V core/2.5V-3.3V I/O) Commercial Range: 0°C to +70°C Configuration 1Mx36 Frequency Order Part Number Package 166 IS61LPS102436A-166TQ IS61LPS102436A-166TQL IS61LPS102436A-166B3 100 TQFP 100 TQFP, Lead-free 165 PBGA 166 IS61LPS204818A-166TQ IS61LPS204818A-166TQL IS61LPS204818A-166B3 100 TQFP 100 TQFP, Lead-free 165 PBGA Order Part Number Package 166 IS61LPS102436A-166TQI IS61LPS102436A-166TQLI IS61LPS102436A-166B3I IS61LPS102436A-166B3LI 100 TQFP 100 TQFP, Lead-free 165 PBGA 165 PBGA, Lead-free 166 IS61LPS204818A-166TQI IS61LPS204818A-166B3I 100 TQFP 165 PBGA 2Mx18 Industrial Range: -40°C to +85°C Configuration 1Mx36 Frequency 2Mx18 18 Integrated Silicon Solution, Inc. Rev.  C 05/27/2010 IS61VPS102436A,  IS61LPS102436A, IS61VPS204818A, IS61LPS204818A ORDERING INFORMATION (2.5V core/2.5V I/O) Commercial Range: 0°C to +70°C Configuration 1Mx36 Frequency Order Part Number Package 166 IS61VPS102436A-166TQ IS61VPS102436A-166TQL IS61VPS102436A-166B3 100 TQFP 100 TQFP, Lead-free 165 PBGA 166 IS61VPS204818A-166TQ IS61VPS204818A-166TQL IS61VPS204818A-166B3 100 TQFP 100 TQFP, Lead-free 165 PBGA Order Part Number Package IS61VPS204818A-166TQI IS61VPS204818A-166B3I 100 TQFP 165 PBGA 2Mx18 Industrial Range: -40°C to +85°C Configuration 2Mx18 Frequency 166 Integrated Silicon Solution, Inc. Rev.  C 05/27/2010 19 IS61VPS102436A,  IS61LPS102436A, IS61VPS204818A, IS61LPS204818A 20 Integrated Silicon Solution, Inc. Rev.  C 05/27/2010 Integrated Silicon Solution, Inc. Rev.  C 05/27/2010 Package Outline 1. CONTROLLING DIMENSION : MM . NOTE : 08/28/2008 IS61VPS102436A,  IS61LPS102436A, IS61VPS204818A, IS61LPS204818A 21