IS61WV1288EEBLL-10TLI

IS61WV1288EEBLL IS64WV1288EEBLL 128K x 8 HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM WITH ECC MAY 2020 DESCRIPTION The ISSI IS61/64WV1288EEBLL is a high-speed, FEATURES • High-speed access time: 8, 10 ns • Low Active Power: 85 mW (typical) • Low Standby Power: 7 mW (typical) CMOS standby • Single power supply • Fully static operation: no clock or refresh required • Three state outputs • Industrial and Automotive temperature support • Lead-free available • Error Detection and Error Correction 1,048,576-bit static RAMs organized as 131,072 words by 8 bits. It is fabricated using ISSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields high-performance and low power consumption devices. When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs, CE and OE. The active LOW Write Enable (WE) controls both writing and reading of the memory. The IS61/64WV1288EEBLL is packaged in the JEDEC standard 32-pin SOJ, TSOP-II, sTSOP-I, and 48-ball BGA (6mmx8mm). FUNCTIONAL BLOCK DIAGRAM A0-A16 Memory Array (128Kx8) Decoder 8 8 IO0-7 I/O Data Circuit /CE /OE /WE Control Circuit 8 ECC Array (128Kx4) 4 12 ECC Column I/O Copyright © 2020 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc. — www.issi.com 1 Rev. B1 05/27/2020 IS61/64WV1288EEBLL PIN CONFIGURATION PIN CONFIGURATION 32-Pin SOJ 32-Pin TSOP (Type II) (T) 32-Pin sTSOP (Type I) (H) A0 1 32 A16 A1 2 31 A15 A2 3 30 A14 A3 4 29 A13 CE 5 28 OE I/O0 6 27 I/O7 I/O1 7 26 I/O6 VDD 8 25 GND GND 9 24 VDD I/O2 10 23 I/O5 I/O3 11 22 I/O4 WE 12 21 A12 A4 13 20 A11 A5 14 19 A10 A6 15 18 A9 A7 16 17 A8 PIN DESCRIPTIONS A0-A16 Address Inputs CE Chip Enable Input OE Output Enable Input WE Write Enable Input I/O0-I/O7 Bidirectional Ports Vdd Power GND Ground 2 A0 A1 A2 A3 CE I/O0 I/O1 VDD GND I/O2 I/O3 WE A4 A5 A6 A7 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A16 A15 A14 A13 OE I/O7 I/O6 GND VDD I/O5 I/O4 A12 A11 A10 A9 A8 PIN CONFIGURATION 48-mini BGA (B) (6 mm x 8 mm) 1 2 3 4 5 6 A NC OE A2 A6 A7 NC B I/O0 NC A1 A5 CE I/O7 C I/O1 NC A0 A4 NC I/O6 D GND NC NC A3 NC VDD E VDD NC NC NC NC GND F I/O2 NC A14 A11 I/O4 I/O5 G I/O3 NC A15 A12 WE A8 H NC A10 A16 A13 A9 NC Integrated Silicon Solution, Inc. — www.issi.com Rev. B1 05/27/2020 IS61/64WV1288EEBLL ABSOLUTE MAXIMUM RATINGS(1) Symbol Parameter Vterm Terminal Voltage with Respect to GND Vdd Vdd Relates to GND Tstg Storage Temperature Pt Power Dissipation Value –0.5 to Vdd + 0.5 –0.3 to 4.0 –65 to +150 1.0 1 Unit V V °C W 2 Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. CAPACITANCE(1,2) Symbol Cin CI/O Parameter Conditions Input Capacitance Input/Output Capacitance Vin = 0V Vout = 0V Max. Unit 6 pF 8 pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: Ta = 25°C, f = 1 MHz, Vdd = 3.3V. ERROR DETECTION AND ERROR CORRECTION • • • • Independent ECC with hamming code for each byte Detect and correct one bit error per byte Better reliability than parity code schemes which can only detect an error but not correct an error Backward Compatible: Drop in replacement to current in industry standard devices (without ECC) TRUTH TABLE Mode CE WE Not Selected H X (Power-down) Output Disabled L H Read L H Write L L High-Z Dout Din 6 7 8 11 IS61WV1288EEBLL Vdd (8, 10ns) 2.4V-3.6V — — IS64WV1288EEBLL Vdd (8, 10ns) — 2.4V-3.6V (8,10ns) 2.4V-3.6V (10ns) Note: 1. Contact SRAM@issi.com for 1.8V option Integrated Silicon Solution, Inc. — www.issi.com 3 Rev. B1 05/27/2020 5 10 Icc Icc Icc OPERATING RANGE (Vdd)1 Range Ambient Temperature Industrial –40°C to +85°C Automotive (A1) –40°C to +85°C Automotive (A3) –40°C to +125°C 4 9 OE I/O Operation Vdd Current X High-Z Isb1, Isb2 H L X 3 12 IS61/64WV1288EEBLL DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Vdd = 3.3V + 10% Symbol Voh Vol Vih Vil Ili Ilo Parameter Test Conditions Output HIGH Voltage Vdd = Min., Ioh = –4.0 mA Output LOW Voltage Vdd = Min., Iol = 8.0 mA Input HIGH Voltage Input LOW Voltage(1) Input Leakage GND ≤ Vin ≤ Vdd Output Leakage GND ≤ Vout ≤ Vdd, Outputs Disabled Min. Max. Unit 2.4 — V — 0.4 V 2 Vdd + 0.3 V –0.3 0.8 V –1 1 µA –1 1 µA Note: 1. Vil (min.) = –0.3V DC; Vil (min.) = –2.0V AC (pulse width < 2 ns). Not 100% tested. Vih (max.) = Vdd + 0.3V DC; Vih (max.) = Vdd + 2.0V AC (pulse width < 2 ns). Not 100% tested. DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Vdd = 2.4V-3.6V Symbol Voh Vol Vih Vil Ili Ilo Parameter Test Conditions Output HIGH Voltage Vdd = Min., Ioh = –1.0 mA Output LOW Voltage Vdd = Min., Iol = 1.0 mA Input HIGH Voltage Input LOW Voltage(1) Input Leakage GND ≤ Vin ≤ Vdd Output Leakage GND ≤ Vout ≤ Vdd, Outputs Disabled Min. Max. Unit 1.8 — V — 0.4 V 2.0 Vdd + 0.3 V –0.3 0.8 V –1 1 µA –1 1 µA Note: 1. Vil (min.) = –0.3V DC; Vil (min.) = –2.0V AC (pulse width < 2 ns). Not 100% tested. Vih (max.) = Vdd + 0.3V DC; Vih (max.) = Vdd + 2.0V AC (pulse width < 2 ns). Not 100% tested. POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) -8 -10 -20 Symbol Parameter Test Conditions Min. Max. Min. Max. Min. Max. Unit Icc Vdd Dynamic Operating Vdd = Max., Com. — 25 — 20 — 15 mA Supply Current Iout = 0 mA, f = fmax Ind. — 30 — 25 — 20 Auto. — — — 35 — 30 typ.(2) 15 15 Icc1 Operating Vdd = Max., Com. — 10 — 10 — 10 mA Supply Current Iout = 0 mA, f = 0 Ind. — 12 — 12 — 12 Auto. — — — 15 — 15 Isb1 TTL Standby Current Vdd = Max., Com. — 10 — 10 — 10 mA (TTL Inputs) Vin = Vih or Vil Ind. — 12 — 12 — 12 CE ≥ Vih, f = 0 Auto. — — — 20 — 20 Isb2 CMOS Standby Vdd = Max., Com. — 3 — 3 — 3 mA Current (CMOS Inputs) CE ≥ Vdd – 0.2V, Ind. — 4 — 4 — 4 Vin ≥ Vdd – 0.2V or Auto. — — — 10 — 10 Vin ≤ 0.2V, f = 0 typ.(2) 1 1 Note: 1. At f = fmax, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. Typical values are measured at Vdd = 3.0V, Ta = 25oC and not 100% tested. 4 Integrated Silicon Solution, Inc. — www.issi.com Rev. B1 05/27/2020 IS61/64WV1288EEBLL AC TEST CONDITIONS 1 Parameter Unit (2.4V-3.6V) Input Pulse Level 0.4V to Vdd-0.3V Input Rise and Fall Times 1V/ ns Input and Output Timing Vdd/2 and Reference Level (VRef) Output Load See Figures 1 and 2 2 3 AC TEST LOADS 4 319 Ω ZO = 50Ω 3.3V 50Ω 1.5V OUTPUT 30 pF Including jig and scope Figure 1. OUTPUT 353 Ω 5 pF Including jig and scope Figure 2. 5 6 7 READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) -8 -10 -20 Symbol Parameter Min. Max. Min. Max. Min. Max. trc Read Cycle Time 8 — 10 — 20 — taa Address Access Time — 8 — 10 — 20 toha Output Hold Time 2.0 — 2.0 — 2.5 — tace CE Access Time — 8 — 10 — 20 OE Access Time — 4.5 — 4.5 — 8 tdoe thzoe(2) OE to High-Z Output — 3 — 4 — 8 (2) tlzoe OE to Low-Z Output 0 — 0 — 0 — thzce(2 CE to High-Z Output 0 3 0 4 0 8 tlzce(2) CE to Low-Z Output 3 — 3 — 3 — tpu Power Up Time 0 — 0 — 0 — tpd Power Down Time — 8 — 10 — 20 Unit ns ns ns ns ns ns ns ns ns ns ns Notes: 1.  Test conditions and output loading conditions are specified in the AC Test Conditions and AC Test Loads (Figure 1). 2.  Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Integrated Silicon Solution, Inc. — www.issi.com 5 Rev. B1 05/27/2020 8 9 10 11 12 IS61/64WV1288EEBLL AC WAVEFORMS READ CYCLE NO. 1(1,2) (Address Controlled) (CE = OE = Vil) t RC ADDRESS t AA t OHA DOUT t OHA DATA VALID PREVIOUS DATA VALID READ1.eps READ CYCLE NO. 2(1,3) (CE and OE Controlled) t RC ADDRESS t AA t OHA OE t HZOE t DOE t LZOE CE t LZCE DOUT t ACE HIGH-Z t HZCE DATA VALID CE_RD2.eps Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE = Vil. 3. Address is valid prior to or coincident with CE LOW transitions. 6 Integrated Silicon Solution, Inc. — www.issi.com Rev. B1 05/27/2020 IS61/64WV1288EEBLL WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range) -8 -10 -20 Symbol Parameter Min. Max. Min. Max. Min. Max. Unit twc Write Cycle Time 8 — 10 — 20 — ns tsce CE to Write End 6.5 — 8 — 12 — ns taw Address Setup Time 6.5 — 8 — 12 — ns to Write End tha Address Hold from Write End 0 — 0 — 0 — ns tsa Address Setup Time 0 — 0 — 0 — ns tpwe1 WE Pulse Width 6.5 — 8 — 12 — ns tpwe2 WE Pulse Width (OE = LOW) 8.0 — 10 — 17 — ns tsd Data Setup to Write End 5 — 6 — 9 — ns thd Data Hold from Write End 0 — 0 — 0 — ­ns thzwe(2) WE LOW to High-Z Output — 3.5 — 5 — 9 ns (2) tlzwe WE HIGH to Low-Z Output 2 — 2 — 2 — ns Notes: 1.  Test conditions and output loading conditions are specified in the AC Test Conditions and AC Test Loads (Figure 1). 2.  Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3.  The internal write time is defined by the overlap of CE LOW, and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. Shaded area product in development 1 2 3 4 5 6 7 8 9 10 11 12 Integrated Silicon Solution, Inc. — www.issi.com 7 Rev. B1 05/27/2020 IS61/64WV1288EEBLL AC WAVEFORMS WRITE CYCLE NO. 1(1,2) (CE Controlled, OE = HIGH or LOW) t WC VALID ADDRESS ADDRESS t SA t SCE t HA CE t AW t PWE1 t PWE2 WE t HZWE DOUT DATA UNDEFINED t LZWE HIGH-Z t SD DIN t HD DATAIN VALID CE_WR1.eps 8 Integrated Silicon Solution, Inc. — www.issi.com Rev. B1 05/27/2020 IS61/64WV1288EEBLL WRITE CYCLE NO. 2(1,2) (WE Controlled: OE is HIGH During Write Cycle) t WC ADDRESS 1 VALID ADDRESS t HA 2 OE CE 3 LOW t AW t PWE1 WE t SA DOUT t HZWE 4 t LZWE HIGH-Z DATA UNDEFINED t SD 5 t HD DATAIN VALID DIN CE_WR2.eps Notes: 1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. 2. I/O will assume the High-Z state if OE > Vih. 6 7 WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle) 8 t WC ADDRESS VALID ADDRESS OE LOW CE LOW 9 t HA t AW 10 t PWE2 11 WE t SA DOUT DATA UNDEFINED t HZWE t LZWE HIGH-Z t SD DIN 12 t HD DATAIN VALID CE_WR3.eps Integrated Silicon Solution, Inc. — www.issi.com 9 Rev. B1 05/27/2020 IS61/64WV1288EEBLL HIGH SPEED DATA RETENTION SWITCHING CHARACTERISTICS  (2.4V-3.6V) Symbol Parameter Test Condition Options Min. Typ.(1) Max. Unit Vdr Vdd for Data Retention See Data Retention Waveform 2.0 — 3.6 V Idr Data Retention Current Vdd = Vdr(min), CE ≥ Vdd – 0.2V, Com. — 0.5 3 mA Vin > Vdd - 0.2V or Ind. — — 4 Vin < 0.2V Auto. 10 tsdr Data Retention Setup Time See Data Retention Waveform 0 — — ns trdr Recovery Time See Data Retention Waveform trc — — ns Note 1: Typical values are measured at Vdd = Vdr(min), Ta = 25 C and not 100% tested. o DATA RETENTION WAVEFORM (CE Controlled) tSDR Data Retention Mode tRDR VDD VDR CE GND 10 CE ≥ VDD - 0.2V Integrated Silicon Solution, Inc. — www.issi.com Rev. B1 05/27/2020 IS61/64WV1288EEBLL ORDERING INFORMATION (HIGH SPEED) Industrial Range: -40°C to +85°C Speed (ns) 8 10 Order Part No. IS61WV1288EEBLL-8BLI IS61WV1288EEBLL-8TLI IS61WV1288EEBLL-10BLI IS61WV1288EEBLL-10HLI IS61WV1288EEBLL-10TLI Package 48 mini BGA (6mm x 8mm), Lead-free TSOP (Type II), Lead-free 48 mini BGA (6mm x 8mm), Lead-free sTSOP (Type I) (8mm x 13.4mm), Lead-free TSOP (Type II), Lead-free Automotive A1 Range: -40°C to +85°C Speed (ns) 8 10 Order Part No. IS64WV1288EEBLL-8BLA1 IS64WV1288EEBLL-8CTLA1 IS64WV1288EEBLL-10BLA1 IS64WV1288EEBLL-10CTLA1 Package 48 mini BGA (6mm x 8mm), Lead-free TSOP (Type II), Lead-free, Copper Leadframe 48 mini BGA (6mm x 8mm), Lead-free TSOP (Type II), Lead-free, Copper Leadframe Automotive A3 Range: -40°C to +125°C Speed (ns) 10 Order Part No. IS64WV1288EEBLL-10BLA3 IS64WV1288EEBLL-10CTLA3 Package 48 mini BGA (6mm x 8mm), Lead-free TSOP (Type II), Lead-free, Copper Leadframe 1 2 3 4 5 6 7 8 9 10 11 12 Integrated Silicon Solution, Inc. — www.issi.com 11 Rev. B1 05/27/2020 IS61/64WV1288EEBLL 12 Integrated Silicon Solution, Inc. — www.issi.com Rev. B1 05/27/2020 IS61/64WV1288EEBLL 1 2 3 4 5 6 7 8 9 10 11 12 Integrated Silicon Solution, Inc. — www.issi.com 13 Rev. B1 05/27/2020 IS61/64WV1288EEBLL 14 Integrated Silicon Solution, Inc. — www.issi.com Rev. B1 05/27/2020 08/12/2008 1 2 3 Package Outline 1. CONTROLLING DIMENSION : MM . 2. Reference document : JEDEC MO-207 NOTE : IS61/64WV1288EEBLL 4 5 6 7 8 9 10 11 12 Integrated Silicon Solution, Inc. — www.issi.com 15 Rev. B1 05/27/2020