IS61WV204816ALL-10BLI

IS61/64WV204816ALL IS61/64WV204816BLL 2Mx16 HIGH-SPEED ASYNCHRONOUS CMOS STATIC RAM WITH 3.3V/1.8V SUPPLY FEATURES  High-speed access time: 10ns, 12ns  High- performance, low power CMOS process  Multiple center power and ground pins for greater noise immunity  Easy memory expansion with CS# and OE#  TTL compatible inputs and outputs  Single power supply – 1.65V-2.2V VDD (IS61/64WV204816ALL) – 2.4V-3.6V VDD (IS61/64WV204816BLL)  Packages available : - 48 ball mini BGA (6mm x 8mm) - 48 pin TSOP (Type I) Industrial and Automotive temperature support   Lead-free available  Data Control for upper and lower bytes AUGUST 2019 DESCRIPTION The ISSI IS61/64WV204816ALL/BLL are high-speed, 32M bit static RAMs organized as 2048K words by 16 bits. It is fabricated using ISSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields high-performance and low power consumption devices. When CS# is HIGH (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs. The active LOW Write Enable (WE#) controls both writing and reading of the memory. A data byte allows Upper Byte (UB#) and Lower Byte (LB#) access. The device is packaged in the JEDEC standard 48-Pin TSOP (TYPE I) and 48-pin mini BGA (6mm x 8mm). FUNCTIONAL BLOCK DIAGRAM A0 – A20 DECODER 2048 K x 16 MEMORY ARRAY I/ O DATA CIRCUIT COLUMN IO VDD VSS I/O 0 – I/O7 Lower Byte I/O 8 – I/O15 Upper Byte CS# OE# WE# UB# LB# CONTROL CIRCUIT Copyright © 2019 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc.- www.issi.com Rev. A2 08/07/2019 1 IS61/64WV204816ALL IS61/64WV204816BLL PIN CONFIGURATIONS 48-Pin mini BGA (6mm x 8mm) 1 A B LB# I/O8 2 OE# UB# 3 A0 A3 4 A1 A4 5 A2 CE# 48-Pin TSOP ,TYPE I ( 12mm x 20mm ) 6 NC I/O0 A4 1 48 A5 A3 A2 2 3 47 A6 46 A1 4 45 A7 A8 A0 NC 5 6 44 43 CS# I/O0 7 42 UB# LB# 8 41 I/O15 9 40 I/O14 39 I/O3 10 11 I/O13 I/O12 VDD 12 VSS I/O4 13 14 36 VDD 35 I/O11 I/O5 I/O6 15 34 I/O10 16 33 I/O9 I/O7 17 32 I/O8 18 31 A20 A9 I/O1 I/O2 C D I/O9 VSS E F VDD I/O14 I/O10 I/O11 I/O12 I/O13 A5 A17 NC A14 A6 A7 A16 A15 I/O1 I/O3 I/O4 I/O5 I/O2 VDD VSS I/O6 G I/O15 A19 A12 A13 WE# I/O7 H A18 A8 A9 A10 A11 A20 WE# 38 37 OE# VSS NC 19 30 A19 20 29 A10 A18 A17 21 28 A11 22 A12 A16 23 27 26 A15 24 25 A14 A13 PIN DESCRIPTIONS A0-A20 I/O0-I/O15 CS# Address Inputs Data Inputs/Outputs Chip Enable Input OE# WE# LB# Output Enable Input Write Enable Input Lower-byte Control (I/O0-I/O7) Upper-byte Control (I/O8-I/O15) No Connection Power Ground UB# NC VDD VSS Integrated Silicon Solution, Inc.- www.issi.com Rev. A2 08/07/2019 2 IS61/64WV204816ALL IS61/64WV204816BLL FUNCTION DESCRIPTION SRAM is one of random access memories. Each byte or word has an address and can be accessed randomly. SRAM has three different modes supported. Each function is described below with Truth Table. STANDBY MODE Device enters standby mode when deselected (CS# HIGH). The input and output pins (I/O0-15) are placed in a high impedance state. CMOS input in this mode will maximize saving power. WRITE MODE Write operation issues with Chip selected (CS#) and Write Enable (WE#) input LOW. The input and output pins (I/O015) are in data input mode. Output buffers are closed during this time even if OE# is LOW. UB# and LB# enables a byte write feature. By enabling LB# LOW, data from I/O pins (I/O0 through I/O7) are written into the location specified on the address pins. And with UB# being LOW, data from I/O pins (I/O8 through I/O15) are written into the location. READ MODE Read operation issues with Chip selected (CS# LOW) and Write Enable (WE#) input HIGH. When OE# is LOW, output buffer turns on to make data output. Any input to I/O pins during READ mode is not permitted. UB# and LB# enables a byte read feature. By enabling LB# LOW, data from memory appears on I/O0-7. And with UB# being LOW, data from memory appears on I/O8-15. In the READ mode, output buffers can be turned off by pulling OE# HIGH. In this mode, internal device operates as READ but I/Os are in a high impedance state. Since device is in READ mode, active current is used. POWER UP INITIALIZATION The device includes on-chip voltage sensor used to launch POWER-UP initialization process. When VDD reaches stable level, the device requires 150us of tPU (Power-Up Time) to complete its self-initialization process. When initialization is complete, the device is ready for normal operation. tPU 150 us Stable VDD Device Initialization VDD Device for Normal Operation 0V TRUTH TABLE Mode Not Selected Output Disabled Read Write CS# WE# OE# LB# UB# I/O0-I/O7 I/O8-I/O15 VDD Current H L L L L L L L L X H H H H H L L L X H H L L L X X X X L H L H L L H L X L L H L L H L L High-Z High-Z High-Z DOUT High-Z DOUT DIN High-Z DIN High-Z High-Z High-Z High-Z DOUT DOUT High-Z DIN DIN ISB1, ISB2 Integrated Silicon Solution, Inc.- www.issi.com Rev. A2 08/07/2019 ICC ICC ICC 3 IS61/64WV204816ALL IS61/64WV204816BLL ABSOLUTE MAXIMUM RATINGS AND Operating Range ABSOLUTE MAXIMUM RATINGS(1) Symbol Vt er m Parameter Terminal Voltage with Respect to VSS Value –0.5 to VDD + 0.5V Unit V VDD V DD Related to VSS –0.3 to 4.0 V tStg Storage Temperature –65 to +150 PT Power Dissipation 1.0 C W Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. PIN CAPACITANCE (1) Parameter Symbol Input capacitance DQ capacitance (IO0–IO15) CIN CI/O Test Condition TA = 25°C, f = 1 MHz, VDD = VDD(typ) Max Units 6 8 pF pF Note: 1. These parameters are guaranteed by design and tested by a sample basis only. OPERATING RANGE Range Ambient Temperature Commercial 0C to +70C Industrial -40C to +85C Automotive (A3) -40C to +125C PART NUMBER IS61WV204816ALL IS61WV204816BLL IS61WV204816ALL IS61WV204816BLL IS64WV204816ALL IS64WV204816BLL VDD SPEED (MAX) 1.65V – 2.2V 2.4V – 3.6V 1.65V – 2.2V 2.4V – 3.6V 1.65V – 2.2V 2.4V – 3.6V 12 ns(1) 10ns 12 ns(1) 10ns 12 ns Note: 1. Contact ISSI MKT for 1.8V 10ns device. Integrated Silicon Solution, Inc.- www.issi.com Rev. A2 08/07/2019 4 IS61/64WV204816ALL IS61/64WV204816BLL AC TEST CONDITIONS (OVER THE OPERATING RANGE) Parameter Input Pulse Level Unit (1.65V~2.2V) 0V to VDD Unit (2.4V~3.6V) 0V to VDD 1.5 ns ½ VDD 13500 10800 1.8V 1.5 ns ½ VDD 319 353 3.3V Input Rise and Fall Time Output Timing Reference Level R1 (ohm) R2 (ohm) VTM (V) Output Load Conditions Refer to Figure 1 and 2 AC TEST LOADS FIGURE 1 FIGURE 2 R1 VTM TM V Zo = 50 ohm Output 50 ohm VDD/2 30 pF, Including jig and scope Integrated Silicon Solution, Inc.- www.issi.com Rev. A2 08/07/2019 OUTPUT 5pF, Including jig and scope R2R2 5 IS61/64WV204816ALL IS61/64WV204816BLL DC ELECTRICAL CHARACTERISTICS DC ELECTRICAL CHARACTERISTICS-I (OVER THE OPERATING RANGE) VDD = 1.65V – 2.2V Symbol VOH VOL VIH(1) VIL(1) ILI ILO Note: 1. Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Output Leakage Test Conditions I OH = -0.1 mA IOL = 0.1 mA GND < VIN < VDD GND < VIN < VDD, Output Disabled Min. 1.4 — 1.4 –0.2 –1 –1 Max. — 0.2 VDD + 0.2 0.4 1 1 Unit V V V V µA µA VILL(min) = -1.0V AC (pulse width < 10ns). Not 100% tested. VIHH (MAX) = VDD + 1.0V AC (PULSE WIDTH < 10NS). NOT 100% TESTED. VDD = 2.4V – 3.6V Symbol VOH VOL VIH(1) VIL(1) ILI ILO Parameter Output HIGH 2.4V Voltage 2.7V Output LOW 2.4V Voltage 2.7V Input HIGH Voltage 2.4V 2.7V Input LOW Voltage 2.4V 2.7V Input Leakage Output Leakage ~ ~ ~ ~ ~ ~ ~ ~ 2.7V 3.6V 2.7V 3.6V 2.7V 3.6V 2.7V 3.6V V DD V DD V DD V DD = = = = Test Conditions Min., I OH = -1.0 mA Min., I OH = -4.0 mA Min., IOL = 2.0 mA Min., I OL = 8.0 mA VSS < VIN < VDD VSS < VIN < VDD, Output Disabled Min. 2.0 2.2 — — 2.0 2.0 –0.3 –0.3 –2 –2 Max. — 0.4 0.4 VDD + 0.3 0.6 0.8 2 2 Unit V V V V µA µA Note: 1. VIL(min) = -0.3V DC ; VIL(min) = -2.0V AC (pulse width 2.0ns). Not 100% tested. VIH (max) = VDD + 0.3V DC ; VIH(max) = VDD + 2.0V AC (pulse width 2.0ns). Not 100% tested. Integrated Silicon Solution, Inc.- www.issi.com Rev. A2 08/07/2019 6 IS61/64WV204816ALL IS61/64WV204816BLL POWER SUPPLY CHARACTERISTICS-II FOR POWER (1, 2) (OVER THE OPERATING RANGE) IS61/64WV204816ALL (VDD = 1.65V – 2.2V) & IS61/64WV204816BLL (VDD = 2.4V – 3.6V) Symbol Parameter Test Conditions ICC VDD Dynamic Operating Supply Current VDD = MAX, IOU T = 0 mA, f = fMAX ICC1 Operating Supply Current ISB1 TTL Standby Current (TTL Inputs) ISB2 CMOS Standby Current (CMOS Inputs) Notes: 1. 2. VDD = MAX, IOUT = 0 mA, f = 0 VDD = MAX, VIN = VIH or VIL CS# ≥ VIH , f = 0 VDD = MAX, CS# ≥ VDD - 0.2V VIN ≥ VDD - 0.2V , or VIN ≤ 0.2V ,f=0 -10 Max. 90 100 140 80 90 110 60 70 110 50 -12 Max. 85 95 135 80 90 110 60 70 110 50 Ind. 60 60 Auto. 100 100 Grade Com. Ind. Auto. Com. Ind. Auto. Com. Ind. Auto. Com. Typ. (2) Unit mA mA mA mA 10 At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input line change. Typical values are measured at VDD = 3.0V/1.8V, TA = 25 °C and not 100% tested. Integrated Silicon Solution, Inc.- www.issi.com Rev. A2 08/07/2019 7 IS61/64WV204816ALL IS61/64WV204816BLL AC CHARACTERISTICS (OVER OPERATING RANGE) READ CYCLE AC CHARACTERISTICS Parameter Symbol Read Cycle Time Address Access Time Output Hold Time tRC tAA tOHA CS# Access Time OE# Access Time OE# to High-Z Output OE# to Low-Z Output CS# to High-Z Output CS# to Low-Z Output UB#, LB# Access Time UB#, LB# to High-Z Output UB#, LB# to Low-Z Output -10(1) -12(1) unit notes Min Max Min Max 10 2.5 10 - 12 2.5 12 - ns ns ns tACE tDOE tHZOE tLZOE tHZCE tLZCE 0 0 0 3 10 6 5 5 - 0 0 0 3 12 7 6 6 - ns ns ns ns ns ns 2 2 2 2 tBA tHZB tLZB 0 0 6 5 - 0 0 7 6 - ns ns ns 2 2 Notes: 1. Test conditions assume signal transition times of 1.5 ns or less, timing reference levels of VDD/2, input pulse levels of 0V to VDD and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. Integrated Silicon Solution, Inc.- www.issi.com Rev. A2 08/07/2019 8 IS61/64WV204816ALL IS61/64WV204816BLL AC WAVEFORMS READ CYCLE NO. 1(1) (Address Controlled, CS# = OE# = UB# = LB# = LOW, WE# = HIGH) tRC Address tAA tOHA tOHA DQ 0-15 Note: 1. PREVIOUS DATA VALID DATA VALID The device is continuously selected. READ CYCLE NO. 2(1) (OE# CONTROLLED, WE# = HIGH) tRC ADDRESS tAA tOHA tDOE OE# tHZOE tLZOE CS# tACS tHZCS tLZCS UB#,LB# tHZB tBA tLZB DOUT Note: 1. HIGH-Z LOW-Z DATA VALID Address is valid prior to or coincident with CS# LOW transition. Integrated Silicon Solution, Inc.- www.issi.com Rev. A2 08/07/2019 9 IS61/64WV204816ALL IS61/64WV204816BLL WRITE CYCLE AC CHARACTERISTICS Symbol Write Cycle Time tWC tSCS tAW 10 8 8 tPWB tHA tSA tPWE1 tPWE2 tSD tHD tHZWE tLZWE CS# to Write End Address Setup Time to Write End UB#,LB# to Write End Address Hold from Write End Address Setup Time WE# Pulse Width WE# Pulse Width (OE# = LOW) Data Setup to Write End Data Hold from Write End WE# LOW to High-Z Output WE# HIGH to Low-Z Output Notes: 1 2 -12(1) -10(1) Min Max Parameter unit Min Max - 12 9 9 - ns ns ns 8 0 0 8 10 6 - 9 0 0 9 12 7 - ns ns ns ns ns ns 0 2 4 - 0 2 5 - ns ns ns notes 2 The internal write time is defined by the overlap of CS# = LOW, UB# or LB# = LOW, and WE# = LOW. All conditions must be in valid states to initiate a Write, but any condition can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. Tested tPWE > tHZWE + tSD when OE# is LOW. AC WAVEFORMS WRITE CYCLE NO. 1 (CS# CONTROLLED, OE# = HIGH OR LOW) tWC ADDRESS tSCS tSA tHA CS# tAW tPWE WE# tPWB UB#,LB# tHZWE DOUT DATA UNDEFINED (1) HIGH-Z tSD DIN DATA UNDEFINED (2) tLZWE tHD DATA IN VALID Note: 1. tHZWE is is based on the assumption when tSA=0nS after READ operation. Actual DOUT for tHZWE may not appear if OE# goes high before Write Cycle. Integrated Silicon Solution, Inc.- www.issi.com Rev. A2 08/07/2019 10 IS61/64WV204816ALL IS61/64WV204816BLL WRITE CYCLE NO. 2(1,2) (WE# CONTROLLED: OE# IS HIGH DURING WRITE CYCLE) tWC ADDRESS tSCS tHA CS# tAW WE# tPWE tSA tPWB UB#,LB# OE# tHZOE DATA UNDEFINED DOUT HIGH-Z (1) tHD tSD DATA UNDEFINED DIN (2) DATA IN VALID Notes: 1. tHZOE is the time DOUT goes to High-Z after OE# goes high. 2. During this period the I/Os are in output state. Do not apply input signals. WRITE CYCLE NO. 3(1) (WE# CONTROLLED: OE# IS LOW DURING WRITE CYCLE) tWC ADDRESS OE# = LOW CS#=LOW tHA tAW tPWE2 WE# tSA UB#,LB# tPWB tHZWE DOUT tLZWE HIGHZ DATA UNDEFINED tSD DIN Note: 1. tHD DATA IN VALID If OE# is low during write cycle, tHZWE must be met in the application. Do not apply input signal during this period. Data output from the previous READ operation will drive IO BUS. Integrated Silicon Solution, Inc.- www.issi.com Rev. A2 08/07/2019 11 IS61/64WV204816ALL IS61/64WV204816BLL WRITE CYCLE NO. 4(1, 2, 3) (UB# & LB# Controlled, CS# = OE# = LOW) tWC tWC ADDRESS ADDRESS 1 ADDRESS 2 CS#=LOW OE#=LOW tSA tHA tSA tHA WE# tPWB UB#, LB# tPWB WORD 1 WORD 2 tHZWE DOUT tLZWE HIGH-Z DATA UNDEFINED tHD tSD DIN Notes: 1. 2. 3. DATA IN VALID DATA IN VALID If OE# is low during write cycle, tHZWE must be met in the application. Do not apply input signal during this period. Data output from the previous READ operation will drive IO BUS. Due to the restriction of note1, OE# is recommended to be HIGH during write period. WE# stays LOW in this example. If WE# toggles,, tPWE and tHZWE must be considered. Integrated Silicon Solution, Inc.- www.issi.com Rev. A2 08/07/2019 12 IS61/64WV204816ALL IS61/64WV204816BLL DATA RETENTION CHARACTERISTICS Symbol Parameter VDR VDD for Data Retention Data Retention Current IDR Test Condition OPTION Min. VDD = 2.4V to 3.6V 2.0 Typ.(2) Max. Unit 3.6 See Data Retention Waveform V VDD = 1.65V to 2.2V 1.2 Com. - 10 50 Ind. - - 60 Auto - - 100 VDD= VDR(min), CS# ≥ VDD – 0.2V 3.6 mA tSDR Data Retention Setup Time See Data Retention Waveform 0 - - ns tRDR Recovery Time See Data Retention Waveform tRC - - ns Notes: 1. 2. If CS# > VDD–0.2V, all other inputs including UB# and LB# must meet this condition. Typical values are measured at VDD = VDR (Min), TA = 25 °C and not 100% tested. DATA RETENTION WAVEFORM (CS# CONTROLLED) tSDR Data Retention Mode tRDR VDD VDR CS# CS# > VDD – 0.2V GND Integrated Silicon Solution, Inc.- www.issi.com Rev. A2 08/07/2019 13 IS61/64WV204816ALL IS61/64WV204816BLL ORDERING INFORMATION IS61/64WV204816ALL (1.65V – 2.2V) Commercial Range: 0°C to +70°C Speed (ns) Order Part No. Package 10 Contact ISSI MKT for 10ns 12 IS61WV204816ALL-12B mini BGA (6mm x 8mm) 12 IS61WV204816ALL-12BL mini BGA (6mm x 8mm), Lead-free 12 IS61WV204816ALL-12TL TSOP (Type I), Lead-free Industrial Range: -40°C to +85°C Speed (ns) Order Part No. Package 10 Contact ISSI MKT for 10ns 12 IS61WV204816ALL-12BI mini BGA (6mm x 8mm) 12 IS61WV204816ALL-12BLI mini BGA (6mm x 8mm), Lead-free 12 IS61WV204816ALL-12TLI TSOP (Type I), Lead-free Automotive (A3) Range: –40°C to +125°C Speed (ns) Order Part No. Package 12 IS64WV204816ALL-12BA3 mini BGA (6mm x 8mm) 12 IS64WV204816ALL-12BLA3 mini BGA (6mm x 8mm), Lead-free 12 IS64WV204816ALL-12CTLA3 TSOP (Type I), Copper Lead-frame, Lead-free Integrated Silicon Solution, Inc.- www.issi.com Rev. A2 08/07/2019 14 IS61/64WV204816ALL IS61/64WV204816BLL IS61/64WV204816BLL (2.2V - 3.6V) Commercial Range: 0°C to +70°C Speed (ns) Order Part No. Package 10 IS61WV204816BLL-10B mini BGA (6mm x 8mm) 10 IS61WV204816BLL-10BL mini BGA (6mm x 8mm), Lead-free 10 IS61WV204816BLL-10TL TSOP (Type I), Lead-free Industrial Range: -40°C to +85°C Speed (ns) Order Part No. Package 10 IS61WV204816BLL-10BI mini BGA (6mm x 8mm) 10 IS61WV204816BLL-10BLI mini BGA (6mm x 8mm), Lead-free 10 IS61WV204816BLL-10TLI TSOP (Type I), Lead-free Automotive (A3) Range: –40°C to +125°C Speed (ns) Order Part No. Package 12 IS64WV204816BLL-12BA3 mini BGA (6mm x 8mm) 12 IS64WV204816BLL-12BLA3 mini BGA (6mm x 8mm), Lead-free 12 IS64WV204816BLL-12CTLA3 TSOP (Type I), Copper Lead-frame, Lead-free Integrated Silicon Solution, Inc.- www.issi.com Rev. A2 08/07/2019 15 IS61/64WV204816ALL IS61/64WV204816BLL PACKAGE INFORMATION Integrated Silicon Solution, Inc.- www.issi.com Rev. A2 08/07/2019 16 IS61/64WV204816ALL IS61/64WV204816BLL Integrated Silicon Solution, Inc.- www.issi.com Rev. A2 08/07/2019 17