IS61WV25616EDALL-20BLI-TR

IS61WV25616EDALL 256Kx16 HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM with ECC KEY FEATURES  High-speed access time: 20ns  Single power supply – 1.65V-2.2V VDD  Low Standby Current:1.5mA (typical)  Fully static operation: no clock or refresh required  Data control  Three state outputs  Industrial and Automotive temperature support  Lead-free available  Error Detection and Correction FUNCTIONAL BLOCK DIAGRAM Memory Memory Lower IO ECC Upper IO ECC Array Array Array Array 256Kx8 256Kx4 256Kx8 256Kx4 DECODER A0 – A17 VDD VSS 8 I/O0 – I/O7 I/O8 – I/O15 I/O DATA CIRCUIT 8 4 DESCRIPTION The ISSI IS61WV25616EDALL are high-speed, low power, 4M bit static RAMs organized as 256K words by 16 bits. It is fabricated using ISSI's high-performance CMOS technology and implemented ECC function to improve reliability. When CS# is HIGH (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs. The active LOW Write Enable (WE#) controls both writing and reading of the memory. A data byte allows Upper Byte (UB#) and Lower Byte (LB#) access. The IS61WV25616EDALL are packaged in the JEDEC standard 48-pin mini BGA (6mm x 8mm), and 44-pin TSOP (TYPE II) 12 8 8 4 AUGUST 2020 ECC ECC 12 COLUMN I/OColumn I/O CS# OE# WE# UB# LB# CONTROL CIRCUIT Copyright © 2020 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc.- www.issi.com Rev. A2 08/28/2020 1 IS61WV25616EDALL PIN CONFIGURATIONS 48-Pin mini BGA(6mm x 8mm) 1 A B LB# I/O8 C D E F I/O9 VSS VDD I/O14 2 OE# UB# I/O10 I/O11 I/O12 I/O13 3 A0 A3 A5 A17 NC A14 4 A1 A4 A6 A7 A16 A15 44-Pin TSOP-II 5 6 A2 CS# NC I/O0 I/O1 I/O3 I/O2 VDD I/O4 I/O5 VSS I/O6 G I/O15 NC A12 A13 WE# I/O7 H NC A8 A9 A10 A11 NC A0 1 44 A17 A1 2 43 A16 A2 3 42 A15 A3 4 41 OE# A4 5 40 UB# CS# 6 39 LB# I/O0 7 38 I/O15 I/O1 I/O2 8 9 37 36 I/O14 I/O13 I/O12 I/O3 10 35 VDD 11 34 VSS VSS 12 33 VDD I/O4 13 32 I/O11 I/O5 I/O6 14 31 I/O10 15 30 I/O9 I/O7 16 29 I/O8 WE# 17 28 NC A5 18 27 A14 A6 A7 19 26 A13 20 25 A12 A8 21 24 A11 A9 22 23 A10 PIN DESCRIPTIONS A0-A17 I/O0-I/O15 CS# OE# WE# LB# UB# NC VDD VSS Address Inputs Data Inputs/Outputs Chip Enable Input Output Enable Input Write Enable Input Lower-byte Control (I/O0-I/O7) Upper-byte Control (I/O8-I/O15) No Connection Power Ground Integrated Silicon Solution, Inc.- www.issi.com Rev. A2 08/28/2020 2 IS61WV25616EDALL FUNCTION DESCRIPTION SRAM is one of random access memories. Each byte or word has an address and can be accessed randomly. SRAM has various modes supported. Each function is described below with Truth Table. STANDBY MODE Device enters standby mode when deselected (CS# HIGH). The input and output pins (I/O0-15) are placed in a high impedance state. The current consumption in this mode will be ISB1, or ISB2. WRITE MODE Write operation issues with Chip Select (CS#) Low and Write Enable (WE#) Low. The input and output pins (I/O0-15) are in data input mode. Output buffers are closed during this time even if OE# is Low. UB# and LB# enables a byte write feature. By enabling LB# Low, data from I/O pins (I/O0 through I/O7) are written into the location specified on the address pins. And with UB# being Low, data from I/O pins (I/O8 through I/O15) are written into the location. READ MODE Read operation issues with Chip Select (CS#) Low and Write Enable (WE#) High. When OE# is Low, output buffer turns on to make data output. Any input to I/O pins during READ mode is not permitted. UB# and LB# enables a byte read feature. By enabling LB# Low, data from memory appears on I/O0-7. And with UB# being Low, data from memory appears on I/O8-15. In the READ mode, output buffers can be turned off by pulling OE# High. In this mode, internal device operates as READ but I/Os are in a high impedance state. Since device is in READ mode, active current is used. TRUTH TABLE Mode CS# WE# OE# LB# UB# I/O0-I/O7 I/O8-I/O15 VDD Current Not Selected H X X X X High-Z High-Z ISB1, ISB2 L H H L X High-Z High-Z L X X H H High-Z High-Z L H L L H DOUT High-Z L H L H L High-Z DOUT L H L L L DOUT DOUT L L X L H DIN High-Z L L X H L High-Z DIN L L X L L DIN DIN Output Disabled Read Write ICC,ICC1 Integrated Silicon Solution, Inc.- www.issi.com Rev. A2 08/28/2020 ICC,ICC1 ICC,ICC1 3 IS61WV25616EDALL ABSOLUTE MAXIMUM RATINGS(1) Symbol Vter m VDD tStg Parameter Terminal Voltage with Respect to VSS V DD Related to VSS Storage Temperature Value –0.5 to VDD + 0.5V –0.3 to 4.0 –65 to +150 PT Power Dissipation 1.0 Unit V V C W Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. . PIN CAPACITANCE (1) Parameter Input capacitance DQ capacitance (IO0–IO15) Symbol CIN CI/O Test Condition TA = 25°C, f = 1 MHz, VDD = VDD(typ) Max 6 8 Units pF pF Note: 1. These parameters are guaranteed by design and tested by a sample basis only. OPERATING RANGE(1) Range Ambient Temperature Commercial 0C to +70C Industrial -40C to +85C Note: 1. PART NUMBER IS61WV25616EDALL SPEED (MAX) VDD 20 ns 20 ns 1.65V – 2.2V 1.65V – 2.2V Full device AC operation assumes a 100 µs ramp time from 0 to VDD(min) and 200 µs wait time after VDD stabilization. THERMAL CHARACTERISTICS (1) Parameter Thermal resistance from junction to ambient (airflow = 1m/s) Thermal resistance from junction to pins Thermal resistance from junction to case Symbol RθJA RθJB RθJC Rating TBD TBD TBD Units °C/W °C/W °C/W Note: 1. These parameters are guaranteed by design and tested by a sample basis only. Integrated Silicon Solution, Inc.- www.issi.com Rev. A2 08/28/2020 4 IS61WV25616EDALL AC TEST CONDITIONS (OVER THE OPERATING RANGE) Parameter Unit (1.65V~2.2V) 0V to VDD 1.5 ns 0.9V 13500 10800 1.8V Refer to Figure 1 and 2 Input Pulse Level Input Rise and Fall Time Output Timing Reference Level R1 (ohm) R2 (ohm) VTM (V) Output Load Conditions OUTPUT LOAD CONDITIONS FIGURES FIGURE 1 FIGURE 2 R1 VTM TM V Zo = 50 ohm Output 50 ohm VDD/2 30 pF, Including jig and scope Integrated Silicon Solution, Inc.- www.issi.com Rev. A2 08/28/2020 OUTPUT 5pF, Including jig and scope R2R2 5 IS61WV25616EDALL DC ELECTRICAL CHARACTERISTICS IS61(64)WV25616EEBLL DC ELECTRICAL CHARACTERISTICS-I (OVER THE OPERATING RANGE) VDD = 1.65V – 2.2V Symbol Parameter Test Conditions Min. Max. VOH Output HIGH Voltage IOH = -0.1 mA 1.4 — VOL Output LOW Voltage IOL = 0.1 mA — 0.2 VIH(1) Input HIGH Voltage 1.4 VDD + 0.2 VIL(1) Input LOW Voltage –0.2 0.4 ILI Input Leakage GND < VIN < VDD –1 1 ILO Output Leakage GND < VIN < VDD, Output Disabled –1 1 Notes: 1. 2. Unit V V V V µA µA VILL(min) = -1.0V AC (pulse width < 20ns). Not 100% tested. VIHH (max) = VDD + 1.0V AC (pulse width < 20ns). Not 100% tested. POWER SUPPLY CHARACTERISTICS-II FOR POWER (OVER THE OPERATING RANGE) Symbol Parameter ICC VDD Dynamic Operating Supply Current ICC1 Operating Supply Current ISB1 TTL Standby Current (TTL Inputs) ISB2 CMOS Standby Current (CMOS Inputs) Test Conditions VDD = MAX, IOU T = 0 mA, f = fMAX VDD = MAX, IOUT = 0 mA, f = 0 VDD = MAX, VIN = VIH or VIL CS# ≥ VIH , f = 0 VDD = MAX, CS# ≥ VDD - 0.2V VIN ≥ VDD - 0.2V , or VIN ≤ 0.2V , f =0 Notes: 1. 2. Grade Com. Ind. Auto. Com. Ind. Auto. Com. Ind. Auto. Com. -20 Max 25 30 20 25 10 15 5 Ind. 6 Auto. - Typ. (2) Unit mA mA mA mA 1.5 At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input line change. Typical values are measured at VDD = 1.8V, TA = 25 °C and not 100% tested. Integrated Silicon Solution, Inc.- www.issi.com Rev. A2 08/28/2020 6 IS61WV25616EDALL AC CHARACTERISTICS (OVER OPERATING RANGE) READ CYCLE AC CHARACTERISTICS Parameter Symbol Read Cycle Time Address Access Time Output Hold Time CS# Access Time OE# Access Time OE# to High-Z Output OE# to Low-Z Output CS# to High-Z Output CS# to Low-Z Output UB#, LB# Access Time UB#, LB# to High-Z Output UB#, LB# to Low-Z Output tRC tAA tOHA tACE tDOE tHZOE tLZOE tHZCE tLZCE tBA tHZB tLZB Notes: 1. 2. -20(1) Min 20 2.5 0 0 0 3 0 0 Max 20 20 8 8 8 8 8 - unit ns ns ns ns ns ns ns ns ns ns ns ns notes 2 2 2 2 2 2 Test conditions assume signal transition times of 3 ns or less, timing reference levels of VDD/2, and output loading specified in Figure 1. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. Integrated Silicon Solution, Inc.- www.issi.com Rev. A2 08/28/2020 7 IS61WV25616EDALL Timing Diagram READ CYCLE NO. 1(1,2) (ADDRESS CONTROLLED , CS#, OE#, UB#, LB# = LOW, WE# = HIGH) tRC Address tAA tOHA tOHA DQ 0-15 Note: 1. PREVIOUS DATA VALID DATA VALID The device is continuously selected. READ CYCLE NO. 2(1) (OE# CONTROLLED) tRC ADDRESS tOHA tAA tDOE OE# tLZOE tHZOE CS# tACS tHZCS tLZCS UB#,LB# tBA tLZB DOUT HIGH-Z LOW-Z tHZB DATA VALID Notes: 1. Address is valid prior to or coincident with CS# LOW transition. Integrated Silicon Solution, Inc.- www.issi.com Rev. A2 08/28/2020 8 IS61WV25616EDALL WRITE CYCLE AC CHARACTERISTICS Parameter Symbol Write Cycle Time tWC tSCS tAW tPWB tHA tSA tPWE1 tPWE2 tSD tHD tHZWE tLZWE CS# to Write End Address Setup Time to Write End UB#,LB# to Write End Address Hold from Write End Address Setup Time WE# Pulse Width WE# Pulse Width (OE# = LOW) Data Setup to Write End Data Hold from Write End WE# LOW to High-Z Output WE# HIGH to Low-Z Output Notes: 1 2 3 4 -20(1) Min 20 12 12 12 0 0 12 17 9 0 3 Max 9 - unit ns ns ns ns ns ns ns ns ns ns ns ns notes 2 Test conditions assume signal transition times of 3 ns or less, timing reference levels of VDD/2, and output loading specified in Figure 1. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. The internal write time is defined by the overlap of CS# = LOW, UB# or LB# = LOW, and WE# = LOW. All signals must be in valid states to initiate a Write, but anyone can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. If OE# is LOW during write cycle, (WE# controlled, CS# = UB# = LB# = LOW), the minimum Write cycle time for write cycle NO.3 is the sum of tHZWE and tSD Integrated Silicon Solution, Inc.- www.issi.com Rev. A2 08/28/2020 9 IS61WV25616EDALL Timing Diagram WRITE CYCLE NO. 1(1) (WE# CONTROLLED, OE# = HIGH OR LOW) tWC ADDRESS tSA tSCS tHA CS# WE# tAW tPWE1 tPWE2 UB#,LB# tPBW tHZWE tLZWE HIGH-Z DATA UNDEFINED DOUT tHD tSD DATA IN VALID DIN Notes: 1. tHZWE is based on the assumption when tSA=0nS after READ operation. Actual DOUT for tHZWE may not appear if OE# goes high before Write Cycle. WRITE CYCLE NO. 2 (WE# CONTROLLED) tWC ADDRESS OE# tSCS tHA CS# tAW tPWE1 WE# tSA tPWB UB#,LB# tHZWE DOUT tLZWE HIGHZ DATA UNDEFINED tSD DIN Integrated Silicon Solution, Inc.- www.issi.com Rev. A2 08/28/2020 tHD DATA IN VALID 10 IS61WV25616EDALL WRITE CYCLE NO. 3 (WE# CONTROLLED, OE#, CS#, UB #, LB# = LOW) ADDRESS OE# = LOW tPWE2 WE# tHZWE DOUT HIGH-Z DATA UNDEFINED DATA IN VALID DIN WRITE CYCLE NO. 4 (UB# & LB# Controlled) tWC ADDRESS tWC ADDRESS 1 ADDRESS 2 CS#=LOW OE#=LOW tSA tHA WE# tHA tSA tPWB UB#, LB# tPWB WORD 1 WORD 2 tHZWE DOUT tLZWE HIGH-Z DATA UNDEFINED tHD tSD DIN DATA IN VALID Integrated Silicon Solution, Inc.- www.issi.com Rev. A2 08/28/2020 DATA IN VALID 11 IS61WV25616EDALL DATA RETENTION CHARACTERISTICS Symbol Parameter Test Condition VDR VDD for Data Retention See Data Retention Waveform Data Retention Current VDD = MAX, CS# ≥ VDD – 0.2V, VIN ≥ VDD - 0.2V, or VIN ≤ 0.2V See Data Retention Waveform IDR tSDR Data Retention Setup Time tRDR Recovery Time Min. Typ.(2) Max. Unit 1.2 - - V Com. - 0.5 5 mA Ind. - - 6 0 - - tRC - - OPTION See Data Retention Waveform ns ns Notes: 1. If CS# >VDD–0.2V, all other inputs including UB# and LB# must meet this condition. 2. Typical values are measured at VDD= 1.8V, TA = 25℃ and not 100% tested. DATA RETENTION WAVEFORM (CS# CONTROLLED) tSDR Data Retention Mode tRDR VDD VDR CS# > VDD – 0.2V CS# GND Integrated Silicon Solution, Inc.- www.issi.com Rev. A2 08/28/2020 12 IS61WV25616EDALL ORDERING INFORMATION Industrial Range: –40°C to +85°C Speed (ns) 20 20 Order Part No. Package IS61WV25616EDALL-20BLI IS61WV25616EDALL-20TLI mini BGA (6mm x 8mm), Lead-free TSOP (Type II), Lead-free Integrated Silicon Solution, Inc.- www.issi.com Rev. A2 08/28/2020 13 IS61WV25616EDALL PACKAGE INFORMATION Integrated Silicon Solution, Inc.- www.issi.com Rev. A2 08/28/2020 14 IS61WV25616EDALL Integrated Silicon Solution, Inc.- www.issi.com Rev. A2 08/28/2020 15