IS61WV25632ALL/ALS
IS61WV25632BLL/BLS
IS64WV25632BLL/BLS
256K x 32 HIGH-SPEED ASYNCHRONOUS
CMOS STATIC RAM WITH 3.3V SUPPLY
FEATURES
• High-speed access times:
8, 10, 20 ns
• High-performance, low-power CMOS process
• Multiple center power and ground pins for
greater noise immunity
• Easy memory expansion with CE and OE options
• CE power-down
• Fully static operation: no clock or refresh
required
• TTL compatible inputs and outputs
• Single power supply
Vdd 1.65V to 2.2V (IS61WV25632Axx)
speed = 20ns for Vdd 1.65V to 2.2V
Vdd 2.4V to 3.6V (IS61/64WV25632Bxx)
speed = 10ns for Vdd 2.4V to 3.6V
speed = 8ns for Vdd 3.3V + 5%
• Packages available:
– 90-ball miniBGA (8mm x 13mm)
• Industrial and Automotive Temperature Support
• Lead-free available
PRELIMINARY INFORMATION
APRIL 2008
DESCRIPTION
The ISSI IS61WV25632Axx/Bxx and IS64WV25632Bxx
are high-speed, 8M-bit static RAMs organized as 256K
words by 32 bits. It is fabricated using ISSI's high-performance CMOS technology. This highly reliable process
coupled with innovative circuit design techniques, yields
high-performance and low power consumption devices.
When CE is HIGH (deselected), the device assumes
a standby mode at which the power dissipation can be
reduced down with CMOS input levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs, CE and OE. The active LOW
Write Enable (WE) controls both writing and reading of
the memory.
The device is packaged in the JEDEC standard 90-ball
BGA (8mm x 13mm).
FUNCTIONAL BLOCK DIAGRAM
A0-A17
DECODER
256K x 32
MEMORY ARRAY
I/O
DATA
CIRCUIT
COLUMN I/O
VDD
VSS
DQa-d
CE
OE
WE
CONTROL
CIRCUIT
BWa-d
CE2
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the
latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00B
04/23/08
1
IS61WV25632ALL/ALS
IS61WV25632BLL/BLS
IS64WV25632BLL/BLS
PIN CONFIGURATION
package code: B 90 bALL fbga (Top View) (8.00 mm x 13.00 mm Body, 0.8 mm Ball Pitch)
1 2 3 4 5 6 7 8 9
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
DQ1 DQ0 VSS
VDD DQ31 DQ30
DQ2 VDD VSS
VDD
VSS DQ3 DQ4
DQ27 DQ28 VDD
VSS DQ6 DQ5
DQ26 DQ25 VDD
VSS DQ29
VDD DQ7
NC
NC
DQ24 VSS
VSS BWa
A3
A4
BWd VDD
A0
A1
A2
A10
A5
A6
A15
A14
A13
A8
A7
A11
CE2
A17
A16
A9
A12
CE
BWb
NC
NC
OE
WE
BWc
VDD DQ8 VSS
VDD DQ23 VSS
VSS DQ9 DQ10
DQ21 DQ22 VDD
VSS DQ12 DQ11
DQ20 DQ19 VDD
DQ13 VDD VSS
VDD
VSS DQ18
DQ14 DQ15 VSS
VDD DQ16 DQ17
PIN DESCRIPTIONS
A0-A17
DQx
CE, CE2
OE
WE
BWx (x=a-d)
Vdd
Vss
NC
2
Address Inputs
Data I/O
Chip Enable Input
Output Enable Input
Write Enable Input
Byte Write Control
Power
Ground
No Connection
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00B
04/23/08
IS61WV25632ALL/ALS
IS61WV25632BLL/BLS
IS64WV25632BLL/BLS
TRUTH TABLE
CE CE2 OE WE BWa BWb BWc BWd DQ0-7
DQ8-15 DQ16-23 DQ24-31
H
X
X
X
X
X
X
X
High-Z High-Z
High-Z
High-Z
X
L
X
X
X
X
X
X
High-Z High-Z
High-Z
High-Z
L
H
L
H
L
L
L
L Data Out Data Out Data Out Data Out
L
H
L
H
L
H
H
H Data Out High-Z
High-Z
High-Z
L
H
L
H
H
L
H
H
High-Z Data Out High-Z
High-Z
L
H
L
H
H
H
L
H
High-Z High-Z Data Out High-Z
L
H
L
H
H
H
H
L
High-Z High-Z
High-Z Data Out
L
H
X
L
L
L
L
L
Data In Data In Data In Data In
L
H
X
L
L
H
H
H
Data In High-Z
High-Z
High-Z
L
H
X
L
H
L
H
H
High-Z Data In High-Z
High-Z
L
H
X
L
H
H
L
H
High-Z High-Z Data In High-Z
L
H
X
L
H
H
H
L
High-Z High-Z
High-Z Data In
L
H
H
H
X
X
X
X
High-Z High-Z
High-Z
High-Z
Mode
Power
Power Down (Isb)
Power Down (Isb)
Read All Bits (Icc)
Read Byte a (Icc)
Bits Only
Read Byte b (Icc)
Bits Only
Read Byte c (Icc)
Bits Only
Read Byte d (Icc)
Bits Only
Write All Bits (Icc)
Write Byte a (Icc)
Bits Only
Write Byte b (Icc)
Bits Only
Write Byte c (Icc)
Bits Only
Write Byte d (Icc)
Bits Only
Selected,
(Icc)
Outputs
Disabled
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Vterm
Vdd
Tstg
Pt
Parameter
Terminal Voltage with Respect to GND
Vdd Relates to GND
Storage Temperature
Power Dissipation
Value
Unit
–0.5 to Vdd + 0.5
V
–0.3 to 4.0
V
–65 to +150
°C
1.0
W
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
CAPACITANCE(1,2)
Symbol
Cin
CI/O
Parameter
Input Capacitance
Input/Output Capacitance
Conditions
Vin = 0V
Vout = 0V
Max.
6
8
Unit
pF
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: Ta = 25°C, f = 1 MHz, Vdd = 3.3V.
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00B
04/23/08
3
IS61WV25632ALL/ALS
IS61WV25632BLL/BLS
IS64WV25632BLL/BLS
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Vdd = 3.3V + 5%
Symbol
Voh
Vol
Vih
Vil
Ili
Ilo
Parameter
Test Conditions
Output HIGH Voltage
Vdd = Min., Ioh = –4.0 mA
Output LOW Voltage
Vdd = Min., Iol = 8.0 mA
Input HIGH Voltage
Input LOW Voltage(1)
Input Leakage
GND ≤ Vin ≤ Vdd
Output Leakage
GND ≤ Vout ≤ Vdd, Outputs Disabled
Min.
2.4
—
2
–0.3
–1
–1
Max.
—
0.4
Vdd + 0.3
0.8
1
1
Unit
V
V
V
V
µA
µA
Min.
1.8
—
2.0
–0.3
–1
–1
Max.
—
0.4
Vdd + 0.3
0.8
1
1
Unit
V
V
V
V
µA
µA
Note:
1. Vil (min.) = –0.3V DC; Vil (min.) = –2.0V AC (pulse width 2.0 ns). Not 100% tested.
Vih (max.) = Vdd + 0.3V DC; Vih (max.) = Vdd + 2.0V AC (pulse width 2.0 ns). Not 100% tested.
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Vdd = 2.4V-3.6V
Symbol
Voh
Vol
Vih
Vil
Ili
Ilo
Parameter
Test Conditions
Output HIGH Voltage
Vdd = Min., Ioh = –1.0 mA
Output LOW Voltage
Vdd = Min., Iol = 1.0 mA
Input HIGH Voltage
Input LOW Voltage(1)
Input Leakage
GND ≤ Vin ≤ Vdd
Output Leakage
GND ≤ Vout ≤ Vdd, Outputs Disabled
Note:
1. Vil (min.) = –0.3V DC; Vil (min.) = –2.0V AC (pulse width 2.0 ns). Not 100% tested.
Vih (max.) = Vdd + 0.3V DC; Vih (max.) = Vdd + 2.0V AC (pulse width 2.0 ns). Not 100% tested.
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Vdd = 1.65V-2.2V
Symbol
Voh
Vol
Vih
Vil(1)
Ili
Ilo
Parameter
Test Conditions
Vdd
Output HIGH Voltage
Ioh = -0.1 mA
1.65-2.2V
Output LOW Voltage
Iol = 0.1 mA
1.65-2.2V
Input HIGH Voltage
1.65-2.2V
Input LOW Voltage
1.65-2.2V
Input Leakage
GND ≤ Vin ≤ Vdd
Output Leakage
GND ≤ Vout ≤ Vdd, Outputs Disabled
Min.
1.4
—
1.4
–0.2
–1
–1
Max.
—
0.2
Vdd + 0.2
0.4
1
1
Unit
V
V
V
V
µA
µA
Notes:
1. Vil (min.) = –0.3V DC; Vil (min.) = –2.0V AC (pulse width -2.0ns). Not 100% tested.
Vih (max.) = Vdd + 0.3V DC; Vih (max.) = Vdd + 2.0V AC (pulse width -2.0ns). Not 100% tested.
4
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Rev. 00B
04/23/08
IS61WV25632ALL/ALS
IS61WV25632BLL/BLS
IS64WV25632BLL/BLS
HIGH SPEED
OPERATING RANGE (Vdd) (IS61WV25632ALL)
Range
Ambient Temperature
Commercial
0°C to +70°C
Industrial
–40°C to +85°C
Automotive
–40°C to +125°C
Vdd
1.65V-2.2V
1.65V-2.2V
1.65V-2.2V
OPERATING RANGE (Vdd) (IS61WV25632BLL)(1)
Range
Ambient Temperature
Commercial
0°C to +70°C
Industrial
–40°C to +85°C
Vdd (8 ns)1
3.3V + 5%
3.3V + 5%
Speed
20ns
20ns
20ns
Vdd (10 ns)1
2.4V-3.6V
2.4V-3.6V
Note:
1. When operated in the range of 2.4V-3.6V, the device meets 10ns. When operated in the range of 3.3V + 5%,
the device meets 8ns.
OPERATING RANGE (Vdd) (IS64WV25632BLL)
Range
Ambient Temperature
Automotive
–40°C to +125°C
Vdd (10 ns)
2.4V-3.6V
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-8
Symbol Parameter
Test Conditions Min. Max.
Icc
Vdd Dynamic Operating Vdd = Max.,
Com.
—
110
Supply Current
Iout = 0 mA, f = fmax
Ind.
—
115
Auto.
—
—
typ.(2)
Icc1
Operating
Vdd = Max.,
Com.
—
85
Supply Current
Iout = 0 mA, f = 0
Ind.
—
90
Auto.
—
—
Isb1
TTL Standby Current
Vdd = Max.,
Com.
—
30
(TTL Inputs)
Vin = Vih or Vil
Ind.
—
35
CE ≥ Vih, f = 0
Auto.
—
—
Isb2
CMOS Standby
Vdd = Max.,
Com.
—
20
Current (CMOS Inputs) CE ≥ Vdd – 0.2V,
Ind.
—
25
Vin ≥ Vdd – 0.2V, or
Auto.
—
—
Vin ≤ 0.2V, f = 0
typ.(2)
-10
Min. Max.
—
90
—
95
— 140
60
—
85
—
90
— 110
—
30
—
35
—
70
—
20
—
25
—
60
4
-20
Min. Max.
Unit
—
50
mA
—
60
— 100
—
—
—
—
—
—
—
—
—
45
mA
55
90
30
mA
35
70
20
mA
25
60
Note:
1. At f = fmax, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
2. Typical values are measured at Vdd = 3.0V, Ta = 25oC and not 100% tested.
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00B
04/23/08
5
IS61WV25632ALL/ALS
IS61WV25632BLL/BLS
IS64WV25632BLL/BLS
LOW POWER
OPERATING RANGE (Vdd) (IS61WV25632ALS)
Range
Ambient Temperature
Commercial
0°C to +70°C
Industrial
–40°C to +85°C
Automotive
–40°C to +125°C
Vdd
1.65V-2.2V
1.65V-2.2V
1.65V-2.2V
Speed
35ns
35ns
35ns
OPERATING RANGE (Vdd) (IS61WV25632BLS)(1)
Range
Ambient Temperature
Commercial
0°C to +70°C
Industrial
–40°C to +85°C
Vdd (25 ns)1
2.4V-3.6V
2.4V-3.6V
Note:
1. When operated in the range of 2.4V-3.6V, the device meets 25ns. When operated in the
range of 3.3V + 5%, the device meets 20ns.
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-25
Symbol Parameter
Test Conditions Min. Max.
Icc
Vdd Dynamic Operating Vdd = Max.,
Com.
—
30
Supply Current
Iout = 0 mA, f = fmax
Ind.
—
35
Auto.
—
60
typ.(2)
25
Icc1
Operating
Vdd = Max.,
Com.
—
20
Supply Current
Iout = 0 mA, f = 0
Ind.
—
30
Auto.
—
50
Isb1
TTL Standby Current
Vdd = Max.,
Com.
—
15
(TTL Inputs)
Vin = Vih or Vil
Ind.
—
20
CE ≥ Vih, f = 0
Auto.
—
40
Isb2
CMOS Standby
Vdd = Max.,
Com.
—
0.8
Current (CMOS Inputs) CE ≥ Vdd – 0.2V,
Ind.
—
1.2
Vin ≥ Vdd – 0.2V, or
Auto.
—
2
Vin ≤ 0.2V, f = 0
typ.(2)
0.1
-35
Min. Max.
Unit
—
25
mA
—
30
—
60
—
—
—
—
—
—
—
—
—
0.1
20
mA
30
50
15
mA
20
40
0.8
mA
1.2
2
Note:
1. At f = fmax, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
2. Typical values are measured at Vdd = 3.0V, Ta = 25oC and not 100% tested.
6
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Rev. 00B
04/23/08
IS61WV25632ALL/ALS
IS61WV25632BLL/BLS
IS64WV25632BLL/BLS
AC TEST CONDITIONS (HIGH SPEED)
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Level (VRef)
Output Load
Unit
(2.4V-3.6V)
0.4V to Vdd-0.3V
1.5ns
Vdd/2
Unit
(3.3V + 5%)
0.4V to Vdd-0.3V
1.5ns
Vdd/2 + 0.05
Unit
(1.65V-2.2V)
0.4V to Vdd-0.2V
1.5ns
Vdd/2
See Figures 1 and 2
See Figures 1 and 2
See Figures 1 and 2
AC TEST LOADS
319 Ω
ZO = 50Ω
3.3V
50Ω
1.5V
OUTPUT
30 pF
Including
jig and
scope
Figure 1.
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00B
04/23/08
OUTPUT
5 pF
Including
jig and
scope
353 Ω
Figure 2.
7
IS61WV25632ALL/ALS
IS61WV25632BLL/BLS
IS64WV25632BLL/BLS
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
-8
Symbol
Parameter Min. Max.
trc
Read Cycle Time
8
—
taa
Address Access Time —
8
toha
Output Hold Time 2.5
—
tace
CE Access Time —
8
tdoe
OE Access Time —
5.5
thzoe(2)
OE to High-Z Output —
3
(2)
tlzoe
OE to Low-Z Output
0
—
thzce(2
CE to High-Z Output
0
3
(2)
tlzce
CE to Low-Z Output
3
—
tba
Byte Enable to Data Valid —
5.5
tlzb
Byte Enable to Low-Z
0
—
thzb
Byte Enable to High-Z
0
3
-10
Min. Max.
10 —
— 10
2.5 —
— 10
— 6.5
—
4
0
—
0
4
3
—
— 6.5
0
—
0
3
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to 3.0V
and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage.
8
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00B
04/23/08
IS61WV25632ALL/ALS
IS61WV25632BLL/BLS
IS64WV25632BLL/BLS
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
Symbol
Parameter
trc
Read Cycle Time
taa
Address Access Time
toha
Output Hold Time
tace
CE Access Time
tdoe
OE Access Time
thzoe(2)
OE to High-Z Output
tlzoe(2)
OE to Low-Z Output
(2
thzce
CE to High-Z Output
(2)
tlzce
CE to Low-Z Output
tba
Byte Enable to Data Valid
tlzb
Byte Enable to Low-Z
thzb
Byte Enable to High-Z
-20 ns
Min. Max.
20
—
—
20
2.5
—
—
20
—
8
0
8
0
—
0
8
3
—
—
8
0
—
0
3
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
1. Test conditions assume signal transition times of 1.5 ns or less, timing reference levels of 1.25V, input pulse levels of 0.4V to
Vdd-0.3V and output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. Not 100% tested.
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Rev. 00B
04/23/08
9
IS61WV25632ALL/ALS
IS61WV25632BLL/BLS
IS64WV25632BLL/BLS
AC WAVEFORMS
READ CYCLE NO. 1(1,2) (Address Controlled) (CE = OE = Vil)
t RC
ADDRESS
t OHA
DOUT
t AA
t OHA
DATA VALID
PREVIOUS DATA VALID
READ1.eps
READ CYCLE NO. 2(1,3) (CE and OE Controlled)
t RC
ADDRESS
t AA
t OHA
OE
CE
t LZCE
DOUT
t HZOE
t DOE
t BA
BWa-d
t HZB
t LZB
t LZOE
t ACE
HIGH-Z
t HZCE
DATA VALID
CE_RD2.eps
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE = Vil.
3. Address is valid prior to or coincident with CE LOW transitions.
10
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Rev. 00B
04/23/08
IS61WV25632ALL/ALS
IS61WV25632BLL/BLS
IS64WV25632BLL/BLS
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range)
Symbol
twc
tsce
taw
tha
tsa
tpwb
tpwe1
tpwe2
tsd
thd
thzwe(2)
tlzwe(2)
Parameter
Write Cycle Time
CE to Write End
Address Setup Time
to Write End
Address Hold from Write End
Address Setup Time
BWa-d Valid to End of Write
WE Pulse Width
WE Pulse Width (OE = LOW)
Data Setup to Write End
Data Hold from Write End
WE LOW to High-Z Output
WE HIGH to Low-Z Output
-8
Min.
8
6.5
6.5
Max.
—
—
—
-10
Min. Max.
10
—
8
—
8
—
Unit
ns
ns
ns
0
0
6.5
6.5
8.0
5
—
—
—
—
—
—
0
0
8
8
10
6
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
0
—
2
—
3.5
—
0
—
2
— ns
5
ns
—
ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to 3.0V and
output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE LOW, and WE LOW. All signals must be in valid states to initiate a Write, but
any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of
the signal that terminates the write. Shaded area product in development
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00B
04/23/08
11
IS61WV25632ALL/ALS
IS61WV25632BLL/BLS
IS64WV25632BLL/BLS
WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range)
Symbol
Parameter
twc
Write Cycle Time
tsce
CE to Write End
taw
Address Setup Time
to Write End
tha
Address Hold from Write End
tsa
Address Setup Time
tpwb
BWa-d Valid to End of Write
tpwe1
WE Pulse Width (OE = HIGH)
tpwe2
WE Pulse Width (OE = LOW)
tsd
Data Setup to Write End
thd
Data Hold from Write End
thzwe
tlzwe(3)
(3)
WE LOW to High-Z Output
WE HIGH to Low-Z Output
-20 ns
Min. Max. Unit
20
— ns
12
— ns
12
— ns
0
0
12
12
17
9
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
0
—
3
— ns
9 ns
— ns
Notes:
1. Test conditions assume signal transition times of 3ns or less, timing reference levels of 1.5V, input
pulse levels of 0V to 0.3V and output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not
100% tested.
3. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid
states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup
and Hold timing are referenced to the rising or falling edge of the signal that terminates the write.
12
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Rev. 00B
04/23/08
IS61WV25632ALL/ALS
IS61WV25632BLL/BLS
IS64WV25632BLL/BLS
AC WAVEFORMS
WRITE CYCLE NO. 1(1,2) (CE Controlled, OE = HIGH or LOW)
t WC
VALID ADDRESS
ADDRESS
t SA
t SCE
t HA
CE
t AW
t PWE1
t PWE2
WE
t HZWE
DOUT
DATA UNDEFINED
t LZWE
HIGH-Z
t SD
DIN
t HD
DATAIN VALID
CE_WR1.eps
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00B
04/23/08
13
IS61WV25632ALL/ALS
IS61WV25632BLL/BLS
IS64WV25632BLL/BLS
AC WAVEFORMS
WRITE CYCLE NO. 2 (WE Controlled. OE is HIGH During Write Cycle) (1,2)
t WC
ADDRESS
VALID ADDRESS
t HA
OE
CE
LOW
t AW
t PWE1
WE
t SA
t PBW
BWa-d
t HZWE
DOUT
t LZWE
HIGH-Z
DATA UNDEFINED
t SD
t HD
DATAIN VALID
DIN
UB_CEWR2.eps
WRITE CYCLE NO. 3 (WE Controlled. OE is LOW During Write Cycle) (1)
t WC
ADDRESS
VALID ADDRESS
OE
LOW
CE
LOW
t HA
t AW
t PWE2
WE
t SA
t PBW
BWa-d
t HZWE
DOUT
DATA UNDEFINED
t LZWE
HIGH-Z
t SD
DIN
t HD
DATAIN VALID
UB_CEWR3.eps
14
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00B
04/23/08
IS61WV25632ALL/ALS
IS61WV25632BLL/BLS
IS64WV25632BLL/BLS
AC WAVEFORMS
WRITE CYCLE NO. 4 (Byte Controlled, Back-to-Back Write) (1,3)
t WC
ADDRESS
t WC
ADDRESS 1
ADDRESS 2
OE
t SA
CE
LOW
t HA
t SA
WE
BWa-d
t HA
t PBW
t PBW
WORD 1
WORD 2
t HZWE
DOUT
t LZWE
HIGH-Z
DATA UNDEFINED
t HD
t SD
DIN
DATAIN
VALID
t HD
t SD
DATAIN
VALID
UB_CEWR4.eps
Notes:
1. The internal Write time is defined by the overlap of and WE = LOW. All signals must be in valid states to initiate a Write, but any can be
deasserted to terminate the Write. The t sa, t ha, t sd, and t hd timing is referenced to the rising or falling edge of the signal that terminates the
Write.
2. Tested with OE HIGH for a minimum of 4 ns before WE = LOW to place the I/O in a HIGH-Z state.
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00B
04/23/08
15
IS61WV25632ALL/ALS
IS61WV25632BLL/BLS
IS64WV25632BLL/BLS
DATA RETENTION SWITCHING CHARACTERISTICS (HIGH SPEED) (IS61WV25632ALL/BLL)
Symbol
Parameter
Test Condition
Vdr
Vdd for Data Retention
See Data Retention Waveform
Idr
Data Retention Current
Vdd = 1.2V, CE ≥ Vdd – 0.2V
Ind.
Auto.
tsdr
Data Retention Setup Time
See Data Retention Waveform
trdr
Recovery Time
See Data Retention Waveform
Min.
1.2
—
—
0
trc
Max.
3.6
25
60
—
—
Unit
V
mA
ns
ns
DATA RETENTION WAVEFORM (CE Controlled)
tSDR
Data Retention Mode
tRDR
VDD
1.65V
1.4V
VDR
CE
GND
16
CE ≥ VDD - 0.2V
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00B
04/23/08
IS61WV25632ALL/ALS
IS61WV25632BLL/BLS
IS64WV25632BLL/BLS
DATA RETENTION SWITCHING CHARACTERISTICS (LOW POWER) (IS61WV25632ALS/BLS)
Symbol
Parameter
Test Condition
Vdr
Vdd for Data Retention
See Data Retention Waveform
Idr
Data Retention Current
Vdd = 1.2V, CE ≥ Vdd – 0.2V
Ind.
Auto.
tsdr
Data Retention Setup Time
See Data Retention Waveform
trdr
Recovery Time
See Data Retention Waveform
Min.
1.2
—
—
0
trc
Max.
3.6
1.2
2
—
—
Unit
V
mA
ns
ns
DATA RETENTION WAVEFORM (CE Controlled)
tSDR
Data Retention Mode
tRDR
VDD
1.65V
1.4V
VDR
CE
GND
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00B
04/23/08
CE ≥ VDD - 0.2V
17
IS61WV25632ALL/ALS
IS61WV25632BLL/BLS
IS64WV25632BLL/BLS
ORDERING INFORMATION
Industrial Range: -40°C to +85°C
Voltage Range: 2.4V to 3.6V
peed (ns)
S
10 (81)
Order Part No.
Package
IS61WV25632BLL-10BI 90-ball BGA (8mm x 13mm)
IS61WV25632BLL-10BLI 90-ball BGA (8mm x 13mm), Lead-free
Note:
1. Speed = 8ns for Vdd = 3.3V + 5%. Speed = 10ns for Vdd = 2.4V - 3.6V
Industrial Range: -40°C to +85°C
Voltage Range: 1.65V to 2.2V
peed (ns)
S
20
Order Part No.
IS61WV25632ALL-20BI
Package
90-ball BGA (8mm x 13mm)
Automotive Range: -40°C to +125°C
Voltage Range: 2.4V to 3.6V
peed (ns)
S
10
18
Order Part No.
Package
IS64WV25632BLL-10BA3 90-ball BGA (8mm x 13mm)
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00B
04/23/08
IS61WV25632ALL/ALS
IS61WV25632BLL/BLS
IS64WV25632BLL/BLS
D1
0.80
Package Outline
0.45
NOTE :
1. CONTROLLING DIMENSION : MM .
2. Reference document : JEDEC MO-207
08/14/2008
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00B
04/23/08
19
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