IS61WV3216BLL

IS64WV3216BLL IS61WV3216BLL 32K x 16 HIGH-SPEED CMOS STATIC RAM ISSI NOVEMBER 2005 ® FEATURES • High-speed access time: 12 ns: 3.3V + 10% 15 ns: 2.5V-3.6V • CMOS low power operation: 50 mW (typical) operating 25 µW (typical) standby • TTL compatible interface levels • Fully static operation: no clock or refresh required • Three state outputs • Data control for upper and lower bytes • Automotive Temperature Available • Lead-free available DESCRIPTION The ISSI IS61/64WV3216BLL is a high-speed, 524,288-bit static RAM organized as 32,768 words by 16 bits. It is fabricated using I SSI 's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields access times as fast as 12ns (3.3V + 10%) and 15ns (2.5V-3.6V) with low power consumption. When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs, CE and OE. The active LOW Write Enable (WE) controls both writing and reading of the memory. A data byte allows Upper Byte (UB) and Lower Byte (LB) access. The IS61/64WV3216BLL is packaged in the JEDEC standard 44-pin TSOP-II, and 48-pin mini BGA (6mm x 8mm). FUNCTIONAL BLOCK DIAGRAM A0-A14 DECODER 32K x 16 MEMORY ARRAY VDD GND I/O0-I/O7 Lower Byte I/O8-I/O15 Upper Byte I/O DATA CIRCUIT COLUMN I/O CE OE WE UB LB CONTROL CIRCUIT Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A 09/26/05 1 IS64WV3216BLL IS61WV3216BLL PIN CONFIGURATIONS 48-Pin mini BGA (6mm x 8mm) 1 2 3 4 5 6 NC A14 A13 A12 A11 CE I/O0 I/O1 I/O2 I/O3 VDD GND I/O4 I/O5 I/O6 I/O7 WE A10 A9 A8 A7 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 ISSI 44-Pin TSOP-II ® A B C D E F G H LB I/O8 I/O9 GND VDD I/O14 I/O15 NC OE UB I/O10 I/O11 I/O12 I/O13 NC A8 A0 A3 A5 NC NC A14 A12 A9 A1 A4 A6 A7 NC NC A13 A10 A2 CE I/O1 I/O3 I/O4 I/O5 WE A11 NC I/O0 I/O2 VDD GND I/O6 I/O7 NC 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A0 A1 A2 OE UB LB I/O15 I/O14 I/O13 I/O12 GND VDD I/O11 I/O10 I/O9 I/O8 NC A3 A4 A5 A6 NC PIN DESCRIPTIONS A0-A14 I/O0-I/O15 CE OE WE LB UB NC VDD GND Address Inputs Data Inputs/Outputs Chip Enable Input Output Enable Input Write Enable Input Lower-byte Control (I/O0-I/O7) Upper-byte Control (I/O8-I/O15) No Connection Power Ground 2 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A 09/26/05 IS64WV3216BLL IS61WV3216BLL TRUTH TABLE Mode Not Selected Output Disabled Read WE X H X H H H L L L CE H L L L L L L L L OE X H X L L L X X X LB X X H L H L L H L UB X X H H L L H L L I/O PIN I/O0-I/O7 I/O8-I/O15 High-Z High-Z High-Z DOUT High-Z DOUT DIN High-Z DIN High-Z High-Z High-Z High-Z DOUT DOUT High-Z DIN DIN ISSI VDD Current ISB1, ISB2 ICC ICC ® Write ICC ABSOLUTE MAXIMUM RATINGS(1) Symbol VTERM TSTG PT VDD Parameter Terminal Voltage with Respect to GND Storage Temperature Power Dissipation VDD Related to GND Value –0.5 to VDD+0.5 –65 to +150 1.5 -0.2 to +3.9 Unit V °C W V Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. OPERATING RANGE (VDD) Range Commercial Industrial Automotive Ambient Temperature 0°C to +70°C –40°C to +85°C –40°C to +125°C VDD (15 ns) 2.5V-3.6V 2.5V-3.6V 2.5V-3.6V VDD (12 ns) 3.3V + 10% 3.3V + 10% 3.3V + 10% Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A 09/26/05 3 IS64WV3216BLL IS61WV3216BLL DC ELECTRICAL CHARACTERISTICS (Over Operating Range) VDD = 2.5V-3.6V Symbol VOH VOL VIH VIL ILI ILO Note: 1. VIL (min.) = –0.3V DC; VIL (min.) = –2.0V AC (pulse width - 2.0 ns). Not 100% tested. VIH (max.) = VDD + 0.3V DC; VIH (max.) = VDD + 2.0V AC (pulse width - 2.0 ns). Not 100% tested. ISSI Test Conditions VDD = Min., IOH = –1.0 mA VDD = Min., IOL = 1.0 mA Min. 2.3 — 2.0 –0.3 GND ≤ VIN ≤ VDD GND ≤ VOUT ≤ VDD, Outputs Disabled –2 –2 Max. — 0.4 VDD + 0.3 0.8 2 2 Unit V V V V µA µA ® Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage(1) Input Leakage Output Leakage DC ELECTRICAL CHARACTERISTICS (Over Operating Range) VDD = 3.3V + 10% Symbol VOH VOL VIH VIL ILI ILO Note: 1. VIL (min.) = –0.3V DC; VIL (min.) = –2.0V AC (pulse width - 2.0 ns). Not 100% tested. VIH (max.) = VDD + 0.3V DC; VIH (max.) = VDD + 2.0V AC (pulse width - 2.0 ns). Not 100% tested. Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage(1) Input Leakage Output Leakage Test Conditions VDD = Min., IOH = –4.0 mA VDD = Min., IOL = 8.0 mA Min. 2.4 — 2 –0.3 Max. — 0.4 VDD + 0.3 0.8 2 2 Unit V V V V µA µA GND ≤ VIN ≤ VDD GND ≤ VOUT ≤ VDD, Outputs Disabled –2 –2 4 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A 09/26/05 IS64WV3216BLL IS61WV3216BLL POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter ICC VDD Dynamic Operating Supply Current Test Conditions VDD = Max., IOUT = 0 mA, f = fMAX Options COM. IND. AUTO ISSI -12 ns Min. Max. — — — — — — — — — — — 35 45 60 20 5 5 5 20 50 75 6 -15 ns Min. Max. — — — — — — — — — — — 30 40 50 20 5 5 5 20 50 75 6 Unit mA ® typ.(2) ICC1 Operating Supply Current CMOS Standby Current (CMOS Inputs) VDD = Max., Iout = 0mA, f = 0 VDD = Max., CE ≥ VDD – 0.2V, VIN ≥ VDD – 0.2V, or VIN ≤ 0.2V, f = 0 COM. IND. AUTO mA ISB2 COM. IND. AUTO uA typ.(2) Note: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. Typical values are measured at VDD=2.5V, TA=25oC. Not 100% tested. CAPACITANCE(1) Symbol CIN COUT Parameter Input Capacitance Input/Output Capacitance Conditions VIN = 0V VOUT = 0V Max. 6 8 Unit pF pF Note: 1. Tested initially and after any design or process changes that may affect these parameters. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A 09/26/05 5 IS64WV3216BLL IS61WV3216BLL AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level (VRef) Output Load Unit (2.5V-3.6V) 0V to VDD V 1.5ns VDD/2 See Figures 1a and 1b Unit (3.3V + 10%) 0V to VDD V 1.5ns VDD/2 + 0.05 See Figures 1a and 1b ISSI ® AC TEST LOADS 319 Ω Zo=50Ω OUTPUT 50Ω VRef 30 pF Including jig and scope 2.5V OUTPUT 5 pF Including jig and scope Figure 1b. 353 Ω Figure 1a. 6 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A 09/26/05 IS64WV3216BLL IS61WV3216BLL READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter Read Cycle Time Address Access Time Output Hold Time CE Access Time OE Access Time (2) ISSI -12 ns Min. Max. 12 — 3 — — — 0 0 3 — 0 0 — 12 — 12 6 6 — 6 — 6 6 — -15 ns Min. Max. 15 — 3 — — 0 0 0 3 — 0 0 — 15 — 15 7 6 — 6 — 7 6 — Unit ns ns ns ns ns ns ns ns ns ns ns ns ® tRC tAA tOHA tACE tDOE tHZOE tHZCE tLZCE tBA tHZB tLZB tLZOE(2) (2 (2) OE to High-Z Output OE to Low-Z Output CE to High-Z Output CE to Low-Z Output LB, UB Access Time LB, UB to High-Z Output LB, UB to Low-Z Output Notes: 1. Test conditions assume signal transition times of 1.5 ns or less, timing reference levels of 1.25V, input pulse levels of 0V to VDD V and output loading specified in Figure 1a. 2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3. Not 100% tested. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A 09/26/05 7 IS64WV3216BLL IS61WV3216BLL AC WAVEFORMS READ CYCLE NO. 1(1,2) (Address Controlled) (CS = OE = VIL, UB or LB = VIL) tRC ISSI ® ADDRESS tAA tOHA tOHA DATA VALID DOUT PREVIOUS DATA VALID READ CYCLE NO. 2(1,3) tRC ADDRESS tAA tOHA OE tDOE tHZOE CE tLZCE tLZOE tACE tHZCE LB, UB tBA tHZB DATA VALID DOUT HIGH-Z tLZB Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE, UB, or LB = VIL. 3. Address is valid prior to or coincident with CE LOW transition. 8 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A 09/26/05 IS64WV3216BLL IS61WV3216BLL WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range) Symbol Parameter Write Cycle Time CE to Write End Address Setup Time to Write End Address Hold from Write End Address Setup Time LB, UB Valid to End of Write WE Pulse Width (OE = HIGH) WE Pulse Width (OE = LOW) Data Setup to Write End Data Hold from Write End WE LOW to High-Z Output WE HIGH to Low-Z Output -12 ns Min. Max. 12 9 9 0 0 9 9 11 9 0 — 3 — — — — — — — — — — 6 — -15 ns Min. Max. 15 10 10 0 0 10 10 12 9 0 — 3 — — — — — — — — — — 7 — ISSI Unit ns ns ns ns ns ns ns ns ns ns ns ns ® tWC tSCE tAW tHA tSA tPWB tPWE1 tPWE2 tSD tHD tHZWE(3) tLZWE(3) Notes: 1. Test conditions for IS61WV3216BLL assume signal transition times of 1.5ns or less, timing reference levels of 1.25V, input pulse levels of 0V to VDD V and output loading specified in Figure 1a. 2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A 09/26/05 9 IS64WV3216BLL IS61WV3216BLL WRITE CYCLE NO. 1(1,2) (CE Controlled, OE = HIGH or LOW) ISSI t WC ® ADDRESS VALID ADDRESS t SA CE t SCE t HA WE t AW t PWE1 t PWE2 t PBW UB, LB t HZWE DOUT DATA UNDEFINED HIGH-Z t LZWE t SD DIN t HD DATAIN VALID UB_CEWR1.eps 10 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A 09/26/05 IS64WV3216BLL IS61WV3216BLL WRITE CYCLE NO. 2(1) (WE Controlled, OE = HIGH during Write Cycle) t WC ADDRESS VALID ADDRESS ISSI ® t HA OE CE LOW t AW t PWE1 WE t SA UB, LB t PBW t HZWE DOUT DATA UNDEFINED HIGH-Z t LZWE t SD DIN t HD DATAIN VALID UB_CEWR2.eps WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle) t WC ADDRESS OE CE VALID ADDRESS LOW t HA LOW t AW t PWE2 WE t SA UB, LB t PBW t HZWE DOUT DATA UNDEFINED HIGH-Z t LZWE t SD DIN t HD DATAIN VALID UB_CEWR3.eps Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A 09/26/05 11 IS64WV3216BLL IS61WV3216BLL WRITE CYCLE NO. 4 (LB, UB Controlled, Back-to-Back Write) (1,3) t WC ADDRESS ADDRESS 1 ISSI t WC ADDRESS 2 ® OE t SA CE LOW WE t HA t SA t PBW t PBW WORD 2 t HA UB, LB WORD 1 t HZWE DOUT HIGH-Z t LZWE t HD DATAIN VALID DATA UNDEFINED t SD DIN t SD DATAIN VALID t HD UB_CEWR4.eps Notes: 1. The internal Write time is defined by the overlap of CE = LOW, UB and/or LB = LOW, and WE = LOW. All signals must be in valid states to initiate a Write, but any can be deasserted to terminate the Write. The t SA, t HA, t SD, and t HD timing is referenced to the rising or falling edge of the signal that terminates the Write. 2. Tested with OE HIGH for a minimum of 4 ns before WE = LOW to place the I/O in a HIGH-Z state. 3. WE may be held LOW across many address cycles and the LB, UB pins can be used to control the Write function. 12 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A 09/26/05 IS64WV3216BLL IS61WV3216BLL DATA RETENTION SWITCHING CHARACTERISTICS Symbol Parameter VDD for Data Retention Data Retention Current Test Condition VDD = 1.8V, CE ≥ VDD – 0.2V Operations COM. IND. AUTO ISSI Min. 1.8 — — — 0 Typ.(1) — 6 6 6 — — Max. 3.6 20 50 75 — — Unit V µA See Data Retention Waveform ® VDR IDR tSDR tRDR Note: Data Retention Setup Time Recovery Time See Data Retention Waveform See Data Retention Waveform O ns ns tRC 1. Typical values are measured at VDD = 2.5V, TA = 25 C. Not 100% tested. DATA RETENTION WAVEFORM (CE Controlled) tSDR VDD 1.65V Data Retention Mode tRDR 1.4V VDR CE ≥ VDD - 0.2V CE GND Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A 09/26/05 13 IS64WV3216BLL IS61WV3216BLL ORDERING INFORMATION Industrial Temperature Range: –40°C to +85°C Speed (ns) 12 12 12 12 Order Part No. IS61WV3216BLL-12TI IS61WV3216BLL-12TLI IS61WV3216BLL-12BI IS61WV3216BLL-12BLI Package Plastic TSOP Plastic TSOP, Lead-free mini BGA (6mm x 8mm) mini BGA (6mm x 8mm), Lead-free ISSI ® Temperature Range (A3): –40°C to +125°C Speed (ns) 15 (12*) 15 (12*) 15 (12*) 15 (12*) Order Part No. IS64WV3216BLL-15TA3 IS64WV3216BLL-15TLA3 IS64WV3216BLL-15BA3 IS64WV3216BLL-15BLA3 Package Plastic TSOP Plastic TSOP, Lead-free mini BGA (6mm x 8mm) mini BGA (6mm x 8mm), Lead-free Note: 1. Speed = 12ns for VDD = 3.3V + 10%. Speed = 15ns for VDD = 2.5V- 3.6V. 14 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A 09/26/05 PACKAGING INFORMATION Mini Ball Grid Array Package Code: B (48-pin) Top View 1 2 3 4 56 6 ISSI Bottom View φ b (48x) ® 5 4 3 2 1 A B C D D E F G H D1 e A B C D E F G H e E E1 A2 SEATING PLANE A1 A Notes: 1. Controlling dimensions are in millimeters. mBGA - 6mm x 8mm MILLIMETERS Sym. N0. Leads A A1 A2 D D1 E E1 e b — 0.24 0.60 7.90 5.90 mBGA - 8mm x 10mm INCHES Min. Typ. Max. Sym. N0. Leads MILLIMETER Min. Typ. Max. 48 — 0.24 0.60 9.90 7.90 — — — — — 1.20 0.30 — 10.10 8.10 — INCHES Min. Typ. Max. Min. Typ. Max. 48 — — — — — 1.20 0.30 — 8.10 6.10 — 0.009 0.024 0.311 0.232 — — — — — 0.047 0.012 — 0.319 0.240 A A1 A2 D D1 E E1 e b — — — — — 0.047 0.012 — 0.398 0.319 0.009 0.024 0.390 0.311 5.25 BSC 3.75 BSC 0.75 BSC 0.30 0.35 0.40 0.207 BSC 0.148 BSC 0.030 BSC 0.012 0.014 0.016 5.25 BSC 3.75 BSC 0.75 BSC 0.30 0.35 0.40 0.207 BSC 0.148 BSC 0.030 BSC 0.012 0.014 0.016 Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. D 01/15/03 PACKAGING INFORMATION Plastic TSOP Package Code: T (Type II) ISSI Notes: 1. Controlling dimension: millimieters, unless otherwise specified. 2. BSC = Basic lead spacing between centers. 3. Dimensions D and E1 do not include mold flash protrusions and should be measured from the bottom of the package. 4. Formed leads shall be planar with respect to one another within 0.004 inches at the seating plane. ® N N/2+1 E1 E 1 D N/2 SEATING PLANE ZD A . e b L A1 α C Symbol Ref. Std. No. Leads A A1 b C D E1 E e L ZD α Millimeters Min Max Inches Min Max Plastic TSOP (T - Type II) Millimeters Inches Min Max Min Max 44 — 1.20 — 0.047 0.05 0.15 0.002 0.006 0.30 0.45 0.012 0.018 0.12 0.21 0.005 0.008 18.31 18.52 0.721 0.729 10.03 10.29 0.395 0.405 11.56 11.96 0.455 0.471 0.80 BSC 0.032 BSC 0.41 0.60 0.016 0.024 0.81 REF 0.032 REF 0° 5° 0° 5° Millimeters Min Max 50 — 1.20 0.05 0.15 0.30 0.45 0.12 0.21 20.82 21.08 10.03 10.29 11.56 11.96 0.80 BSC 0.40 0.60 0.88 REF 0° 5° Inches Min Max (N) 32 — 1.20 — 0.047 0.05 0.15 0.002 0.006 0.30 0.52 0.012 0.020 0.12 0.21 0.005 0.008 20.82 21.08 0.820 0.830 10.03 10.29 0.391 0.400 11.56 11.96 0.451 0.466 1.27 BSC 0.050 BSC 0.40 0.60 0.016 0.024 0.95 REF 0.037 REF 0° 5° 0° 5° — 0.047 0.002 0.006 0.012 0.018 0.005 0.008 0.820 0.830 0.395 0.405 0.455 0.471 0.031 BSC 0.016 0.024 0.035 REF 0° 5° Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. F 06/18/03