IS61WV51216ALL

IS61WV51216ALL IS61WV51216BLL IS64WV51216BLL 512K x 16 HIGH-SPEED ASYNCHRONOUS CMOS STATIC RAM WITH 3.3V SUPPLY FEATURES • High-speed access times: 8, 10, 20 ns • High-performance, low-power CMOS process • Multiple center power and ground pins for greater noise immunity • Easy memory expansion with CE and OE options • CE power-down • Fully static operation: no clock or refresh required • TTL compatible inputs and outputs • Single power supply VDD 1.65V to 2.2V (IS61WV51216ALL) speed = 20ns for VDD 1.65V to 2.2V VDD 2.4V to 3.6V (IS61/64WV51216BLL) speed = 10ns for VDD 2.4V to 3.6V speed = 8ns for VDD 3.3V + 5% • Packages available: – 48-ball miniBGA (9mm x 11mm) – 44-pin TSOP (Type II) • Industrial and Automotive Temperature Support • Lead-free available • Data control for upper and lower bytes OCTOBER 2009 DESCRIPTION The ISSI IS61WV51216ALL/BLL and IS64WV51216BLL are high-speed, 8M-bit static RAMs organized as 512K words by 16 bits. It is fabricated using ISSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields high-performance and low power consumption devices. When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs, CE and OE. The active LOW Write Enable (WE) controls both writing and reading of the memory. A data byte allows Upper Byte (UB) and Lower Byte (LB) access. The device is packaged in the JEDEC standard 44-pin TSOP Type II and 48-pin Mini BGA (9mm x 11mm). FUNCTIONAL BLOCK DIAGRAM A0-A18 DECODER 512K x 16 MEMORY ARRAY VDD GND I/O0-I/O7 Lower Byte I/O8-I/O15 Upper Byte I/O DATA CIRCUIT COLUMN I/O CE OE WE UB LB CONTROL CIRCUIT Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — www.issi.com Rev. F 10/01/09 1 IS61WV51216ALL IS61WV51216BLL IS64WV51216BLL 48-pin mini BGA (9mmx11mm) 1 2 3 4 5 6 A B C D E F G H LB I/O8 I/O9 GND VDD I/O14 I/O15 A18 OE UB I/O10 I/O11 I/O12 I/O13 NC A8 A0 A3 A5 A17 NC A14 A12 A9 A1 A4 A6 A7 A16 A15 A13 A10 A2 CE I/O1 I/O3 I/O4 I/O5 WE A11 NC I/O0 I/O2 VDD GND I/O6 I/O7 NC PIN DESCRIPTIONS A0-A18 I/O0-I/O15 CE OE WE LB UB NC VDD GND Address Inputs Data Inputs/Outputs Chip Enable Input Output Enable Input Write Enable Input Lower-byte Control (I/O0-I/O7) Upper-byte Control (I/O8-I/O15) No Connection Power Ground 2 Integrated Silicon Solution, Inc. — www.issi.com Rev. F 10/01/09 IS61WV51216ALL IS61WV51216BLL IS64WV51216BLL PIN CONFIGURATIONS 44-Pin TSOP (Type II) A0 A1 A2 A3 A4 CE I/O0 I/O1 I/O2 I/O3 VDD GND I/O4 I/O5 I/O6 I/O7 WE A5 A6 A7 A8 A9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A17 A16 A15 OE UB LB I/O15 I/O14 I/O13 I/O12 GND VDD I/O11 I/O10 I/O9 I/O8 A18 A14 A13 A12 A11 A10 PIN DESCRIPTIONS A0-A18 I/O0-I/O15 CE OE WE LB UB NC VDD GND Address Inputs Data Inputs/Outputs Chip Enable Input Output Enable Input Write Enable Input Lower-byte Control (I/O0-I/O7) Upper-byte Control (I/O8-I/O15) No Connection Power Ground Integrated Silicon Solution, Inc. — www.issi.com Rev. F 10/01/09 3 IS61WV51216ALL IS61WV51216BLL IS64WV51216BLL TRUTH TABLE WE X H X H H H L L L CE H L L L L L L L L OE X H X L L L X X X LB X X H L H L L H L UB X X H H L L H L L I/O PIN I/O0-I/O7 I/O8-I/O15 High-Z High-Z High-Z DOUT High-Z DOUT DIN High-Z DIN High-Z High-Z High-Z High-Z DOUT DOUT High-Z DIN DIN Mode Not Selected Output Disabled Read VDD Current ISB1, ISB2 ICC ICC Write ICC ABSOLUTE MAXIMUM RATINGS(1) Symbol VTERM VDD TSTG PT Parameter Terminal Voltage with Respect to GND VDD Relates to GND Storage Temperature Power Dissipation Value –0.5 to VDD + 0.5 –0.3 to 4.0 –65 to +150 1.0 Unit V V °C W Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. CAPACITANCE(1,2) Symbol CIN CI/O Parameter Input Capacitance Input/Output Capacitance Conditions VIN = 0V VOUT = 0V Max. 6 8 Unit pF pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25°C, f = 1 MHz, VDD = 3.3V. 4 Integrated Silicon Solution, Inc. — www.issi.com Rev. F 10/01/09 IS61WV51216ALL IS61WV51216BLL IS64WV51216BLL OPERATING RANGE (VDD) (IS61WV51216ALL) Range Ambient Temperature Commercial 0°C to +70°C Industrial –40°C to +85°C Automotive –40°C to +125°C VDD (20 nS) 1.65V-2.2V 1.65V-2.2V 1.65V-2.2V OPERATING RANGE (VDD) (IS61WV51216BLL)(1) Range Ambient Temperature Commercial 0°C to +70°C Industrial –40°C to +85°C VDD (8 nS) 3.3V + 5% 3.3V + 5% VDD (10 nS) 2.4V-3.6V 2.4V-3.6V Note: 1. When operated in the range of 2.4V-3.6V, the device meets 10ns. When operated in the range of 3.3V + 5%, the device meets 8ns. OPERATING RANGE (VDD) (IS64WV51216BLL) Range Automotive Ambient Temperature –40°C to +125°C VDD (10 nS) 2.4V-3.6V Integrated Silicon Solution, Inc. — www.issi.com Rev. F 10/01/09 5 IS61WV51216ALL IS61WV51216BLL IS64WV51216BLL DC ELECTRICAL CHARACTERISTICS (Over Operating Range) VDD = 3.3V + 5% Symbol VOH VOL VIH VIL ILI ILO Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage(1) Input Leakage Output Leakage GND ≤ VIN ≤ VDD GND ≤ VOUT ≤ VDD, Outputs Disabled Test Conditions VDD = Min., IOH = –4.0 mA VDD = Min., IOL = 8.0 mA Min. 2.4 — 2 –0.3 –1 –1 Max. — 0.4 VDD + 0.3 0.8 1 1 Unit V V V V µA µA Note: 1. VIL (min.) = –0.3V DC; VIL (min.) = –2.0V AC (pulse width < 10 ns). Not 100% tested. VIH (max.) = VDD + 0.3V DC; VIH (max.) = VDD + 2.0V AC (pulse width < 10 ns). Not 100% tested. DC ELECTRICAL CHARACTERISTICS (Over Operating Range) VDD = 2.4V-3.6V Symbol VOH VOL VIH VIL ILI ILO Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage(1) Input Leakage Output Leakage GND ≤ VIN ≤ VDD GND ≤ VOUT ≤ VDD, Outputs Disabled Test Conditions VDD = Min., IOH = –1.0 mA VDD = Min., IOL = 1.0 mA Min. 1.8 — 2.0 –0.3 –1 –1 Max. — 0.4 VDD + 0.3 0.8 1 1 Unit V V V V µA µA Note: 1. VIL (min.) = –0.3V DC; VIL (min.) = –2.0V AC (pulse width < 10 ns). Not 100% tested. VIH (max.) = VDD + 0.3V DC; VIH (max.) = VDD + 2.0V AC (pulse width < 10 ns). Not 100% tested. DC ELECTRICAL CHARACTERISTICS (Over Operating Range) VDD = 1.65V-2.2V Symbol VOH VOL VIH VIL(1) ILI ILO Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Output Leakage GND ≤ VIN ≤ VDD GND ≤ VOUT ≤ VDD, Outputs Disabled Test Conditions IOH = -0.1 mA IOL = 0.1 mA VDD 1.65-2.2V 1.65-2.2V 1.65-2.2V 1.65-2.2V Min. 1.4 — 1.4 –0.2 –1 –1 Max. — 0.2 VDD + 0.2 0.4 1 1 Unit V V V V µA µA Notes: 1. VIL (min.) = –0.3V DC; VIL (min.) = –2.0V AC (pulse width < 10 ns). Not 100% tested. VIH (max.) = VDD + 0.3V DC; VIH (max.) = VDD + 2.0V AC (pulse width < 10 ns). Not 100% tested. 6 Integrated Silicon Solution, Inc. — www.issi.com Rev. F 10/01/09 IS61WV51216ALL IS61WV51216BLL IS64WV51216BLL AC TEST CONDITIONS (HIGH SPEED) Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level (VRef) Output Load Unit (2.4V-3.6V) 0.4V to VDD-0.3V 1.5ns VDD/2 See Figures 1 and 2 Unit (3.3V + 5%) 0.4V to VDD-0.3V 1.5ns VDD/2 + 0.05 See Figures 1 and 2 Unit (1.65V-2.2V) 0.4V to VDD-0.2V 1.5ns VDD/2 See Figures 1 and 2 AC TEST LOADS 319 Ω ZO = 50Ω OUTPUT 50Ω 1.5V 30 pF Including jig and scope 3.3V OUTPUT 5 pF Including jig and scope 353 Ω Figure 1. Figure 2. Integrated Silicon Solution, Inc. — www.issi.com Rev. F 10/01/09 7 IS61WV51216ALL IS61WV51216BLL IS64WV51216BLL POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) -8 Symbol Parameter ICC VDD Dynamic Operating Supply Current Test Conditions VDD = Max., IOUT = 0 mA, f = fMAX Com. Ind. Auto. typ.(2) Com. Ind. Auto. Com. Ind. Auto. Com. Ind. Auto. typ.(2) Min. — — — — — — — — — — — — Max. 110 115 — 85 90 — 30 35 — 20 25 — -10 Min. Max. — — — 60 — — — — — — — — — 4 85 90 110 30 35 70 20 25 60 — — — — — — — — — 45 55 90 30 35 70 15 20 60 mA 90 95 140 -20 Min. Max. — — — 50 60 100 Unit mA ICC1 Operating Supply Current TTL Standby Current (TTL Inputs) CMOS Standby Current (CMOS Inputs) VDD = Max., IOUT = 0 mA, f = 0 VDD = Max., VIN = VIH or VIL CE ≥ VIH, f = 0 VDD = Max., CE ≥ VDD – 0.2V, VIN ≥ VDD – 0.2V, or VIN ≤ 0.2V, f = 0 ISB1 mA ISB2 mA Note: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. Typical values are measured at VDD = 3.0V, TA = 25oC and not 100% tested. 8 Integrated Silicon Solution, Inc. — www.issi.com Rev. F 10/01/09 IS61WV51216ALL IS61WV51216BLL IS64WV51216BLL READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) -8 Symbol Parameter Read Cycle Time Address Access Time Output Hold Time CE Access Time OE Access Time OE to High-Z Output OE to Low-Z Output CE to High-Z Output CE to Low-Z Output LB, UB Access Time LB, UB to High-Z Output LB, UB to Low-Z Output Power Up Time Power Down Time Min. 8 — 2.5 — — — 0 0 3 — 0 0 0 — Max. — 8 — 8 5.5 3 — 3 — 5.5 3 — — 8 -10 Min. Max. 10 — 2.5 — — — 0 0 3 — 0 0 0 — — 10 — 10 6.5 4 — 4 — 6.5 3 — — 10 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns tRC tAA tOHA tACE tDOE tHZOE(2) tLZOE(2) tHZCE(2 tLZCE(2) tBA tHZB(2) tLZB(2) tPU tPD Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to 3.0V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Integrated Silicon Solution, Inc. — www.issi.com Rev. F 10/01/09 9 IS61WV51216ALL IS61WV51216BLL IS64WV51216BLL READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter Read Cycle Time Address Access Time Output Hold Time CE Access Time OE Access Time OE to High-Z Output OE to Low-Z Output CE to High-Z Output CE to Low-Z Output LB, UB Access Time LB, UB to High-Z Output LB, UB to Low-Z Output (2) -20 ns Min. Max. 20 — 2.5 — — 0 0 0 3 — 0 0 — 20 — 20 8 8 — 8 — 8 8 — Unit ns ns ns ns ns ns ns ns ns ns ns ns tRC tAA tOHA tACE tDOE tHZOE(2) tLZOE tHZCE tLZCE tBA tHZB tLZB (2 (2) Notes: 1. Test conditions assume signal transition times of 1.5 ns or less, timing reference levels of 1.25V, input pulse levels of 0.4V to VDD-0.3V and output loading specified in Figure 1a. 2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3. Not 100% tested. 10 Integrated Silicon Solution, Inc. — www.issi.com Rev. F 10/01/09 IS61WV51216ALL IS61WV51216BLL IS64WV51216BLL AC WAVEFORMS READ CYCLE NO. 1(1,2) (Address Controlled) (CE = OE = VIL) t RC ADDRESS t AA t OHA DOUT PREVIOUS DATA VALID t OHA DATA VALID READ1.eps READ CYCLE NO. 2(1,3) (CE and OE Controlled) t RC ADDRESS t AA OE t OHA t DOE CE t HZOE t LZOE t ACE t LZCE t HZCE DATA VALID CE_RD2.eps DOUT HIGH-Z Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE = VIL. 3. Address is valid prior to or coincident with CE LOW transitions. Integrated Silicon Solution, Inc. — www.issi.com Rev. F 10/01/09 11 IS61WV51216ALL IS61WV51216BLL IS64WV51216BLL WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range) -8 Symbol Parameter Write Cycle Time CE to Write End Address Setup Time to Write End Address Hold from Write End Address Setup Time LB, UB Valid to End of Write WE Pulse Width WE Pulse Width (OE = LOW) Data Setup to Write End Data Hold from Write End (2) -10 Max. — — — — — — — — — — 3.5 — Min. 10 8 8 0 0 8 8 10 6 0 — 2 Max. — — — — — — — — — — 5 — Unit ns ns ns ns ns ns ns ns ns ns ns ns Min. 8 6.5 6.5 0 0 6.5 6.5 8.0 5 0 — 2 tWC tSCE tAW tHA tSA tPWB tPWE1 tPWE2 tSD tHD tHZWE tLZWE(2) WE LOW to High-Z Output WE HIGH to Low-Z Output Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to 3.0V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. Shaded area product in development 12 Integrated Silicon Solution, Inc. — www.issi.com Rev. F 10/01/09 IS61WV51216ALL IS61WV51216BLL IS64WV51216BLL WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range) Symbol Parameter Write Cycle Time CE to Write End Address Setup Time to Write End Address Hold from Write End Address Setup Time LB, UB Valid to End of Write WE Pulse Width (OE = HIGH) WE Pulse Width (OE = LOW) Data Setup to Write End Data Hold from Write End WE LOW to High-Z Output WE HIGH to Low-Z Output -20 ns Min. Max. 20 12 12 0 0 12 12 17 9 0 — 3 — — — — — — — — — — 9 — Unit ns ns ns ns ns ns ns ns ns ns ns ns tWC tSCE tAW tHA tSA tPWB tPWE1 tPWE2 tSD tHD tHZWE(3) tLZWE(3) Notes: 1. Test conditions for IS61WV51216ALL/BLL assume signal transition times of 1.5ns or less, timing reference levels of 1.25V, input pulse levels of 0.4V to VDD-0.3V and output loading specified in Figure 1a. 2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. Integrated Silicon Solution, Inc. — www.issi.com Rev. F 10/01/09 13 IS61WV51216ALL IS61WV51216BLL IS64WV51216BLL AC WAVEFORMS WRITE CYCLE NO. 1(1,2) (CE Controlled, OE = HIGH or LOW) t WC ADDRESS VALID ADDRESS t SA CE t SCE t HA WE t AW t PWE1 t PWE2 t HZWE t LZWE HIGH-Z DOUT DATA UNDEFINED t SD DIN t HD DATAIN VALID CE_WR1.eps 14 Integrated Silicon Solution, Inc. — www.issi.com Rev. F 10/01/09 IS61WV51216ALL IS61WV51216BLL IS64WV51216BLL AC WAVEFORMS WRITE CYCLE NO. 2 (WE Controlled. OE is HIGH During Write Cycle) (1,2) t WC ADDRESS VALID ADDRESS t HA OE CE LOW t AW t PWE1 WE t SA UB, LB t PBW t HZWE DOUT DATA UNDEFINED HIGH-Z t LZWE t SD DIN t HD DATAIN VALID UB_CEWR2.eps WRITE CYCLE NO. 3 (WE Controlled. OE is LOW During Write Cycle) (1) t WC ADDRESS OE CE VALID ADDRESS LOW t HA LOW t AW t PWE2 WE t SA UB, LB t PBW t HZWE DOUT DATA UNDEFINED HIGH-Z t LZWE t SD DIN t HD DATAIN VALID UB_CEWR3.eps Integrated Silicon Solution, Inc. — www.issi.com Rev. F 10/01/09 15 IS61WV51216ALL IS61WV51216BLL IS64WV51216BLL AC WAVEFORMS WRITE CYCLE NO. 4 (LB, UB Controlled, Back-to-Back Write) (1,3) t WC ADDRESS ADDRESS 1 t WC ADDRESS 2 OE t SA CE LOW WE t HA t SA t PBW t PBW WORD 2 t HA UB, LB WORD 1 t HZWE DOUT HIGH-Z t LZWE t HD DATAIN VALID DATA UNDEFINED t SD DIN t SD DATAIN VALID t HD UB_CEWR4.eps Notes: 1. The internal Write time is defined by the overlap of CE = LOW, UB and/or LB = LOW, and WE = LOW. All signals must be in valid states to initiate a Write, but any can be deasserted to terminate the Write. The tSA, t HA, tSD, and tHD timing is referenced to the rising or falling edge of the signal that terminates the Write. 2. Tested with OE HIGH for a minimum of 4 ns before WE = LOW to place the I/O in a HIGH-Z state. 3. WE may be held LOW across many address cycles and the LB, UB pins can be used to control the Write function. 16 Integrated Silicon Solution, Inc. — www.issi.com Rev. F 10/01/09 IS61WV51216ALL IS61WV51216BLL IS64WV51216BLL DATA RETENTION SWITCHING CHARACTERISTICS Symbol Parameter VDD for Data Retention Data Retention Current Data Retention Setup Time Recovery Time Test Condition See Data Retention Waveform VDD = 1.2V, CE ≥ VDD – 0.2V See Data Retention Waveform See Data Retention Waveform Ind. Auto. Min. 1.2 — — 0 Max. 3.6 20 50 — — Unit V mA ns ns VDR IDR tSDR tRDR tRC DATA RETENTION WAVEFORM (CE Controlled) tSDR VDD 1.65V Data Retention Mode tRDR 1.4V VDR CE ≥ VDD - 0.2V CE GND Integrated Silicon Solution, Inc. — www.issi.com Rev. F 10/01/09 17 IS61WV51216ALL IS61WV51216BLL IS64WV51216BLL ORDERING INFORMATION Industrial Range: -40°C to +85°C Voltage Range: 2.4V to 3.6V Speed (ns) 10 (8 ) 1 Order Part No. IS61WV51216BLL-10MI IS61WV51216BLL-10MLI IS61WV51216BLL-10TI IS61WV51216BLL-10TLI Package 48 mini BGA (9mm x 11mm) 48 mini BGA (9mm x 11mm), Lead-free TSOP (Type II) TSOP (Type II), Lead-free Note: 1. Speed = 8ns for VDD = 3.3V + 5%. Speed = 10ns for VDD = 2.4V - 3.6V Industrial Range: -40°C to +85°C Voltage Range: 1.65V to 2.2V Speed (ns) 20 Order Part No. IS61WV51216ALL-20MI IS61WV51216ALL-20TI Package 48 mini BGA (9mm x 11mm) TSOP (Type II) Automotive Range: -40°C to +125°C Voltage Range: 2.4V to 3.6V Speed (ns) 10 Order Part No. IS64WV51216BLL-10MA3 IS64WV51216BLL-10MLA3 IS64WV51216BLL-10CTA3 IS64WV51216BLL-10CTLA3 Package 48 mini BGA (9mm x 11mm) 48 mini BGA (9mm x 11mm), Lead-free TSOP (Type II), Copper Leadframe TSOP (Type II), Lead-free, Copper Leadframe 18 Integrated Silicon Solution, Inc. — www.issi.com Rev. F 10/01/09 IS61WV51216ALL IS61WV51216BLL IS64WV51216BLL 08/21/2008 Integrated Silicon Solution, Inc. — www.issi.com Rev. F 10/01/09 NOTE : 1. CONTROLLING DIMENSION : MM . 2. Reference document : JEDEC MO-207 19 20 IS61WV51216ALL IS61WV51216BLL IS64WV51216BLL NOTE : 1. CONTROLLING DIMENSION : MM 2. DIMENSION D AND E1 DO NOT INCLUDE MOLD PROTRUSION. 3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION/INTRUSION. Integrated Silicon Solution, Inc. — www.issi.com Package Outline 06/04/2008 Rev. F 10/01/09