IS61WV51216EEBLL-10TLI

IS61WV51216EEALL IS61/64WV51216EEBLL 512Kx16 HIGH SPEED AYNCHRONOUS CMOS STATIC RAM with ECC KEY FEATURES  High-speed access time: 8ns, 10ns, 20ns  Single power supply – 1.65V-2.2V VDD (IS61WV51216EEALL) – 2.4V-3.6V VDD (IS61/64WV51216EEBLL)  Error Detection and Correction with optional ERR1/ERR2 output pin: - ERR1 pin indicates 1-bit error detection and correction. - ERR2 pin indicates 2-bit error detection  Package Available: - 44-pin TSOP (Type II) - 48-pin TSOP (Type I) - 48-ball mini BGA (6mm x 8mm) - 54 pin TSOP (Type II)  Three state outputs  Industrial and Automotive temperature support  Lead-free available FUNCTIONAL BLOCK DIAGRAM A0 – A18 DECODER VDD VSS ERR1 ERR2 I/O0 – I/O7 I/O8 – I/O15 CS# or CS1#/CS2 OE# WE# UB# LB# Memory Memory Lower IO ECC Upper IO ECC Array Array Array Array 512Kx8 512Kx5 512Kx8 512Kx5 8 I/O DATA CIRCUIT 8 5 8 13 8 ECC ECC 13 5 AUGUST 2019 DESCRIPTION The ISSI IS61/64WV51216EEALL/BLL are high-speed, low power, 8M bit static RAMs organized as 512K words by 16 bits. It is fabricated using ISSI's high-performance CMOS technology and implemented ECC function to improve reliability. This highly reliable process coupled with innovative circuit design techniques including ECC (SEC-DED: Single Error Correcting-Double Error Detecting) yield high-performance and highly reliable devices. When CS# is HIGH (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs. The active LOW Write Enable (WE#) controls both writing and reading of the memory. A data byte allows Upper Byte (UB#) and Lower Byte (LB#) access. The devices are packaged in the JEDEC standard 44-pin TSOP (TYPE II), 48-pin mini BGA (6mm x 8mm), 48-pin TSOP (TYPE I), and 54-pin TSOP (TYPE II) COLUMN I/OColumn I/O CONTROL CIRCUIT Copyright © 2019 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc.- www.issi.com Rev. A1 08/07/2019 1 IS61WV51216EEALL IS61/64WV51216EEBLL PIN CONFIGURATIONS 48-Pin mini BGA(6mm x 8mm) 48-Pin mini BGA (6mm x 8mm), ERR1/2 1 2 3 4 5 6 LB# OE# A0 A1 A2 NC A B I/O8 UB# A3 A4 CS# I/O0 C I/O9 I/O10 A5 A6 I/O1 D VSS I/O11 A17 A7 E VDD I/O12 NC F I/O14 I/O13 G I/O15 H A18 A 1 2 3 4 5 6 LB# OE# A0 A1 A2 NC B I/O8 UB# A3 A4 CS# I/O0 I/O2 C I/O9 I/O10 A5 A6 I/O1 I/O2 I/O3 VDD D VSS I/O11 A17 A7 I/O3 VDD A16 I/O4 VSS E VDD I/O12 ERR1 A16 I/O4 VSS A14 A15 I/O5 I/O6 F I/O14 I/O13 A14 A15 I/O5 I/O6 NC A12 A13 WE# I/O7 G I/O15 ERR2 A12 A13 WE# I/O7 A8 A9 A10 A11 NC H A18 A8 A9 A10 A11 NC 44-Pin TSOP-II 48-Pin TSOP-I, ERR1/ERR2 A0 1 44 A17 A0 1 48 A17 A1 2 43 A16 A16 3 42 A15 2 3 47 A2 A1 A2 46 A3 4 41 OE# A3 4 45 A15 NC 5 6 44 43 CS# I/O0 7 42 UB# LB# 8 41 I/O15 9 40 I/O14 10 11 39 I/O3 I/O13 I/O12 VDD 12 VSS I/O4 13 14 36 VDD 35 I/O11 I/O5 15 34 I/O10 I/O6 16 33 I/O9 I/O7 17 32 I/O8 WE# 18 31 NC ERR2 19 30 A18 5 40 UB# 6 39 LB# I/O0 I/O1 7 38 I/O15 8 9 37 I/O14 I/O2 36 I/O13 I/O1 I/O2 I/O3 10 35 I/O12 VDD 11 34 VSS VSS 12 VDD I/O4 13 33 32 I/O11 I/O5 I/O6 14 31 I/O10 30 I/O9 I/O7 15 16 29 I/O8 WE# 17 28 A18 OE# A4 ERR1 A4 CS# 38 37 VSS A5 18 27 A14 A5 20 29 A14 A6 19 26 A13 21 28 A13 A7 20 25 A12 A6 A7 22 A12 A8 21 24 A11 A8 23 27 26 A9 22 23 A10 A9 24 25 A10 Integrated Silicon Solution, Inc.- www.issi.com Rev. A1 08/07/2019 A11 2 IS61WV51216EEALL IS61/64WV51216EEBLL 54-Pin TSOP-II 54-Pin TSOP-II, ERR1/ERR2 I/O12 1 54 I/O11 I/O12 1 54 I/O11 VDD 53 VSS VDD VSS 52 I/O13 52 I/O14 4 51 I/O10 I/O9 2 3 53 I/O13 2 3 I/O14 4 51 I/O10 I/O9 VSS 5 50 VDD VSS 5 50 VDD I/O15 6 49 I/O8 I/O15 6 49 I/O8 A4 7 48 A5 A4 7 48 A5 A3 8 47 A6 A3 8 47 A6 A2 9 46 A7 A2 9 46 A7 A1 45 A8 A1 45 A8 44 43 A9 A0 10 11 NC UB# 12 44 43 ERR1 OE# A0 10 11 UB# 12 CS1# 13 14 42 OE# CS1# VSS VDD 13 14 42 41 41 VSS WE# 15 40 NC WE# 15 40 ERR2 CS2 16 39 LB# CS2 16 39 LB# NC 17 38 A10 NC 17 38 A10 A18 18 37 A11 A18 18 37 A11 A17 19 36 A12 A17 19 36 A12 A16 20 35 A13 A16 20 35 A13 A15 I/O0 21 34 A14 34 A14 I/O7 22 23 VSS VDD 23 33 32 I/O7 VDD 33 32 A15 I/O0 21 22 I/O1 24 31 I/O6 I/O1 24 31 I/O6 I/O2 25 I/O5 I/O2 25 VSS 26 30 29 I/O5 VDD I/O4 I/O3 27 28 I/O4 VDD VSS 26 30 29 I/O3 27 28 A9 VSS VDD PIN DESCRIPTIONS A0-A18 I/O0-I/O15 CS# or CS1#/CS2 OE# WE# LB# UB# ERR1 Address Inputs Data Inputs/Outputs Chip Enable Input ERR2 Output Enable Input Write Enable Input Lower-byte Control (I/O0-I/O7) Upper-byte Control (I/O8-I/O15) 1-bit Error Detection and Correction Signal 2-bit ERR Detection Signal NC VDD VSS No Connection Power Ground Integrated Silicon Solution, Inc.- www.issi.com Rev. A1 08/07/2019 3 IS61WV51216EEALL IS61/64WV51216EEBLL FUNCTION DESCRIPTION SRAM is one of random access memories. Each byte or word has an address and can be accessed randomly. SRAM has three different modes supported. Each function is described below with Truth Table. STANDBY MODE Device enters standby mode when deselected (CS# HIGH). The input and output pins (I/O0-15) are placed in a high impedance state. CMOS input in this mode will maximize saving power. WRITE MODE Write operation issues with Chip selected (CS#) and Write Enable (WE#) input LOW. The input and output pins (I/O015) are in data input mode. Output buffers are closed during this time even if OE# is LOW. UB# and LB# enables a byte write feature. By enabling LB# LOW, data from I/O pins (I/O0 through I/O7) are written into the location specified on the address pins. And with UB# being LOW, data from I/O pins (I/O8 through I/O15) are written into the location. READ MODE Read operation issues with Chip selected (CS# LOW) and Write Enable (WE#) input HIGH. When OE# is LOW, output buffer turns on to make data output. Any input to I/O pins during READ mode is not permitted. UB# and LB# enables a byte read feature. By enabling LB# LOW, data from memory appears on I/O0-7. And with UB# being LOW, data from memory appears on I/O8-15. In the READ mode, output buffers can be turned off by pulling OE# HIGH. In this mode, internal device operates as READ but I/Os are in a high impedance state. Since device is in READ mode, active current is used. ERROR DETECTION AND ERROR CORRECTION  Independent ECC per each byte - detect and correct 1-bit error per byte or detect multi-bit error per byte  Optional ERR1 output signal indicates 1-bit error detection and correction  Optional ERR2 output signal indicates multi-bit error detection.  Controller can use either ERR1 or ERR2 to monitor ECC event. Unused pins (ERR1 or ERR2) can be left floating.  Better reliability than parity code schemes which can only detect an error but not correct an error  Backward Compatible: Drop in replacement to current in industry standard devices (without ECC) ERR1, ERR2 OUTPUT SIGNAL BEHAVIOR DQ pin Status ERR1 ERR2 0 0 Valid Q No Error 1 0 Valid Q 1-Bit Error only 0 1 1 1 High-Z High-Z Multi-Bit Error only 1-bit & Multi-bit In-Valid Q error In-Valid Q Valid D Non-Read Integrated Silicon Solution, Inc.- www.issi.com Rev. A1 08/07/2019 Remark 1-bit error per byte detected and corrected No 1-bit error. Multi-bit error per byte detected (out of 2 bytes) 1-bit error detected and corrected at one byte, and multi-bit error detected at another byte. Write operation or Output Disabled 4 IS61WV51216EEALL IS61/64WV51216EEBLL TRUTH TABLE Mode CS# WE# OE# LB# UB# I/O0-I/O7 I/O8-I/O15 VDD Current Not Selected H X X X X High-Z High-Z ISB1, ISB2 L H H L X High-Z High-Z L X X H H High-Z High-Z L H L L H DOUT High-Z L H L H L High-Z DOUT L H L L L DOUT DOUT L L X L H DIN High-Z L L X H L High-Z DIN L L X L L DIN DIN Output Disabled Read Write ICC,ICC1 ICC,ICC1 ICC,ICC1 Note: 1. CS# = H means CS1#=HIGH, and CS2= LOW in Dual Chip Select Device. POWER UP INITIALIZATION The device includes on-chip voltage sensor used to launch POWER-UP initialization process. When VDD reaches stable level, the device requires 150us of tPU (Power-Up Time) to complete its self-initialization process. When initialization is complete, the device is ready for normal operation. tPU 150 us Stable VDD VDD Device Initialization Device for Normal Operation 0V Integrated Silicon Solution, Inc.- www.issi.com Rev. A1 08/07/2019 5 IS61WV51216EEALL IS61/64WV51216EEBLL ABSOLUTE MAXIMUM RATINGS AND OPERATING RANGE ABSOLUTE MAXIMUM RATINGS(1) Symbol Vt er m Parameter Terminal Voltage with Respect to VSS Value –0.5 to VDD + 0.5V Unit V VDD V DD Related to VSS –0.3 to 4.0 V tStg Storage Temperature –65 to +150 PT Power Dissipation 1.0 C W Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. . PIN CAPACITANCE (1) Parameter Symbol Input capacitance DQ capacitance (IO0–IO15) CIN CI/O Test Condition TA = 25°C, f = 1 MHz, VDD = VDD(typ) Max Units 6 8 pF pF Note: 1. These parameters are guaranteed by design and tested by a sample basis only. OPERATING RANGE(1) Range Industrial Automotive (A3) Note: 1. Ambient Temperature -40C to +85C -40C to +125C IS61WV51216EEALL VDD (20ns) 1.65V – 2.2V – IS61WV51216EEBLL VDD (8, 10ns) 2.4V – 3.6V – IS64WV51216EEBLL VDD (10ns) – 2.4V – 3.6V Full device AC operation assumes a 100 µs ramp time from 0 to VDD(min) and 200 µs wait time after VDD stabilization. THERMAL CHARACTERISTICS (1) Parameter Thermal resistance from junction to ambient (airflow = 1m/s) Thermal resistance from junction to pins Thermal resistance from junction to case Symbol RθJA RθJB RθJC Rating TBD TBD TBD Units °C/W °C/W °C/W Note: 1. These parameters are guaranteed by design and tested by a sample basis only. Integrated Silicon Solution, Inc.- www.issi.com Rev. A1 08/07/2019 6 IS61WV51216EEALL IS61/64WV51216EEBLL AC TEST CONDITIONS (OVER THE OPERATING RANGE) Parameter Input Pulse Level Unit (1.65V~2.2V) 0V to VDD Unit (2.4V~3.6V) 0V to VDD 1.5 ns ½ VDD 13500 10800 1.8V 1.5 ns ½ VDD 319 353 3.3V Input Rise and Fall Time Output Timing Reference Level R1 (ohm) R2 (ohm) VTM (V) Output Load Conditions Refer to Figure 1 and 2 AC TEST LOADS FIGURE 1 FIGURE 2 R1 VTM TM V Zo = 50 ohm Output 50 ohm VDD/2 30 pF, Including jig and scope Integrated Silicon Solution, Inc.- www.issi.com Rev. A1 08/07/2019 OUTPUT 5pF, Including jig and scope R2R2 7 IS61WV51216EEALL IS61/64WV51216EEBLL DC ELECTRICAL CHARACTERISTICS DC ELECTRICAL CHARACTERISTICS (OVER THE OPERATING RANGE) VDD = 1.65V – 2.2V Symbol Parameter VOH Output HIGH Voltage VOL Output LOW Voltage (1) VIH Input HIGH Voltage (1) VIL Input LOW Voltage ILI Input Leakage ILO Output Leakage Test Conditions I OH = -0.1 mA IOL = 0.1 mA GND < VIN < VDD GND < VIN < VDD, Output Disabled Min. 1.4 — 1.4 –0.2 –1 –1 Max. — 0.2 VDD + 0.2 0.4 1 1 Unit V V V V µA µA Notes: 1. VILL(min) = -1.0V AC (pulse width < 10ns). Not 100% tested. 2. VIHH (max) = VDD + 1.0V AC (pulse width < 10ns). Not 100% tested. DC ELECTRICAL CHARACTERISTICS (OVER THE OPERATING RANGE) VDD = 2.4V – 3.6V Symbol Parameter VOH Output HIGH Voltage VOL Output LOW Voltage (1) VIH Input HIGH Voltage VIL(1) ILI ILO Input LOW Voltage 2.4V 2.7V 2.4V 2.7V 2.4V 2.7V 2.4V 2.7V ~ ~ ~ ~ ~ ~ ~ ~ 2.7V 3.6V 2.7V 3.6V 2.7V 3.6V 2.7V 3.6V Input Leakage Output Leakage Test Conditions V DD = Min., I OH = -1.0 mA V DD = Min., I OH = -4.0 mA V DD = Min., IOL = 2.0 mA V DD = Min., I OL = 8.0 mA VSS < VIN < VDD VSS < VIN < VDD, Output Disabled Min. 2.0 2.2 — — 2.0 2.0 –0.3 –0.3 –2 –2 Max. — 0.4 0.4 VDD + 0.3 0.6 0.8 2 2 Unit V V V V µA µA Note: 1. VIL(min) = -0.3V DC ; VIL(min) = -2.0V AC (pulse width 2.0ns). Not 100% tested. VIH (max) = VDD + 0.3V DC ; VIH(max) = VDD + 2.0V AC (pulse width 2.0ns). Not 100% tested.. Integrated Silicon Solution, Inc.- www.issi.com Rev. A1 08/07/2019 8 IS61WV51216EEALL IS61/64WV51216EEBLL POWER SUPPLY CHARACTERISTICS-II FOR POWER (OVER THE OPERATING RANGE) Symbol Parameter ICC VDD Dynamic Operating Supply Current ICC1 Operating Supply Current ISB1 TTL Standby Current (TTL Inputs) ISB2 CMOS Standby Current (CMOS Inputs) Test Conditions VDD = MAX, IOU T = 0 mA, f = fMAX VDD = MAX, IOUT = 0 mA, f = 0 VDD = MAX, VIN = VIH or VIL CS# ≥ VIH , f = 0 VDD = MAX, CS# ≥ VDD - 0.2V VIN ≥ VDD - 0.2V , or VIN ≤ 0.2V , f =0 Notes: 1. 2. Grade Com. Ind. Auto. Com. Ind. Auto. Com. Ind. Auto. Com. Ind. Auto. -8 Max. 90 100 80 90 40 50 30 -10 Max. 85 95 135 80 90 110 40 50 60 30 -20 Max 80 90 80 90 40 50 30 40 40 40 - 50 - Typ. (2) Unit mA mA mA mA 10 At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input line change. Typical values are measured at VDD = 3.0V/1.8V, TA = 25 °C and not 100% tested. Integrated Silicon Solution, Inc.- www.issi.com Rev. A1 08/07/2019 9 IS61WV51216EEALL IS61/64WV51216EEBLL AC CHARACTERISTICS (OVER OPERATING RANGE) READ CYCLE AC CHARACTERISTICS Parameter Symbol Read Cycle Time Address Access Time Output Hold Time CS# Access Time OE# Access Time tRC tAA tOHA tACE tDOE OE# to High-Z Output OE# to Low-Z Output CS# to High-Z Output CS# to Low-Z Output UB#, LB# Access Time UB#, LB# to High-Z Output UB#, LB# to Low-Z Output Notes: 1. 2. -8(1) -10(1) -20(1) unit notes Min Max Min Max Min Max 8 2.5 - 8 8 5.5 10 2.5 - 10 10 6 20 2.5 - 20 20 8 ns ns ns ns ns tHZOE tLZOE tHZCE tLZCE tBA tHZB 0 0 0 3 0 4 4 5.5 4 0 0 0 3 0 5 5 6 5 0 0 0 3 0 8 8 8 8 ns ns ns ns ns ns 2 2 2 2 tLZB 0 - 0 - 0 - ns 2 2 Test conditions assume signal transition times of 1.5 ns or less, timing reference levels of V DD/2, input pulse levels of 0V to VDD and output loading specified in Figure 1. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. AC WAVEFORMS READ CYCLE NO. 1(1,2) (ADDRESS CONTROLLED, CS# = OE# = UB# = LB# = LOW, WE# = HIGH) tRC Address tAA tOHA DQ 0-15 tOHA PREVIOUS DATA VALID LOW-Z DATA VALID ERR1 PREVIOUS ERROR VALID LOW-Z ERROR1 VALID ERR2 PREVIOUS ERROR VALID LOW-Z ERROR2 VALID Notes: 1. The device is continuously selected. 2. ERR1, ERR2 signals act like a Read Data Q during Read Operation. Integrated Silicon Solution, Inc.- www.issi.com Rev. A1 08/07/2019 10 IS61WV51216EEALL IS61/64WV51216EEBLL READ CYCLE NO. 2(1) (OE# CONTROLLED, WE# = HIGH) tRC ADDRESS tAA tOHA tDOE OE# tHZOE tLZOE CS# tACS tHZCS tLZCS UB#,LB# tHZB tBA tLZB DOUT HIGH-Z LOW-Z DATA VALID Note: 1. Address is valid prior to or coincident with CS# LOW transition. Integrated Silicon Solution, Inc.- www.issi.com Rev. A1 08/07/2019 11 IS61WV51216EEALL IS61/64WV51216EEBLL WRITE CYCLE AC CHARACTERISTICS Parameter Symbol -8(1) Min Max Write Cycle Time tWC tSCS tAW tPWB tHA tSA 8 6.5 6.5 6.5 0 0 tPWE1 tPWE2 tSD tHD tHZWE tLZWE 6.5 8 5 0 2 CS# to Write End Address Setup Time to Write End UB#,LB# to Write End Address Hold from Write End Address Setup Time WE# Pulse Width WE# Pulse Width (OE# = LOW) Data Setup to Write End Data Hold from Write End WE# LOW to High-Z Output WE# HIGH to Low-Z Output Notes: 1 2 -10(1) -20(1) unit Min Max Min Max - 10 8 8 8 0 0 - 20 12 12 12 0 0 - ns ns ns ns ns ns 3.5 - 8 10 6 0 2 4 - 12 17 9 0 3 9 - ns ns ns ns ns ns notes 2 The internal write time is defined by the overlap of CS# = LOW, UB# or LB# = LOW, and WE# = LOW. All conditions must be in valid states to initiate a Write, but any condition can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. tPWE > tHZWE + tSD when OE# is LOW. AC WAVEFORMS WRITE CYCLE NO. 1 (CS# CONTROLLED, OE# = HIGH OR LOW) tWC ADDRESS tSCS tSA tHA CS# tAW tPWE WE# tPWB UB#,LB# tHZWE DOUT DATA UNDEFINED (1) HIGH-Z tSD DIN Note: 1. DATA UNDEFINED (2) tLZWE tHD DATA IN VALID tHZWE is based on the assumption when tSA=0nS after READ operation. Actual DOUT for tHZWE may not appear if OE# goes high before Write Cycle. Integrated Silicon Solution, Inc.- www.issi.com Rev. A1 08/07/2019 12 IS61WV51216EEALL IS61/64WV51216EEBLL WRITE CYCLE NO. 2(1,2) (WE# CONTROLLED: OE# IS HIGH DURING WRITE CYCLE) tWC ADDRESS tSCS tHA CS# tAW WE# tPWE tSA tPWB UB#,LB# OE# tHZOE DOUT DATA UNDEFINED DIN DATA UNDEFINED HIGH-Z (1) tSD (2) tHD DATA IN VALID Notes: 1. tHZOE is the time DOUT goes to High-Z after OE# goes high. 2. During this period the I/Os are in output state. Do not apply input signals. WRITE CYCLE NO. 3(1) (WE# CONTROLLED: OE# IS LOW DURING WRITE CYCLE) tWC ADDRESS OE# = LOW CS#=LOW tHA tAW tPWE2 WE# tSA UB#,LB# tPWB tHZWE DOUT tLZWE HIGHZ DATA UNDEFINED tSD DIN tHD DATA IN VALID Note: 3. If OE# is low during write cycle, tHZWE must be met in the application. Do not apply input signal during this period. Data output from the previous READ operation will drive IO BUS. Integrated Silicon Solution, Inc.- www.issi.com Rev. A1 08/07/2019 13 IS61WV51216EEALL IS61/64WV51216EEBLL WRITE CYCLE NO. 4(1, 2, 3) (UB# & LB# Controlled, CS# = OE# = LOW) tWC tWC ADDRESS ADDRESS 1 ADDRESS 2 CS#=LOW OE#=LOW tSA tHA tSA tHA WE# tPWB UB#, LB# tPWB WORD 1 WORD 2 tHZWE DOUT tLZWE HIGH-Z DATA UNDEFINED tHD tSD DIN Notes: 1 2 3 DATA IN VALID DATA IN VALID If OE# is low during write cycle, tHZWE must be met in the application. Do not apply input signal during this period. Data output from the previous READ operation will drive IO BUS. Due to the restriction of note1, OE# is recommended to be HIGH during write period. WE# stays LOW in this example. If WE# toggles, tPWE and tHZWE must be considered. Integrated Silicon Solution, Inc.- www.issi.com Rev. A1 08/07/2019 14 IS61WV51216EEALL IS61/64WV51216EEBLL DATA RETENTION CHARACTERISTICS Symbol Parameter VDR VDD for Data Retention Data Retention Current IDR Test Condition OPTION Min. VDD = 2.4V to 3.6V 2.0 Typ.(2) Max. Unit 3.6 See Data Retention Waveform V VDD = 1.65V to 2.2V 1.2 Com. - 10 30 Ind. - - 40 Auto - - 50 VDD= VDR(min), CS# ≥ VDD – 0.2V 3.6 mA tSDR Data Retention Setup Time See Data Retention Waveform 0 - - ns tRDR Recovery Time See Data Retention Waveform tRC - - ns Note: 1. 2. 3. If CS# > VDD–0.2V, all other inputs including UB# and LB# must meet this condition. CS#=H means CS1#=HIGH, and CS2=LOW in Dual Chip Select Device Typical values are measured at VDD = VDR (Min), TA = 25 °C and not 100% tested. DATA RETENTION WAVEFORM (CS# CONTROLLED) tSDR Data Retention Mode tRDR VDD VDR CS# CS# > VDD – 0.2V GND Integrated Silicon Solution, Inc.- www.issi.com Rev. A1 08/07/2019 15 IS61WV51216EEALL IS61/64WV51216EEBLL ORDERING INFORMATION Industrial Range: -40°C to +85°C, Voltage Range: 1.65V to 2.2V Speed (ns) Order Part No. Package 20 IS61WV51216EEALL-20BLI mini BGA (6mm x 8mm), Lead-free 20 IS61WV51216EEALL-20B2LI mini BGA (6mm x 8mm), ERR1/2 Pins, Lead-free 20 IS61WV51216EEALL-20TLI 44 TSOP (Type II), Lead-free 20 IS61WV51216EEALL-20T2LI 48 TSOP (Type I), ERR1/2 Pins , Lead-free Industrial Range: -40°C to +85°C, Voltage Range: 2.4V to 3.6V Speed (ns) Order Part No. Package 8 IS61WV51216EEBLL-8BI mini BGA (6mm x 8mm) 8 IS61WV51216EEBLL-8BLI mini BGA (6mm x 8mm), Lead-free 8 IS61WV51216EEBLL-8B2I mini BGA (6mm x 8mm), ERR1/2 Pins 8 IS61WV51216EEBLL-8B2LI mini BGA (6mm x 8mm), ERR1/2 Pins, Lead-free 8 IS61WV51216EEBLL-8TLI 44 TSOP (Type II), Lead-free 8 IS61WV51216EEBLL-8T2LI 48 TSOP (Type I), ERR1/2 Pins, Lead-free 8 IS61WV51216EEBLL-8T3LI 54 TSOP (Type II), Lead-free 8 IS61WV51216EEBLL-8T4LI 54 TSOP (Type II), ERR1/2 Pins, Lead-free 10 IS61WV51216EEBLL-10BI mini BGA (6mm x 8mm) 10 IS61WV51216EEBLL-10BLI mini BGA (6mm x 8mm), Lead-free 10 IS61WV51216EEBLL-10B2I mini BGA (6mm x 8mm), ERR1/2 Pins 10 IS61WV51216EEBLL-10B2LI mini BGA (6mm x 8mm), ERR1/2 Pins, Lead-free 10 IS61WV51216EEBLL-10TLI 44 TSOP (Type II), Lead-free 10 IS61WV51216EEBLL-10T2LI 48 TSOP (Type I), ERR1/2 Pins, Lead-free 10 IS61WV51216EEBLL-10T3LI 54 TSOP (Type II), Lead-free 10 IS61WV51216EEBLL-10T4LI 54 TSOP (Type II), ERR1/2 Pins, Lead-free Automotive Range (A3): –40°C to +125°C, Voltage Range: 2.4V to 3.6V Speed (ns) 10 10 10 10 10 10 10 10 Order Part No. IS64WV51216EEBLL-10BA3 IS64WV51216EEBLL-10BLA3 IS64WV51216EEBLL-10B2A3 IS64WV51216EEBLL-10B2LA3 IS64WV51216EEBLL-10CTLA3 IS64WV51216EEBLL-10CT2LA3 IS64WV51216EEBLL-10CT3LA3 IS64WV51216EEBLL-10CT4LA3 Integrated Silicon Solution, Inc.- www.issi.com Rev. A1 08/07/2019 Package mini BGA (6mm x 8mm) mini BGA (6mm x 8mm), Lead-free mini BGA (6mm x 8mm), ERR1/ERR2 Pins mini BGA (6mm x 8mm), ERR1/ERR2 Pins, Lead-free 44 TSOP (Type II), Copper Leadframe, Lead-free 48 TSOP (Type I), Copper Leadframe, ERR1/2 Pins , Lead-free 54 TSOP (Type II), Copper Leadframe, Lead-free 54 TSOP (Type II), Copper Leadframe, ERR1/2 Pins , Lead-free 16 IS61WV51216EEALL IS61/64WV51216EEBLL PACKAGE INFORMATION Integrated Silicon Solution, Inc.- www.issi.com Rev. A1 08/07/2019 17 IS61WV51216EEALL IS61/64WV51216EEBLL Integrated Silicon Solution, Inc.- www.issi.com Rev. A1 08/07/2019 18 IS61WV51216EEALL IS61/64WV51216EEBLL Integrated Silicon Solution, Inc.- www.issi.com Rev. A1 08/07/2019 19 IS61WV51216EEALL IS61/64WV51216EEBLL Integrated Silicon Solution, Inc.- www.issi.com Rev. A1 08/07/2019 20