IS61WV51232BLL-10BLI 数据手册
IS61WV51232ALL/ALS
IS61WV51232BLL/BLS
IS64WV51232BLL/BLS
512K x 32 HIGH-SPEED ASYNCHRONOUS
CMOS STATIC RAM WITH 3.3V SUPPLY
FEATURES
JUNE 2016
DESCRIPTION
The ISSI IS61WV51232Axx/Bxx and IS64WV51232Bxx are
• High-speed access times:
8, 10, 20 ns
• High-performance, low-power CMOS process
• Multiple center power and ground pins for greater
noise immunity
• Easy memory expansion with CE and OE options
• CE power-down
• Fully static operation: no clock or refresh
required
• TTL compatible inputs and outputs
• Single power supply
Vdd 1.65V to 2.2V (IS61WV51232Axx)
speed = 20ns for Vdd 1.65V to 2.2V
Vdd 2.4V to 3.6V (IS61/64WV51232Bxx)
speed = 10ns for Vdd 2.4V to 3.6V
speed = 8ns for Vdd 3.3V + 5%
• Packages available:
– 90-ball miniBGA (8mm x 13mm)
• Industrial and Automotive Temperature Support
• Lead-free available
high-speed, 16M-bit static RAMs organized as 512K words
by 32 bits. It is fabricated using ISSI's high-performance
CMOS technology. This highly reliable process coupled
with innovative circuit design techniques, yields highperformance and low power consumption devices.
When CE is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be reduced down with CMOS input levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs, CE and OE. The active LOW
Write Enable (WE) controls both writing and reading of
the memory.
The device is packaged in the JEDEC standard 90-ball
BGA (8mm x 13mm).
FUNCTIONAL BLOCK DIAGRAM
A0-A18
DECODER
512K x 32
MEMORY ARRAY
I/O
DATA
CIRCUIT
COLUMN I/O
VDD
VSS
DQa-d
CE
OE
WE
CONTROL
CIRCUIT
BWa-d
CE2
Copyright © 2016 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest
version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications
unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. — www.issi.com 1
Rev. A
06/01/2016
IS61WV51232ALL/ALS
IS61WV51232BLL/BLS
IS64WV51232BLL/BLS
PIN CONFIGURATION
package code: B 90 bALL fbga (Top View) (8.00 mm x 13.00 mm Body, 0.8 mm Ball Pitch)
1 2 3 4 5 6 7 8 9
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
DQ1 DQ0 VSS
VDD DQ31 DQ30
DQ2 VDD VSS
VDD
VSS DQ3 DQ4
DQ27 DQ28 VDD
VSS DQ6 DQ5
DQ26 DQ25 VDD
VSS DQ29
VDD DQ7
NC
NC
DQ24 VSS
VSS BWa
A3
A4
BWd VDD
A0
A1
A2
A10
A5
A6
A15
A14
A13
A8
A7
A11
CE2
A17
A16
A9
A12
CE
BWb
NC
A18
OE
WE
BWc
VDD DQ8 VSS
VDD DQ23 VSS
VSS DQ9 DQ10
DQ21 DQ22 VDD
VSS DQ12 DQ11
DQ20 DQ19 VDD
DQ13 VDD VSS
VDD
VSS DQ18
DQ14 DQ15 VSS
VDD DQ16 DQ17
PIN DESCRIPTIONS
A0-A18 Address Inputs
DQx
Data I/O
CE, CE2 Chip Enable Input
OE
Output Enable Input
WE
Write Enable Input
BWx (x=a-d)
Byte Write Control
Vdd Power
Vss Ground
NC
2
No Connection
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
06/01/2016
IS61WV51232ALL/ALS
IS61WV51232BLL/BLS
IS64WV51232BLL/BLS
TRUTH TABLE
CE CE2 OE WE BWa BWb BWc BWd DQ0-7 DQ8-15 DQ16-23 DQ24-31 Mode Power
H
X
X
X
X
X
X
X
High-Z High-Z
High-Z
High-Z Power Down (Isb)
X
L
X
X
X
X
X
X
High-Z High-Z
High-Z
High-Z Power Down (Isb)
L
H
L
H
L
L
L
L Data Out Data Out Data Out Data Out Read All Bits (Icc)
L
H
L
H
L
H
H
H Data Out High-Z
High-Z
High-Z Read Byte a (Icc)
Bits Only
L
H
L
H
H
L
H
H
High-Z Data Out High-Z
High-Z Read Byte b (Icc)
Bits Only
L
H
L
H
H
H
L
H
High-Z High-Z Data Out High-Z Read Byte c (Icc)
Bits Only
L
H
L
H
H
H
H
L
High-Z High-Z
High-Z Data Out Read Byte d (Icc)
Bits Only
L
H
X
L
L
L
L
L
Data In Data In Data In Data In Write All Bits (Icc)
L
H
X
L
L
H
H
H
Data In High-Z
High-Z
High-Z Write Byte a (Icc)
Bits Only
L
H
X
L
H
L
H
H
High-Z Data In High-Z
High-Z Write Byte b (Icc)
Bits Only
L
H
X
L
H
H
L
H
High-Z High-Z Data In High-Z
Write Byte c (Icc)
Bits Only
L
H
X
L
H
H
H
L
High-Z High-Z
High-Z Data In Write Byte d (Icc)
Bits Only
L
H
H
H
X
X
X
X
High-Z High-Z
High-Z
High-Z
Selected,
(Icc)
Outputs
Disabled
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter
Vterm
Terminal Voltage with Respect to GND
Vdd
Vdd Relates to GND
Tstg
Storage Temperature
Pt
Power Dissipation
Value
–0.5 to Vdd + 0.5
–0.3 to 4.0
–65 to +150
1.0
Unit
V
V
°C
W
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
CAPACITANCE(1,2)
Symbol
Cin
CI/O
Parameter
Input Capacitance
Input/Output Capacitance
Conditions
Vin = 0V
Vout = 0V
Max.
6
8
Unit
pF
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: Ta = 25°C, f = 1 MHz, Vdd = 3.3V.
Integrated Silicon Solution, Inc. — www.issi.com 3
Rev. A
06/01/2016
IS61WV51232ALL/ALS
IS61WV51232BLL/BLS
IS64WV51232BLL/BLS
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Vdd = 3.3V + 5%
Symbol
Voh
Vol
Vih
Vil
Ili
Ilo
Parameter
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage(1)
Input Leakage
Output Leakage
Test Conditions
Vdd = Min., Ioh = –4.0 mA
Vdd = Min., Iol = 8.0 mA
GND ≤ Vin ≤ Vdd
GND ≤ Vout ≤ Vdd, Outputs Disabled
Min.
Max.
Unit
2.4
—
V
—
0.4
V
2
Vdd + 0.3
V
–0.3 0.8 V
–1 1 µA
–1
1
µA
Note:
1. Vil (min.) = –0.3V DC; Vil (min.) = –2.0V AC (pulse width 2.0 ns). Not 100% tested.
Vih (max.) = Vdd + 0.3V DC; Vih (max.) = Vdd + 2.0V AC (pulse width 2.0 ns). Not 100% tested.
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Vdd = 2.4V-3.6V
Symbol
Voh
Vol
Vih
Vil
Ili
Ilo
Parameter
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage(1)
Input Leakage
Output Leakage
Test Conditions
Vdd = Min., Ioh = –1.0 mA
Vdd = Min., Iol = 1.0 mA
GND ≤ Vin ≤ Vdd
GND ≤ Vout ≤ Vdd, Outputs Disabled
Min.
Max.
Unit
1.8
—
V
—
0.4
V
2.0
Vdd + 0.3
V
–0.3 0.8 V
–1 1 µA
–1
1
µA
Note:
1. Vil (min.) = –0.3V DC; Vil (min.) = –2.0V AC (pulse width 2.0 ns). Not 100% tested.
Vih (max.) = Vdd + 0.3V DC; Vih (max.) = Vdd + 2.0V AC (pulse width 2.0 ns). Not 100% tested.
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Vdd = 1.65V-2.2V
Symbol
Voh
Vol
Vih
Vil(1)
Ili
Ilo
Parameter
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Leakage
Output Leakage
Test Conditions
Vdd Min. Max. Unit
Ioh = -0.1 mA
1.65-2.2V
1.4
—
V
Iol = 0.1 mA
1.65-2.2V
—
0.2
V
1.65-2.2V
1.4
Vdd + 0.2
V
1.65-2.2V –0.2 0.4 V
GND ≤ Vin ≤ Vdd
–1 1 µA
GND ≤ Vout ≤ Vdd, Outputs Disabled
–1
1
µA
Notes:
1. Vil (min.) = –0.3V DC; Vil (min.) = –2.0V AC (pulse width -2.0ns). Not 100% tested.
Vih (max.) = Vdd + 0.3V DC; Vih (max.) = Vdd + 2.0V AC (pulse width -2.0ns). Not 100% tested.
4
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
06/01/2016
IS61WV51232ALL/ALS
IS61WV51232BLL/BLS
IS64WV51232BLL/BLS
HIGH SPEED
OPERATING RANGE (Vdd) (IS61WV51232ALL)
Range
Ambient Temperature
Commercial
0°C to +70°C
Industrial
–40°C to +85°C
Automotive
–40°C to +125°C
Vdd
1.65V-2.2V
1.65V-2.2V
1.65V-2.2V
Speed
20ns
20ns
20ns
OPERATING RANGE (Vdd) (IS61WV51232BLL)(1)
Range
Ambient Temperature
Commercial
0°C to +70°C
Industrial
–40°C to +85°C
Vdd (8 ns)1
3.3V + 5%
3.3V + 5%
Vdd (10 ns)1
2.4V-3.6V
2.4V-3.6V
Note:
1. When operated in the range of 2.4V-3.6V, the device meets 10ns. When operated in the range of 3.3V + 5%,
the device meets 8ns.
OPERATING RANGE (Vdd) (IS64WV51232BLL)
Range
Ambient Temperature
Automotive
–40°C to +125°C
Vdd (10 ns)
2.4V-3.6V
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-8
Symbol Parameter
Test Conditions Min. Max.
Icc
Vdd Dynamic Operating Vdd = Max.,
Com.
—
110
Supply Current
Iout = 0 mA, f = fmax
Ind. — 115
Auto. — —
typ.(2)
Icc1
Operating
Vdd = Max.,
Com.
—
85
Supply Current
Iout = 0 mA, f = 0
Ind. — 90
Auto. —
—
Isb1
TTL Standby Current
Vdd = Max.,
Com.
—
30
(TTL Inputs)
Vin = Vih or Vil
Ind. — 35
CE ≥ Vih, f = 0
Auto.
—
—
Isb2
CMOS Standby
Vdd = Max.,
Com.
—
20
Current (CMOS Inputs) CE ≥ Vdd – 0.2V,
Ind.
—
25
Vin ≥ Vdd – 0.2V, or Auto. — —
Vin ≤ 0.2V, f = 0
typ.(2)
-10
Min. Max.
—
90
— 95
— 140
60
—
85
— 90
— 110
—
30
— 35
—
70
—
20
—
25
— 60
4
-20
Min. Max. Unit
—
50
mA
— 60
— 100
—
45
mA
— 55
— 90
— 30 mA
— 35
—
70
—
20 mA
—
25
—
60
Note:
1. At f = fmax, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
2. Typical values are measured at Vdd = 3.0V, Ta = 25oC and not 100% tested.
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Rev. A
06/01/2016
IS61WV51232ALL/ALS
IS61WV51232BLL/BLS
IS64WV51232BLL/BLS
LOW POWER
OPERATING RANGE (Vdd) (IS61WV51232ALS)
Range
Ambient Temperature
Commercial
0°C to +70°C
Industrial
–40°C to +85°C
Automotive
–40°C to +125°C
Vdd
1.65V-2.2V
1.65V-2.2V
1.65V-2.2V
Speed
35ns
35ns
35ns
OPERATING RANGE (Vdd) (IS61WV51232BLS)(1)
Range
Ambient Temperature
Commercial
0°C to +70°C
Industrial
–40°C to +85°C
Vdd (25 ns)1
2.4V-3.6V
2.4V-3.6V
Note:
1. When operated in the range of 2.4V-3.6V, the device meets 25ns. When operated in the
range of 3.3V + 5%, the device meets 20ns.
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-25
Symbol Parameter
Test Conditions Min. Max.
Icc
Vdd Dynamic Operating Vdd = Max.,
Com.
—
30
Supply Current
Iout = 0 mA, f = fmax
Ind. — 35
Auto. —
60
typ.(2)
25
Icc1
Operating
Vdd = Max.,
Com.
—
20
Supply Current
Iout = 0 mA, f = 0
Ind. — 30
Auto. —
50
Isb1
TTL Standby Current
Vdd = Max.,
Com.
—
15
(TTL Inputs)
Vin = Vih or Vil
Ind. — 20
CE ≥ Vih, f = 0
Auto.
—
40
CMOS Standby
Vdd = Max.,
Com.
—
0.8
Isb2
Current (CMOS Inputs) CE ≥ Vdd – 0.2V,
Ind.
—
1.2
Vin ≥ Vdd – 0.2V, or Auto. — 2
Vin ≤ 0.2V, f = 0
typ.(2)
0.1
-35
Min. Max.
Unit
—
25
mA
— 30
— 60
—
20
mA
— 30
— 50
— 15 mA
— 20
—
40
—
0.8 mA
—
1.2
—
2
0.1
Note:
1. At f = fmax, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
2. Typical values are measured at Vdd = 3.0V, Ta = 25oC and not 100% tested.
6
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
06/01/2016
IS61WV51232ALL/ALS
IS61WV51232BLL/BLS
IS64WV51232BLL/BLS
AC TEST CONDITIONS (HIGH SPEED)
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Level (VRef)
Output Load
Unit
Unit
(2.4V-3.6V)
(3.3V + 5%)
0.4V to Vdd-0.3V
0.4V to Vdd-0.3V
1.5ns
1.5ns
Vdd/2 Vdd/2 + 0.05
See Figures 1 and 2
Unit
(1.65V-2.2V)
0.4V to Vdd-0.2V
1.5ns
Vdd/2
See Figures 1 and 2
See Figures 1 and 2
AC TEST LOADS
319 Ω
ZO = 50Ω
3.3V
50Ω
1.5V
OUTPUT
30 pF
Including
jig and
scope
Figure 1.
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
06/01/2016
OUTPUT
5 pF
Including
jig and
scope
353 Ω
Figure 2.
7
IS61WV51232ALL/ALS
IS61WV51232BLL/BLS
IS64WV51232BLL/BLS
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
-8
Symbol
Parameter Min. Max.
trc
taa
toha
tace
tdoe
thzoe(2)
tlzoe(2)
thzce(2
tlzce(2)
tba
tlzb
thzb
-10
Min. Max. Unit
Read Cycle Time
8
—
10
—
ns
Address Access Time
—
8
—
10
ns
Output Hold Time
2.5
—
2.5
—
ns
CE Access Time
—
8
—
10
ns
OE Access Time
—
5.5
—
6.5
ns
OE to High-Z Output
—
3
—
4
ns
OE to Low-Z Output
0
—
0
—
ns
CE to High-Z Output
0
3
0
4
ns
CE to Low-Z Output
3
—
3
—
ns
Byte Enable to Data Valid
— 5.5
— 6.5 ns
Byte Enable to Low-Z
0
—
0
—
ns
Byte Enable to High-Z
0
3
0
3
ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to 3.0V
and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage.
8
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
06/01/2016
IS61WV51232ALL/ALS
IS61WV51232BLL/BLS
IS64WV51232BLL/BLS
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
-20 ns
Symbol Parameter Min. Max. Unit
trc
Read Cycle Time
20
—
ns
taa
Address Access Time
—
20
ns
toha
Output Hold Time
2.5
—
ns
tace
CE Access Time
—
20
ns
tdoe
OE Access Time
—
8
ns
thzoe(2)
OE to High-Z Output
0
8
ns
tlzoe
OE to Low-Z Output
0
—
ns
thzce
CE to High-Z Output
0
8
ns
tlzce(2)
CE to Low-Z Output
3
—
tba
tlzb
thzb
Byte Enable to Data Valid
—
8
ns
Byte Enable to Low-Z
0
—
ns
Byte Enable to High-Z
0
3
ns
(2)
(2
ns
Notes:
1. Test conditions assume signal transition times of 1.5 ns or less, timing reference levels of 1.25V, input pulse levels of 0.4V to
Vdd-0.3V and output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. Not 100% tested.
Integrated Silicon Solution, Inc. — www.issi.com 9
Rev. A
06/01/2016
IS61WV51232ALL/ALS
IS61WV51232BLL/BLS
IS64WV51232BLL/BLS
AC WAVEFORMS
READ CYCLE NO. 1(1,2) (Address Controlled) (CE = OE = Vil)
t RC
ADDRESS
t OHA
DOUT
t AA
t OHA
DATA VALID
PREVIOUS DATA VALID
READ1.eps
READ CYCLE NO. 2(1,3) (CE and OE Controlled)
t RC
ADDRESS
t AA
t OHA
OE
CE
t LZCE
DOUT
t HZOE
t DOE
t BA
BWa-d
t HZB
t LZB
t LZOE
t ACE
HIGH-Z
t HZCE
DATA VALID
CE_RD2.eps
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE = Vil.
3. Address is valid prior to or coincident with CE LOW transitions.
10
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Rev. A
06/01/2016
IS61WV51232ALL/ALS
IS61WV51232BLL/BLS
IS64WV51232BLL/BLS
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range)
-8 -10
Symbol Parameter Min. Max. Min. Max. Unit
twc
Write Cycle Time
8
—
10
—
ns
tsce
CE to Write End
6.5
—
8
—
ns
taw
Address Setup Time
to Write End
6.5
—
8
—
ns
tha
Address Hold from Write End
0
—
0
—
ns
tsa
Address Setup Time
0
—
0
—
ns
tpwb
BWa-d Valid to End of Write
6.5
—
8
—
ns
tpwe1
WE Pulse Width 6.5 — 8 —
ns
tpwe2
WE Pulse Width (OE = LOW)
8.0
—
10
—
ns
tsd
Data Setup to Write End
5
—
6
—
ns
thd
Data Hold from Write End
0
—
0
—
ns
thzwe(2)
WE LOW to High-Z Output
—
3.5
—
5
ns
tlzwe
WE HIGH to Low-Z Output
2
—
2
—
ns
(2)
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to 3.0V and
output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE LOW, and WE LOW. All signals must be in valid states to initiate a Write, but
any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of
the signal that terminates the write. Shaded area product in development
Integrated Silicon Solution, Inc. — www.issi.com 11
Rev. A
06/01/2016
IS61WV51232ALL/ALS
IS61WV51232BLL/BLS
IS64WV51232BLL/BLS
WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range)
Symbol
Parameter
-20 ns
Min. Max. Unit
twc
Write Cycle Time
20
—
ns
tsce
CE to Write End
12
—
ns
taw
Address Setup Time
to Write End
12
—
ns
tha
Address Hold from Write End
0
—
ns
tsa
Address Setup Time
0
—
ns
tpwb
BWa-d Valid to End of Write
12
—
ns
tpwe1
WE Pulse Width (OE = HIGH)
12
—
ns
tpwe2
WE Pulse Width (OE = LOW)
17
—
ns
tsd
Data Setup to Write End
9
—
ns
thd
Data Hold from Write End
0
—
ns
thzwe(3)
WE LOW to High-Z Output
—
9
ns
tlzwe
WE HIGH to Low-Z Output
3
—
ns
(3)
Notes:
1. Test conditions assume signal transition times of 3ns or less, timing reference levels of 1.5V, input
pulse levels of 0V to 0.3V and output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not
100% tested.
3. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid
states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and
Hold timing are referenced to the rising or falling edge of the signal that terminates the write.
12
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
06/01/2016
IS61WV51232ALL/ALS
IS61WV51232BLL/BLS
IS64WV51232BLL/BLS
AC WAVEFORMS
WRITE CYCLE NO. 1(1,2) (CE Controlled, OE = HIGH or LOW)
t WC
VALID ADDRESS
ADDRESS
t SA
t SCE
t HA
CE
t AW
t PWE1
t PWE2
WE
t HZWE
DOUT
DATA UNDEFINED
t LZWE
HIGH-Z
t SD
DIN
t HD
DATAIN VALID
CE_WR1.eps
Integrated Silicon Solution, Inc. — www.issi.com 13
Rev. A
06/01/2016
IS61WV51232ALL/ALS
IS61WV51232BLL/BLS
IS64WV51232BLL/BLS
AC WAVEFORMS
WRITE CYCLE NO. 2 (WE Controlled. OE is HIGH During Write Cycle) (1,2)
t WC
ADDRESS
VALID ADDRESS
t HA
OE
CE
LOW
t AW
t PWE1
WE
t SA
t PBW
BWa-d
t HZWE
DOUT
t LZWE
HIGH-Z
DATA UNDEFINED
t SD
t HD
DATAIN VALID
DIN
UB_CEWR2.eps
WRITE CYCLE NO. 3 (WE Controlled. OE is LOW During Write Cycle) (1)
t WC
ADDRESS
VALID ADDRESS
OE
LOW
CE
LOW
t HA
t AW
t PWE2
WE
t SA
t PBW
BWa-d
t HZWE
DOUT
DATA UNDEFINED
t LZWE
HIGH-Z
t SD
DIN
t HD
DATAIN VALID
UB_CEWR3.eps
14
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
06/01/2016
IS61WV51232ALL/ALS
IS61WV51232BLL/BLS
IS64WV51232BLL/BLS
AC WAVEFORMS
WRITE CYCLE NO. 4 (Byte Controlled, Back-to-Back Write) (1,3)
t WC
ADDRESS
t WC
ADDRESS 1
ADDRESS 2
OE
t SA
CE
LOW
t HA
t SA
WE
BWa-d
t HA
t PBW
t PBW
WORD 1
WORD 2
t HZWE
DOUT
t LZWE
HIGH-Z
DATA UNDEFINED
t HD
t SD
DIN
DATAIN
VALID
t HD
t SD
DATAIN
VALID
UB_CEWR4.eps
Notes:
1. The internal Write time is defined by the overlap of and WE = LOW. All signals must be in valid states to initiate a Write, but any can be
deasserted to terminate the Write. The t sa, t ha, t sd, and t hd timing is referenced to the rising or falling edge of the signal that terminates the
Write.
2. Tested with OE HIGH for a minimum of 4 ns before WE = LOW to place the I/O in a HIGH-Z state.
3. WE may be held LOW across many address cycles and the BWa-d pins can be used to control the Write function.
Integrated Silicon Solution, Inc. — www.issi.com 15
Rev. A
06/01/2016
IS61WV51232ALL/ALS
IS61WV51232BLL/BLS
IS64WV51232BLL/BLS
DATA RETENTION SWITCHING CHARACTERISTICS (HIGH SPEED) (IS61WV51232ALL/BLL)
Symbol
Parameter
Test Condition
Min.
Max.
Unit
See Data Retention Waveform
1.2
3.6
V
Idr
Data Retention Current
Vdd = 1.2V, CE ≥ Vdd – 0.2V
Ind.
Auto.
—
—
25
60
mA
tsdr
Data Retention Setup Time
See Data Retention Waveform
0
—
ns
trdr
Recovery Time
See Data Retention Waveform
trc — ns
Vdr Vdd for Data Retention
DATA RETENTION WAVEFORM (CE Controlled)
tSDR
Data Retention Mode
tRDR
VDD
1.65V
1.4V
VDR
CE
GND
16
CE ≥ VDD - 0.2V
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
06/01/2016
IS61WV51232ALL/ALS
IS61WV51232BLL/BLS
IS64WV51232BLL/BLS
DATA RETENTION SWITCHING CHARACTERISTICS (LOW POWER) (IS61WV51232ALS/BLS)
Symbol
Parameter
Test Condition
Min.
Max.
Unit
See Data Retention Waveform
1.2
3.6
V
Idr
Data Retention Current
Vdd = 1.2V, CE ≥ Vdd – 0.2V
Ind.
Auto.
—
—
1.2
2
mA
tsdr
Data Retention Setup Time
See Data Retention Waveform
0
—
ns
trdr
Recovery Time
See Data Retention Waveform
trc — ns
Vdr Vdd for Data Retention
DATA RETENTION WAVEFORM (CE Controlled)
tSDR
Data Retention Mode
tRDR
VDD
1.65V
1.4V
VDR
CE
GND
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
06/01/2016
CE ≥ VDD - 0.2V
17
IS61WV51232ALL/ALS
IS61WV51232BLL/BLS
IS64WV51232BLL/BLS
ORDERING INFORMATION
Industrial Range: -40°C to +85°C
Voltage Range: 2.4V to 3.6V
peed (ns)
S
10 (81)
Order Part No.
Package
IS61WV51232BLL-10BI 90-ball BGA (8mm x 13mm)
IS61WV51232BLL-10BLI 90-ball BGA (8mm x 13mm), Lead-free
Note:
1. Speed = 8ns for Vdd = 3.3V + 5%. Speed = 10ns for Vdd = 2.4V - 3.6V
Industrial Range: -40°C to +85°C
Voltage Range: 1.65V to 2.2V
peed (ns)
S
20
Order Part No.
Package
IS61WV51232ALL-20BI 90-ball BGA (8mm x 13mm)
IS61WV51232ALL-20BLI 90-ball BGA (8mm x 13mm), Lead-free
Automotive Range: -40°C to +125°C
Voltage Range: 2.4V to 3.6V
peed (ns)
S
10
18
Order Part No.
Package
IS64WV51232BLL-10BA3 90-ball BGA (8mm x 13mm)
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
06/01/2016
IS61WV51232ALL/ALS
IS61WV51232BLL/BLS
IS64WV51232BLL/BLS
Integrated Silicon Solution, Inc. — www.issi.com 19
Rev. A
06/01/2016
