IS62C256AL-45T

IS65C256AL IS62C256AL 32K x 8 LOW POWER CMOS STATIC RAM ISSI MARCH 2006 ® FEATURES • Access time: 25 ns, 45 ns • Low active power: 200 mW (typical) • Low standby power — 150 µW (typical) CMOS standby — 15 mW (typical) operating • Fully static operation: no clock or refresh required • TTL compatible inputs and outputs • Single 5V power supply • Lead-free available • Industrial and Automotive temperatures available DESCRIPTION The ISSI IS62C256AL/IS65C256AL is a low power, 32,768 word by 8-bit CMOS static RAM. It is fabricated using ISSI's high-performance, low power CMOS technology. When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation can be reduced down to 150 µW (typical) at CMOS input levels. Easy memory expansion is provided by using an active LOW Chip Select (CE) input and an active LOW Output Enable (OE) input. The active LOW Write Enable (WE) controls both writing and reading of the memory. The IS62C256AL/IS65C256AL is pin compatible with other 32Kx8 SRAMs in plastic SOP or TSOP (Type I) package. FUNCTIONAL BLOCK DIAGRAM A0-A14 DECODER 32K X 8 MEMORY ARRAY VDD GND I/O DATA CIRCUIT I/O0-I/O7 COLUMN I/O CE OE WE CONTROL CIRCUIT Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A 03/17/06 1 IS65C256AL IS62C256AL PIN CONFIGURATION 28-Pin SOP ISSI PIN CONFIGURATION 28-Pin TSOP OE A11 A9 A8 A13 WE VDD A14 A12 A7 A6 A5 A4 A3 22 23 24 25 26 27 28 1 2 3 4 5 6 7 21 20 19 18 17 16 15 14 13 12 11 10 9 8 A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 ® A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VDD WE A13 A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 PIN DESCRIPTIONS A0-A14 CE OE WE I/O0-I/O7 VDD GND Address Inputs Chip Select Input Output Enable Input Write Enable Input Input/Output Power Ground TRUTH TABLE Mode Not Selected (Power-down) Output Disabled Read Write WE X H H L CE H L L L OE X H L X I/O Operation High-Z High-Z DOUT DIN VDD Current ISB1, ISB2 ICC1, ICC2 ICC1, ICC2 ICC1, ICC2 ABSOLUTE MAXIMUM RATINGS(1) Symbol VTERM TSTG PT IOUT Parameter Terminal Voltage with Respect to GND Storage Temperature Power Dissipation DC Output Current (LOW) Value –0.5 to +7.0 –65 to +150 Unit V °C W mA 0.5 20 Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. A 03/17/06 IS65C256AL IS62C256AL OPERATING RANGE Part No. IS62C256AL IS62C256AL IS65C256AL Range Commercial Industrial Automotive Ambient Temperature 0°C to +70°C –40°C to +85°C –40°C to +125°C VDD 5V ± 10% 5V ± 10% 5V ± 10% ISSI ® DC ELECTRICAL CHARACTERISTICS Symbol VOH VOL VIH VIL ILI Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage(1) Input Leakage Test Conditions VDD = Min., IOH = –1.0 mA VDD = Min., IOL = 2.1 mA Min. 2.4 — 2.2 –0.3 –1 –2 –10 –1 –2 –10 Max. — 0.4 VDD + 0.5 0.8 1 2 10 1 2 10 Unit V V V V µA GND ≤ VIN ≤ VDD ILO Output Leakage GND ≤ VOUT ≤ VDD, Outputs Disabled Com. Ind. Auto. Com. Ind. Auto. µA Note: 1. VIL = –3.0V for pulse width less than 10 ns. Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. A 03/17/06 3 IS65C256AL IS62C256AL POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) Symbol ICC1 Parameter VDD Operating Supply Current VDD Dynamic Operating Supply Current Test Conditions VDD = Max., CE = VIL IOUT = 0 mA, f = 0 VDD = Max., CE = VIL IOUT = 0 mA, f = fMAX -25 ns Min. Max. — 15 — 20 — 25 — 25 — 30 — 35 15 — 100 — 120 — 150 — 15 — 20 — 50 5 ISSI Com. Ind. Auto. Com. Ind. Auto. typ. (2) Com. Ind. Auto. Com. Ind. Auto. typ. (2) -45 ns Min. Max. — 15 — 20 — 25 — 20 — 25 — 30 12 — 100 — 120 — 150 — 15 — 20 — 50 5 Unit mA ® ICC2 mA ISB1 TTL Standby Current (TTL Inputs) CMOS Standby Current (CMOS Inputs) ISB2 VDD = Max., VIN = VIH or VIL CE ≥ VIH, f = 0 VDD = Max., CE ≥ VDD – 0.2V, VIN ≥ VDD – 0.2V, or VIN ≤ 0.2V, f = 0 µA µA Note: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. Typical values are measured at VDD = 5.0V, TA = 25oC and not 100% tested. CAPACITANCE(1,2) Symbol CIN COUT Parameter Input Capacitance Output Capacitance Conditions VIN = 0V VOUT = 0V Max. 8 10 Unit pF pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25°C, f = 1 MHz, VDD = 5.0V. 4 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. A 03/17/06 IS65C256AL IS62C256AL READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter Read Cycle Time Address Access Time Output Hold Time CE Access Time OE Access Time (2) ISSI -25 ns Min. Max. 25 — 2 — — 0 0 3 0 0 — — 25 — 25 13 — 12 — 12 — 20 -45 ns Min. Max. 45 — 2 — — 0 0 3 0 0 — — 45 — 45 25 — 20 — 20 — 30 Unit ns ns ns ns ns ns ns ns ns ns ns ® tRC tAA tOHA tACS tDOE tLZOE tHZOE(2) tLZCS(2) tHZCS tPU (3) (2) OE to Low-Z Output OE to High-Z Output CE to Low-Z Output CE to High-Z Output CE to Power-Up CE to Power-Down tPD(3) Notes: 1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3. Not 100% tested. AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Levels Output Load Unit 0V to 3.0V 3 ns 1.5V See Figures 1 and 2 AC TEST LOADS 480 Ω 5V 5V 480 Ω OUTPUT 100 pF Including jig and scope 255 Ω OUTPUT 5 pF Including jig and scope 255 Ω Figure 1. Figure 2. Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. A 03/17/06 5 IS65C256AL IS62C256AL AC WAVEFORMS READ CYCLE NO. 1(1,2) t RC ADDRESS ISSI ® t AA t OHA DOUT PREVIOUS DATA VALID t OHA DATA VALID READ1.eps READ CYCLE NO. 2(1,3) t RC ADDRESS t AA OE t OHA t HZOE t DOE CE t LZOE t LZCS t ACS DATA VALID CS_RD2.eps t HZCS DOUT HIGH-Z Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE = VIL. 3. Address is valid prior to or coincident with CE LOW transitions. 6 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. A 03/17/06 IS65C256AL IS62C256AL WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range) Symbol Parameter Write Cycle Time CE to Write End Address Setup Time to Write End Address Hold from Write End Address Setup Time WE Pulse Width Data Setup to Write End Data Hold from Write End -25 ns Min. Max. 25 15 15 0 0 15 12 0 — — — — — — — — -45 ns Min. Max. 45 35 25 0 0 25 20 0 — — — — — — — — ISSI Unit ns ns ns ns ns ns ns ns ® tWC tSCS tAW tHA tSA tPWE1, tPWE2(4) tSD tHD Notes: 1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. 4. Tested with OE HIGH. AC WAVEFORMS WRITE CYCLE NO. 1 (CE Controlled, OE is HIGH or LOW) (1 ) t WC ADDRESS VALID ADDRESS t SA CE t SCS t AW t PWE1 t PWE2 t HZWE t HA WE t LZWE HIGH-Z DOUT DATA UNDEFINED t SD DIN t HD DATAIN VALID CS_WR1.eps Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. A 03/17/06 7 IS65C256AL IS62C256AL AC WAVEFORMS WRITE CYCLE NO. 2 (OE is HIGH During Write Cycle) (1,2) t WC ADDRESS VALID ADDRESS ISSI ® t HA OE CE LOW t AW t PWE1 WE t SA DOUT DATA UNDEFINED t HZWE HIGH-Z t LZWE t SD DIN t HD DATAIN VALID CS_WR2.eps WRITE CYCLE NO. 3 (OE is LOW During Write Cycle) (1) t WC ADDRESS OE CE VALID ADDRESS LOW t HA LOW t AW WE t PWE2 t LZWE HIGH-Z t SA DOUT DATA UNDEFINED t HZWE t SD DIN t HD DATAIN VALID CS_WR3.eps Notes: 1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. 2. I/O will assume the High-Z state if OE = VIH. 8 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. A 03/17/06 IS65C256AL IS62C256AL DATA RETENTION SWITCHING CHARACTERISTICS Symbol Parameter Test Condition See Data Retention Waveform VDD = 2.0V, CE ≥ VDD – 0.2V VIN ≥ VDD – 0.2V, or VIN ≤ VSS + 0.2V Com. Ind. Auto. Min. 2.0 — — — 0 — — — Typ. ISSI Max. 5.5 15 20 50 — — Unit V µA ® VDR IDR VDD for Data Retention Data Retention Current tSDR tRDR Note: Data Retention Setup Time See Data Retention Waveform Recovery Time See Data Retention Waveform ns ns tRC 1. Typical Values are measured at VDD = 5V, TA = 25oC and not 100% tested. DATA RETENTION WAVEFORM (CE Controlled) tSDR VDD 4.5V Data Retention Mode tRDR 2.2V VDR CE ≥ VDD - 0.2V CE GND Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. A 03/17/06 9 IS65C256AL IS62C256AL ISSI ® ORDERING INFORMATION Commercial Range: 0°C to +70°C Speed (ns) 45 Order Part No. IS62C256AL-45T IS62C256AL-45TL IS62C256AL-45U IS62C256AL-45UL Package TSOP TSOP, Lead-free Plastic SOP Plastic SOP, Lead-free ORDERING INFORMATION Industrial Range: –40°C to +85°C Speed (ns) 25 45 Order Part No. IS62C256AL-25TI IS62C256AL-25UI IS62C256AL-45TI IS62C256AL-45TLI IS62C256AL-45UI IS62C256AL-45ULI Package TSOP Plastic SOP TSOP TSOP, Lead-free Plastic SOP Plastic SOP, Lead-free ORDERING INFORMATION Automotive Range: –40°C to +125°C Speed (ns) 25 Order Part No. IS65C256AL-25TA3 IS65C256AL-25TLA3 IS65C256AL-25UA3 IS65C256AL-25ULA3 IS65C256AL-45TA3 IS65C256AL-45TLA3 IS65C256AL-45UA3 IS65C256AL-45ULA3 Package TSOP TSOP, Lead-free Plastic SOP Plastic SOP, Lead-free TSOP TSOP, Lead-free Plastic SOP Plastic SOP, Lead-free 45 10 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. A 03/17/06 PACKAGING INFORMATION Plastic TSOP - 28-pins Package Code: T (Type I) 1 ISSI ® E H N D SEATING PLANE S A e B L A1 α C Symbol Ref. Std. No. Leads A A1 B C D E H e L α Plastic TSOP (T—Type I) Millimeters Inches Min Max Min Max 28 1.00 1.20 0.05 0.20 0.16 0.27 0.10 0.20 7.90 8.10 11.70 11.90 13.20 13.60 0.55 BSC 0.30 0.70 0° 5° 0.037 0.047 0.002 0.008 0.006 0.011 0.004 0.008 0.308 0.316 0.456 0.465 0.515 0.531 0.022 BSC 0.011 0.027 0° 5° Notes: 1. Controlling dimension: millimeters, unless otherwise specified. 2. BSC = Basic lead spacing between centers. 3. Dimensions D and E do not include mold flash protrusions and should be measured from the bottom of the package. 4. Formed leads shall be planar with respect to one another within 0.004 inches at the seating plane. Integrated Silicon Solution, Inc. PK13197T28 Rev. B 01/31/97 PACKAGING INFORMATION 330-mil Plastic SOP Package Code: U (28-pin) N ISSI ® E1 E 1 D SEATING PLANE S A h x 45o e B L A1 α C MILLIMETERS Sym. A A1 B C D E E1 e h L α S Min. 28 2.84 — 0.51 — 18.24 12.12 8.53 0.51 1.14 8 o INCHES Min. 28 — 0.004 0.014 0.010 0.708 0.453 0.326 0.012 0.028 0 o Max. Max. 0.112 — 0.020 — 0.718 0.477 0.336 0.020 0.045 8o 0.047 No. Leads — 0.10 0.36 0.25 Notes: 1. Controlling dimension: inches, unless otherwise specified. 2. BSC = Basic lead spacing between centers. 3. Dimensions D and E1 do not include mold flash protrusions and should be measured from the bottom of the package. 4. Formed leads shall be planar with respect to one another within 0.004 inches at the seating plane. 17.98 11.51 8.28 0.30 0.71 0 o 1.27 BSC 0.050 BSC 0.58 1.19 0.023 Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. C 02/26/03