IS62C256AL-45TLI

IS65C256AL IS62C256AL 32K x 8 LOW POWER CMOS STATIC RAM FEATURES • • • • • • • • Access time: 25 ns, 45 ns Low active power: 200 mW (typical) Low standby power — 150 µW (typical) CMOS standby — 15 mW (typical) operating Fully static operation: no clock or refresh required TTL compatible inputs and outputs Single 5V power supply Lead-free available Industrial and Automotive temperatures available FEBRUARY 2020 DESCRIPTION The ISSI IS62C256AL/IS65C256AL is a low power, 32,768 word by 8-bit CMOS static RAM. It is fabricated using ISSI's high-performance, low power CMOS technology. When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation can be reduced down to 150 µW (typical) at CMOS input levels. Easy memory expansion is provided by using an active LOW Chip Select (CE) input and an active LOW Output Enable (OE) input. The active LOW Write Enable (WE) controls both writing and reading of the memory. The IS62C256AL/IS65C256AL is pin compatible with other 32Kx8 SRAMs in plastic SOP or TSOP (Type I) package. FUNCTIONAL BLOCK DIAGRAM A0-A14 DECODER 32K X 8 MEMORY ARRAY I/O DATA CIRCUIT COLUMN I/O VDD GND I/O0-I/O7 CE OE WE CONTROL CIRCUIT Copyright © 2020 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc. — www.issi.com 1 Rev. E1 02/07/2020 IS65C256AL IS62C256AL PIN CONFIGURATION PIN CONFIGURATION 28-Pin TSOP 28-Pin SOP A14 1 28 VDD A12 2 27 WE A7 3 26 A13 A6 4 25 A8 A5 5 24 A9 A4 6 23 A11 A3 7 22 OE A2 8 21 A10 A1 9 20 CE A0 10 19 I/O7 I/O0 11 18 I/O6 I/O1 12 17 I/O5 I/O2 13 16 I/O4 GND 14 15 I/O3 PIN DESCRIPTIONS A0-A14 Address Inputs CE Chip Select Input OE Output Enable Input WE Write Enable Input I/O0-I/O7 Input/Output Vdd Power GND Ground OE A11 A9 A8 A13 WE VDD A14 A12 A7 A6 A5 A4 A3 21 20 19 18 17 16 15 14 13 12 11 10 9 8 22 23 24 25 26 27 28 1 2 3 4 5 6 7 A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 TRUTH TABLE Mode WE Not Selected X (Power-down) Output Disabled H Read H Write L CE H OE I/O Operation Vdd Current X High-Z Isb1, Isb2 L L L H L X High-Z Dout Din Icc1, Icc2 Icc1, Icc2 Icc1, Icc2 ABSOLUTE MAXIMUM RATINGS(1) Symbol Parameter Vterm Terminal Voltage with Respect to GND Tstg Storage Temperature Pt Power Dissipation Iout DC Output Current (LOW) Value Unit –0.5 to +7.0 V –65 to +150 °C 0.5 W 20 mA Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2 Integrated Silicon Solution, Inc. Rev. E1 02/07/2020 IS65C256AL IS62C256AL OPERATING RANGE Part No. IS62C256AL IS62C256AL IS65C256AL Range Commercial Industrial Automotive Ambient Temperature 0°C to +70°C –40°C to +85°C –40°C to +125°C Vdd 5V ± 10% 5V ± 10% 5V ± 10% DC ELECTRICAL CHARACTERISTICS Symbol Parameter Test Conditions Min. Max. Unit Voh Output HIGH Voltage Vdd = Min., Ioh = –1.0 mA 2.4 — V Vol Output LOW Voltage Vdd = Min., Iol = 2.1 mA — 0.4 V Vih Input HIGH Voltage 2.2 Vdd + 0.5 V Vil Input LOW Voltage(1) –0.3 0.8 V Ili Input Leakage GND ≤ Vin ≤ Vdd Com. –1 1 µA Ind. –2 2 Auto. –10 10 Ilo Output Leakage GND ≤ Vout ≤ Vdd, Com. –1 1 µA Outputs Disabled Ind. –2 2 Auto. –10 10 Note: 1. Vil = –3.0V for pulse width less than 10 ns. Integrated Silicon Solution, Inc. 3 Rev. E1 02/07/2020 IS65C256AL IS62C256AL POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)         -25 ns Symbol Parameter Test Conditions Min. Max. Icc1 Vdd Operating Vdd = Max., CE = Vil Com. — 15 Supply Current Iout = 0 mA, f = 0 Ind. — 20 Auto. — 25 Icc2 Vdd Dynamic Operating Vdd = Max., CE = Vil Com. — 25 Supply Current Iout = 0 mA, f = fmax Ind. — 30 Auto. — 35 typ. (2) 15 Isb1 TTL Standby Current Vdd = Max.,   Com. — 100 (TTL Inputs) Vin = Vih or Vil Ind. — 120 CE ≥ Vih, f = 0 Auto. — 150 Isb2 CMOS Standby Vdd = Max., Com. — 15 Current (CMOS Inputs) CE ≥ Vdd – 0.2V, Ind. — 20 Vin ≥ Vdd – 0.2V, or Auto. — 50 Vin ≤ 0.2V, f = 0 typ. (2) 5 -45 ns        Min. Max. Unit — 15 mA — 20 — 25 — 20 mA — 25 — 30 12 — 100 µA — 120 — 150 — 15 µA — 20 — 50 5 Note: 1. At f = fmax, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. Typical values are measured at Vdd = 5.0V, Ta = 25oC and not 100% tested. CAPACITANCE(1,2) Symbol Cin Cout Parameter Input Capacitance Output Capacitance Conditions Vin = 0V Vout = 0V Max. Unit 8 pF 10 pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: Ta = 25°C, f = 1 MHz, Vdd = 5.0V. 4 Integrated Silicon Solution, Inc. Rev. E1 02/07/2020 IS65C256AL IS62C256AL READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter trc Read Cycle Time taa Address Access Time toha Output Hold Time tacs CE Access Time tdoe OE Access Time (2) tlzoe OE to Low-Z Output thzoe(2) OE to High-Z Output (2) tlzcs CE to Low-Z Output (2) thzcs CE to High-Z Output (3) tpu CE to Power-Up tpd(3) CE to Power-Down   -25 ns     Min. Max. 25 — — 25 2 — — 25 — 13 0 — 0 12 3 — 0 12 0 — — 20 -45 ns             Min. Max. Unit 45 — ns — 45 ns 2 — ns — 45 ns — 25 ns 0 — ns 0 20 ns 3 — ns 0 20 ns 0 — ns — 30 ns Notes: 1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3. Not 100% tested. AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Levels Output Load Unit 0V to 3.0V 3 ns 1.5V See Figures 1 and 2 AC TEST LOADS 1838  480 Ω 5V 5V OUTPUT OUTPUT 100 pF Including jig and scope Figure 1. 993  5 pF Including jig and scope 255 Ω Figure 2. Integrated Silicon Solution, Inc. 5 Rev. E1 02/07/2020 IS65C256AL IS62C256AL AC WAVEFORMS READ CYCLE NO. 1(1,2) t RC ADDRESS t OHA DOUT t AA t OHA DATA VALID PREVIOUS DATA VALID READ1.eps READ CYCLE NO. 2(1,3) t RC ADDRESS t AA t OHA OE t HZOE t DOE t LZOE CE t LZCS DOUT t ACS HIGH-Z t HZCS DATA VALID CS_RD2.eps Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE = Vil. 3. Address is valid prior to or coincident with CE LOW transitions. 6 Integrated Silicon Solution, Inc. Rev. E1 02/07/2020 IS65C256AL IS62C256AL WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range)     -25 ns Symbol Parameter Min. Max. -45 ns             Min. Max. Unit twc Write Cycle Time 25 — 45 — ns tscs CE to Write End 15 — 35 — ns taw Address Setup Time to Write End 15 — 25 — ns tha Address Hold from Write End 0 — 0 — ns Address Setup Time 0 — 0 — ns tpwe WE Pulse Width 15 — 25 — ns tsd Data Setup to Write End 12 — 20 — ns thd Data Hold from Write End 0 — 0 — ­ns thzwe(2) WE LOW to High-Z Output — 8 — 20 ­ns tlzwe WE HIGH to Low-Z Output 0 — 0 — ­ns tsa (4) (2) Notes: 1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. 4. Tested with OE HIGH. AC WAVEFORMS WRITE CYCLE NO. 1 (CE Controlled, OE is HIGH or LOW) (1 ) t WC VALID ADDRESS ADDRESS t SA t SCS t HA CE t AW t PWE WE t HZWE DOUT DATA UNDEFINED t LZWE HIGH-Z t SD DIN t HD DATAIN VALID CS_WR1.eps Integrated Silicon Solution, Inc. 7 Rev. E1 02/07/2020 IS65C256AL IS62C256AL AC WAVEFORMS WRITE CYCLE NO. 2 (OE is HIGH During Write Cycle) (1,2) t WC ADDRESS VALID ADDRESS t HA OE CE LOW t AW t PWE1 WE t SA DOUT t HZWE t LZWE HIGH-Z DATA UNDEFINED t SD t HD DATAIN VALID DIN CS_WR2.eps WRITE CYCLE NO. 3 (OE is LOW During Write Cycle) (1) t WC ADDRESS VALID ADDRESS OE LOW CE LOW t HA t AW t PWE2 WE t SA DOUT DATA UNDEFINED t HZWE t LZWE HIGH-Z t SD DIN t HD DATAIN VALID CS_WR3.eps Notes: 1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. 2. I/O will assume the High-Z state if OE = Vih. 8 Integrated Silicon Solution, Inc. Rev. E1 02/07/2020 IS65C256AL IS62C256AL DATA RETENTION SWITCHING CHARACTERISTICS Symbol Parameter Vdr Vdd for Data Retention Idr Data Retention Current tsdr Data Retention Setup Time trdr Recovery Time Note: Test Condition See Data Retention Waveform Vdd = 2.0V, CE ≥ Vdd – 0.2V Com. Vin ≥ Vdd – 0.2V, or Vin ≤ Vss + 0.2V Ind. Auto. See Data Retention Waveform See Data Retention Waveform Min. Typ. Max. Unit 2.0 5.5 V — — 15 µA — — 20 — — 50 0 — ns trc — ns 1. Typical Values are measured at Vdd = 5V, Ta = 25oC and not 100% tested. DATA RETENTION WAVEFORM (CE Controlled) tSDR 4.5V 2.2V Data Retention Mode tRDR VDD VDR CE GND CE ≥ VDD - 0.2V Integrated Silicon Solution, Inc. 9 Rev. E1 02/07/2020 IS65C256AL IS62C256AL ORDERING INFORMATION Commercial Range: 0°C to +70°C Speed (ns) 45 Order Part No. IS62C256AL-45TL IS62C256AL-45UL Package TSOP, Lead-free Plastic SOP, Lead-free ORDERING INFORMATION Industrial Range: –40°C to +85°C Speed (ns) 25 45 Order Part No. IS62C256AL-25ULI IS62C256AL-45TLI IS62C256AL-45ULI Package Plastic SOP, Lead-free TSOP, Lead-free Plastic SOP, Lead-free ORDERING INFORMATION Automotive Range: –40°C to +125°C Speed (ns) 25 45 10 Order Part No. IS65C256AL-25TLA3 IS65C256AL-25ULA3 IS65C256AL-45TLA3 IS65C256AL-45ULA3 Package TSOP, Lead-free Plastic SOP, Lead-free TSOP, Lead-free Plastic SOP, Lead-free Integrated Silicon Solution, Inc. Rev. E1 02/07/2020 IS65C256AL IS62C256AL Integrated Silicon Solution, Inc. 11 Rev. E1 02/07/2020 IS65C256AL IS62C256AL 12 Integrated Silicon Solution, Inc. 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