IS62LV256-70T

IS62LV256 32K x 8 LOW VOLTAGE STATIC RAM ISSI DESCRIPTION ® DECEMBER 2002 FEATURES • Access time: 45, 70 ns • Low active power: 70 mW • Low standby power — 45 µW CMOS standby • Fully static operation: no clock or refresh required • TTL compatible inputs and outputs • Single 3.3V power supply The ISSI IS62LV256 is a very high-speed, low power, 32,768-word by 8-bit static RAM. It is fabricated using ISSI's high-performance CMOS double-metal technology. When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation is reduced to 10 µW (typical) with CMOS input levels. Easy memory expansion is provided by using an active LOW Chip Enable (CE) input and an active LOW Output Enable (OE) input. The active LOW Write Enable (WE) controls both writing and reading of the memory. The IS62LV256 is pin compatible with other 32K x 8 SRAMs in 300-mil SOJ, 330-mil plastic SOP, and TSOP (Type I Normal and Reverse Bent) packages. FUNCTIONAL BLOCK DIAGRAM A0-A14 DECODER 256 X 1024 MEMORY ARRAY VCC GND I/O DATA CIRCUIT I/O0-I/O7 COLUMN I/O CE OE WE CONTROL CIRCUIT Copyright © 2002 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. K 12/11/02 1 IS62LV256 PIN CONFIGURATION 28-Pin SOJ and SOP ISSI 28-Pin TSOP (Type I) (Normal Bent) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE A13 A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 OE A11 A9 A8 A13 WE VCC A14 A12 A7 A6 A5 A4 A3 22 23 24 25 26 27 28 1 2 3 4 5 6 7 21 20 19 18 17 16 15 14 13 12 11 10 9 8 ® A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 28-Pin TSOP (Type I) (Reverse Bent) PIN DESCRIPTIONS A0-A14 CE OE WE I/O0-I/O7 Vcc GND Address Inputs Chip Enable Input Output Enable Input Write Enable Input Input/Output Power Ground A3 A4 A5 A6 A7 A12 A14 VCC WE A13 A8 A9 A11 OE 7 6 5 4 3 2 1 28 27 26 25 24 23 22 8 9 10 11 12 13 14 15 16 17 18 19 20 21 A2 A1 A0 I/O0 I/O1 I/O2 GND I/O3 I/O4 I/O5 I/O6 I/O7 CE A10 TRUTH TABLE Mode Not Selected (Power-down) Output Disabled Read Write WE X H H L CE H L L L OE X H L X I/O Operation High-Z High-Z DOUT DIN Vcc Current ISB1, ISB2 ICC1, ICC2 ICC1, ICC2 ICC1, ICC2 2 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. K 12/11/02 IS62LV256 ABSOLUTE MAXIMUM RATINGS(1) Symbol VTERM TBIAS TSTG PT IOUT Parameter Terminal Voltage with Respect to GND Temperature Under Bias Storage Temperature Power Dissipation DC Output Current (LOW) Value –0.5 to +4.6 –55 to +125 –65 to +150 0.5 20 Unit V °C °C W mA ISSI ® Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. OPERATING RANGE Range Commercial Industrial Ambient Temperature 0°C to +70°C –40°C to +85°C VCC 3.3V ± 5% 3.3V ± 5% DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Symbol Parameter VOH VOL VIH VIL ILI ILO Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Output Leakage (1) Test Conditions VCC = Min., IOH = –1.0 mA VCC = Min., IOL = 2.1 mA Min. 2.4 — 2.2 –0.3 Max. — 0.4 VCC + 0.3 0.8 2 5 2 5 Unit V V V V µA µA GND ≤ VIN ≤ VCC GND ≤ VOUT ≤ VCC, Outputs Disabled Com. Ind. Com. Ind. –2 –5 –2 –5 Notes: 1. VIL = –3.0V for pulse width less than 10 ns. 2. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. K 12/11/02 3 IS62LV256 POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) Symbol ICC1 ICC2 ISB1 Parameter Vcc Operating Supply Current Vcc Dynamic Operating Supply Current TTL Standby Current (TTL Inputs) CMOS Standby Current (CMOS Inputs) Test Conditions VCC = Max., CE = VIL IOUT = 0 mA, f = 0 VCC = Max., CE = VIL IOUT = 0 mA, f = fMAX VCC = Max., VIN = VIH or VIL CE ≥ VIH, f = 0 VCC = Max., CE ≥ VCC – 0.2V, VIN ≥ VCC – 0.2V, or VIN ≤ 0.2V, f = 0 Com. Ind. Com. Ind. Com. Ind. Com. Ind. -45 ns Min. Max. — — — — — — — — 20 30 35 45 2 5 90 200 ISSI -70 ns Min. Max. — — — — — — — — 20 30 30 40 2 5 90 200 Unit mA mA mA ® ISB2 µA Notes: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. CAPACITANCE(1,2) Symbol CIN COUT Parameter Input Capacitance Output Capacitance Conditions VIN = 0V VOUT = 0V Max. 6 5 Unit pF pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25°C, f = 1 MHz, Vcc =3.3V. 4 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. K 12/11/02 IS62LV256 AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Levels Output Load Unit 0V to 3.0V 5 ns 1.5V See Figures 1a and 1b ISSI ® 1213 Ω 3.3V 3.3V 1213 Ω OUTPUT 100 pF Including jig and scope 1378 Ω OUTPUT 5 pF Including jig and scope 1378 Ω Figures 1a Figures 1b READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) -45 ns Symbol Parameter Read Cycle Time Address Access Time Output Hold Time CE Access Time OE Access Time OE to Low-Z Output OE to High-Z Output CE to Low-Z Output CE to High-Z Output CE to Power-Up CE to Power-Down (2) -70 ns Max. — 45 — 45 25 — 20 — 20 — 30 Min. 70 — 2 — — 0 0 3 0 0 — Max. — 70 — 70 35 — 25 — 25 — 50 Unit ns ns ns ns ns ns ns ns ns ns ns Min. 45 — 2 — — 0 0 3 0 0 — tRC tAA tOHA tACE tDOE tLZOE(2) tHZOE tLZCE tPU(3) tPD (3) (2) tHZCE(2) Notes: 1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1a. 2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3. Not 100% tested. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. K 12/11/02 5 IS62LV256 AC WAVEFORMS READ CYCLE NO. 1(1,2) tRC ISSI ® ADDRESS tAA tOHA tOHA DATA VALID DOUT READ CYCLE NO. 2(1,3) tRC ADDRESS tAA tOHA OE tDOE tHZOE CE tACE tLZCE tLZOE tHZCE DATA VALID HIGH-Z DOUT HIGH-Z tPU tPD 50% 50% ICC SUPPLY CURRENT ISB Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE = VIL. 3. Address is valid prior to or coincident with CE LOW transitions. 6 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. K 12/11/02 IS62LV256 WRITE CYCLE SWITCHING CHARACTERISTICS(1,2,3) (Over Operating Range) Symbol Parameter Write Cycle Time CE to Write End Address Setup Time to Write End Address Hold from Write End Address Setup Time (4) ISSI -45 ns Min. Max. 45 35 25 0 0 25 20 0 — — — — — — — — -70 ns Min. Max. 70 60 60 0 0 55 30 0 — — — — — — — — Unit ns ns ns ns ns ns ns ns ® tWC tSCE tAW tHA tSA tPWE tSD tHD WE Pulse Width Data Setup to Write End Data Hold from Write End Notes: 1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1a. 2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. 4. Tested with OE HIGH. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. K 12/11/02 7 IS62LV256 AC WAVEFORMS WRITE CYCLE NO. 1 (WE Controlled)(1,2) tWC ISSI ® ADDRESS tSCE tHA CE tAW WE tSA tHZWE tPWE tLZWE HIGH-Z DOUT DATA UNDEFINED tSD tHD DIN DATA-IN VALID WRITE CYCLE NO. 2 (CE Controlled)(1,2) tWC ADDRESS tSA tSCE tHA CE tAW tPWE WE tHZWE tLZWE HIGH-Z DOUT DATA UNDEFINED tSD tHD DIN DATA-IN VALID Notes: 1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. 2. I/O will assume the High-Z state if OE • VIH. 8 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. K 12/11/02 IS62LV256 ISSI ® ORDERING INFORMATION Commercial Range: 0°C to +70°C Speed (ns) 45 45 45 70 70 70 Order Part No. IS62LV256-45J IS62LV256-45U IS62LV256-45T IS62LV256-70U IS62LV256-70T IS62LV256-70RT Package 300-MIL PLASTIC SOJ 330-MIL SOP TSOP (TYPE I NORMAL BENT) 330-MIL SOP TSOP (TYPE I NORMAL BENT) TSOP (TYPE I REVERSE BENT) Industrial Range: –40°C to +85°C Speed (ns) 45 45 45 70 70 70 Order Part No. IS62LV256-45JI IS62LV256-45UI IS62LV256-45TI IS62LV256-70UI IS62LV256-70TI IS62LV256-70RTI Package 300-MIL PLASTIC SOJ 330-mil SOP TSOP (TYPE I NORMAL BENT) 330-mil SOP TSOP (TYPE I NORMAL BENT) TSOP (TYPE I REVERSE BENT) Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. K 12/11/02 9