IS62VV25616LL-85M

IS62VV25616LL 256K x 16 LOW VOLTAGE, 1.8V ULTRA LOW POWER CMOS STATIC RAM FEATURES • High-speed access time: 70, 85, ns • CMOS low power operation – 36 mW (typical) operating – 9 µW (typical) CMOS standby • Single 1.7V- 2.25 VDD power supply • Fully static operation: no clock or refresh required • Three state outputs • Data control for upper and lower bytes • Industrial temperature available • Available in the 44-pin TSOP (Type II) and 48-pin mini BGA (7.2mm x 8.7mm) ISSI AUGUST 2002 ® DESCRIPTION The ISSI IS62VV25616LL is a high-speed, 4,194,304 bit static RAMs organized as 262,144 words by 16 bits. They are fabricated using ISSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields highperformance and low power consumption devices. For the IS62VV25616LL, when CE is HIGH (deselected) or CE is low and both LB and UB are HIGH, the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs, CE and OE. The active LOW Write Enable (WE) controls both writing and reading of the memory. A data byte allows Upper Byte (UB) and Lower Byte (LB) access. The IS62VV25616LL is packaged in the JEDEC standard 44-pin TSOP (Type II) and 48-pin mini BGA (7.2mm x 8.7mm). FUNCTIONAL BLOCK DIAGRAM A0-A17 DECODER 256K x 16 MEMORY ARRAY VDD GND I/O0-I/O7 Lower Byte I/O8-I/O15 Upper Byte I/O DATA CIRCUIT COLUMN I/O CE OE WE UB LB CONTROL CIRCUIT Copyright © 2002 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B 08/07/02 1 IS62VV25616LL PIN CONFIGURATIONS 44-Pin TSOP (Type II) A4 A3 A2 A1 A0 CE I/O0 I/O1 I/O2 I/O3 VDD GND I/O4 I/O5 I/O6 I/O7 WE A16 A15 A14 A13 A12 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE UB LB I/O15 I/O14 I/O13 I/O12 GND VDD I/O11 I/O10 I/O9 I/O8 NC A8 A9 A10 A11 A17 ISSI 48-Pin mini BGA (7.2mm x 8.7mm) 1 2 3 4 5 6 ® A B C D E F G H LB I/O8 I/O9 GND VDD I/O14 I/O15 NC OE UB I/O10 I/O11 I/O12 I/O13 NC A8 A0 A3 A5 A17 NC A14 A12 A9 A1 A4 A6 A7 A16 A15 A13 A10 A2 CE I/O1 I/O3 I/O4 I/O5 WE A11 N/C I/O0 I/O2 VDD GND I/O6 I/O7 NC PIN DESCRIPTIONS A0-A17 I/O0-I/O15 CE OE WE Address Inputs Data Inputs/Outputs Chip Enable Input Output Enable Input Write Enable Input LB UB NC VDD GND Lower-byte Control (I/O0-I/O7) Upper-byte Control (I/O8-I/O15) No Connection Power Ground TRUTH TABLE Mode Not Selected Output Disabled Read WE X X H X H H H L L L CE H L L L L L L L L L OE X X H X L L L X X X LB X H X H L H L L H L UB X H X H H L L H L L I/O PIN I/O0-I/O7 I/O8-I/O15 High-Z High-Z High-Z High-Z DOUT High-Z DOUT DIN High-Z DIN High-Z High-Z High-Z High-Z High-Z DOUT DOUT High-Z DIN DIN Vdd Current ISB1, ISB2 ISB1, ISB2 ICC ISB1, ISB2 I CC Write I CC 2 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B 08/07/02 IS62VV25616LL OPERATING RANGE Range Commercial Industrial Ambient Temperature 0°C to +70°C –40°C to +85°C VDD 1.7V - 2.25V 1.7V - 2.25V ISSI ® ABSOLUTE MAXIMUM RATINGS(1) Symbol VTERM VDD TSTG PT Parameter Terminal Voltage with Respect to GND Vdd Related to GND Storage Temperature Power Dissipation Value –0.2 to VDD+0.25 –0.2 to +2.5 –65 to +150 1.0 Unit V V °C W Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Symbol VOH VOL VIH VIL(1) ILI ILO Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Output Leakage GND ≤ VIN ≤ VDD GND ≤ VOUT ≤ VDD, Outputs Disabled Test Conditions IOH = -0.1 mA IOL = 0.1 mA Min. 1.4 — 1.4 –0.3 –1 –1 Max. — 0.2 VDD + 0.2 0.4 1 1 Unit V V V V µA µA Notes: 1. VIL (min.) = –1.0V for pulse width less than 10 ns. CAPACITANCE(1) Symbol CIN COUT Parameter Input Capacitance Input/Output Capacitance Conditions VIN = 0V VOUT = 0V Max. 8 10 Unit pF pF Note: 1. Tested initially and after any design or process changes that may affect these parameters. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B 08/07/02 3 IS62VV25616LL AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0.4V to VDD - 0.2V 5 ns 0.9V See Figures 1 and 2 ISSI ® AC TEST LOADS 3070 Ω 2.8V 2.8V 3070 Ω OUTPUT 30 pF Including jig and scope 3150 Ω OUTPUT 5 pF Including jig and scope 3150 Ω Figure 1 Figure 2 4 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B 08/07/02 IS62VV25616LL POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) Symbol ICC ICC1 ISB1 Parameter Test Conditions Com. Ind. Com. Ind. Com. Ind. -70 Min. Max. — — — — — — 30 35 3 3 0.3 0.3 ISSI -85 Min. Max. — — — — — — 30 35 3 3 0.3 0.3 ® Unit mA mA mA Vdd Dynamic Operating VDD = Max., Supply Current IOUT = 0 mA, f = fMAX Operating Supply Current TTL Standby Current (TTL Inputs) OR ULB Control VDD = Max., IOUT = 0 mA, f = 1 MHZ VDD = Max., VIN = VIH or VIL CE ≥ VIH , f = 0 Vdd = Max., VIN = VIH or VIL CE = VIL, f = 0, UB = VIH, LB = VIH ISB2 CMOS Standby VDD = 1.95V., Com. Current (CMOS Inputs) CE ≥ VDD – 0.2V, Ind. VIN ≥ VDD – 0.2V, or VIN ≤ 0.2V, f = 0 OR ULB Control VDD = 1.95V., CE = VIL VIN ≤ 0.2V, f = 0; UB / LB = VDD – 0.2V — — 10 10 — — 10 10 µA Note: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter Read Cycle Time Address Access Time Output Hold Time CE Access Time OE Access Time (2) -70 Min. Max. 70 — 10 — — — 5 0 10 — 0 0 — 70 — 70 35 25 — 25 — 70 25 — -85 Min. Max. 85 — 10 — — — 5 0 10 — 0 0 — 85 — 85 40 25 — 25 — 85 25 — Unit ns ns ns ns ns ns ns ns ns ns ns ns tRC tAA tOHA tACE tDOE tHZOE tLZOE tLZCE tBA tHZB tLZB (2) OE to High-Z Output OE to Low-Z Output CE to High-Z Output CE to Low-Z Output LB, UB Access Time LB, UB to High-Z Output LB, UB to Low-Z Output tHZCE(2) (2) Notes: 1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V, input pulse levels of 0.4 to 1.4V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B 08/07/02 5 IS62VV25616LL AC WAVEFORMS READ CYCLE NO. 1(1,2) (Address Controlled) (CE = OE = VIL, UB or LB = VIL) tRC ISSI ® ADDRESS tAA tOHA tOHA DATA VALID DOUT PREVIOUS DATA VALID AC WAVEFORMS READ CYCLE NO. 2(1,3) (CE, OE, AND UB/LB Controlled) tRC ADDRESS tAA tOHA OE tDOE tHZOE CE tLZCE tLZOE tACE tHZCE LB, UB tBA tHZB DATA VALID DOUT HIGH-Z tLZB Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE, UB, or LB = VIL. 3. Address is valid prior to or coincident with CE LOW transition. 6 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B 08/07/02 IS62VV25616LL WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range) -70 Symbol Parameter Write Cycle Time CE to Write End Address Setup Time to Write End Address Hold from Write End Address Setup Time LB, UB Valid to End of Write WE Pulse Width Data Setup to Write End Data Hold from Write End WE LOW to High-Z Output WE HIGH to Low-Z Output Min. 70 65 65 0 0 60 55 30 0 — 5 Max. — — — — — — — — — 30 — Min. 85 70 70 0 0 70 60 35 0 — 5 -85 ISSI Max. — — — — — — — — — 30 — Unit 1ns ns ns ns ns ns ns ns ns ns ns ® tWC tSCE tAW tHA tSA tPWB tPWE tSD tHD tHZWE(3) tLZWE (3) Notes: 1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V, input pulse levels of 0.4V to 1.4V and output loading specified in Figure 1. 2. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. 3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. AC WAVEFORMS WRITE CYCLE NO. 1(1,2) (CE Controlled, OE = HIGH or LOW) t WC ADDRESS VALID ADDRESS t SA CE t SCS t HA WE t AW t PWE1 t PWE2 t PBW UB, LB t HZWE DOUT DATA UNDEFINED HIGH-Z t LZWE t SD DIN t HD DATAIN VALID UB_CSWR1.eps Notes: 1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CE and WE inputs and at least one of the LB and UB inputs being in the LOW state. 2. WRITE = (CE) [ (LB) = (UB) ] (WE). Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B 08/07/02 7 IS62VV25616LL WRITE CYCLE NO. 2 (WE Controlled: OE is HIGH During Write Cycle) t WC ADDRESS VALID ADDRESS ISSI ® t HA OE CE LOW t AW t PWE1 WE t SA UB, LB t PBW t HZWE DOUT DATA UNDEFINED HIGH-Z t LZWE t SD DIN t HD DATAIN VALID UB_CSWR2.eps WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle) t WC ADDRESS OE CE VALID ADDRESS LOW t HA LOW t AW t PWE2 WE t SA UB, LB t PBW t HZWE DOUT DATA UNDEFINED HIGH-Z t LZWE t SD DIN t HD DATAIN VALID UB_CSWR3.eps 8 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B 08/07/02 IS62VV25616LL WRITE CYCLE NO. 4 (UB/LB Controlled) ISSI t WC t WC ADDRESS 2 ® ADDRESS ADDRESS 1 OE t SA CE LOW WE t HA t SA t PBW t PBW WORD 2 t HA UB, LB WORD 1 t HZWE DOUT HIGH-Z t LZWE t HD DATAIN VALID DATA UNDEFINED t SD DIN t SD DATAIN VALID t HD UB_CSWR4.eps DATA RETENTION SWITCHING CHARACTERISTICS Symbol Parameter Vdd for Data Retention Data Retention Current Data Retention Setup Time Recovery Time Test Condition See Data Retention Waveform VDD = 1.0V, CE ≥ VDD – 0.2V See Data Retention Waveform See Data Retention Waveform Min. 1.0 — 0 Max. 2.25 10 — — Unit V µA ns ns VDR IDR tSDR tRDR tRC DATA RETENTION WAVEFORM (CE Controlled) tSDR VDD 2.3V Data Retention Mode tRDR 2.0V VDR CE ≥ VDD Ð 0.2V CE GND Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B 08/07/02 9 IS62VV25616LL ISSI Package TSOP (Type II) MiniBGA (7.2mmx8.7mm) TSOP (Type II) MiniBGA (7.2mmx8.7mm) ® ORDERING INFORMATION Commercial Range: 0°C to +70°C Speed (ns) 70 85 Order Part No. IS62VV25616LL-70T IS62VV25616LL-70M IS62VV25616LL-85T IS62VV25616LL-85M Industrial Range: –40°C to +85°C Speed (ns) 70 85 Order Part No. IS62VV25616LL-70TI IS62VV25616LL-70MI IS62VV25616LL-85TI IS62VV25616LL-85MI Package TSOP (Type II) MiniBGA (7.2mmx8.7mm) TSOP (Type II) MiniBGA (7.2mmx8.7mm) 10 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B 08/07/02