IS62WV102416ALL-35MI

IS62WV102416ALL IS62WV102416BLL IS65WV102416BLL 1M x 16 HIGH-SPEED LOW POWER ASYNCHRONOUS CMOS STATIC RAM FEATURES • High-speed access times: 25, 35 ns • High-performance, low-power CMOS process • Multiple center power and ground pins for greater noise immunity • Easy memory expansion with CS1 and OE options • CS1 power-down • Fully static operation: no clock or refresh required • TTL compatible inputs and outputs • Single power supply Vdd 1.65V to 2.2V (IS62WV102416ALL) speed = 35ns for Vdd 1.65V to 2.2V Vdd 2.4V to 3.6V (IS62/65WV102416BLL) speed = 25ns for Vdd 2.4V to 3.6V • Packages available: – 48-ball miniBGA (9mm x 11mm) – 48-pin TSOP (Type I) • Industrial and Automotive Temperature Support • Lead-free available • Data control for upper and lower bytes APRIL 2015 DESCRIPTION The ISSI IS62WV102416ALL/BLL and IS65WV102416BLL are high-speed, 16M-bit static RAMs organized as 1024K words by 16 bits. It is fabricated using ISSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields high-performance and low power consumption devices. When CS1 is HIGH (deselected) or when CS2 is low (deselected) or when CS1 is low, CS2 is high and both LB and UB are HIGH, the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs. The active LOW Write Enable (WE) controls both writing and reading of the memory. A data byte allows Upper Byte (UB) and Lower Byte (LB) access. The device is packaged in the JEDEC standard 48-pin TSOP Type I and 48-pin Mini BGA (9mm x 11mm). FUNCTIONAL BLOCK DIAGRAM A0-A19 DECODER 1024K x 16 MEMORY ARRAY I/O DATA CIRCUIT COLUMN I/O VDD GND I/O0-I/O7 Lower Byte I/O8-I/O15 Upper Byte CS1 OE WE UB LB CONTROL CIRCUIT Copyright © 2015 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc. — www.issi.com 1 Rev. B 04/22/2015 IS62WV102416ALL IS62WV102416BLL IS65WV102416BLL 1Mx16 LOW POWER PIN CONFIGURATIONS 48-Pin mini BGA (9mmx11mm) 1 2 3 4 5 6 A LB OE A0 A1 A2 CS2 B I/O8 UB A3 A4 CS1 I/O0 C I/O9 I/O10 A5 A6 I/O1 I/O2 D GND I/O11 A17 A7 I/O3 VDD E VDD I/O12 NC A16 I/O4 GND F I/O14 I/O13 A14 A15 I/O5 I/O6 G I/O15 A19 A12 A13 WE I/O7 H A18 A8 A9 A10 A11 NC PIN DESCRIPTIONS 2 A0-A19 Address Inputs I/O0-I/O15 Data Inputs/Outputs CS1, CS2 Chip Enable Input OE Output Enable Input WE Write Enable Input LB Lower-byte Control (I/O0-I/O7) UB Upper-byte Control (I/O8-I/O15) NC No Connection Vdd Power GND Ground Integrated Silicon Solution, Inc. — www.issi.com Rev. B 04/22/2015 IS62WV102416ALL IS62WV102416BLL IS65WV102416BLL 48-pin TSOP-I (12mm x 20mm) A4 A3 A2 A1 A0 NC CS1 I/O0 I/O1 I/O2 I/O3 VDD GND I/O4 I/O5 I/O6 I/O7 WE NC A19 A18 A17 A16 A15 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 A5 A6 A7 A8 OE UB LB I/O15 I/O14 I/O13 I/O12 GND VDD I/O11 I/O10 I/O9 I/O8 NC A9 A10 A11 A12 A13 A14 PIN DESCRIPTIONS A0-A19 Address Inputs I/O0-I/O15 Data Inputs/Outputs CS1 Chip Enable Input OE Output Enable Input WE Write Enable Input LB Lower-byte Control (I/O0-I/O7) UB Upper-byte Control (I/O8-I/O15) NC No Connection Vdd Power GND Ground Integrated Silicon Solution, Inc. — www.issi.com 3 Rev. B 04/22/2015 IS62WV102416ALL IS62WV102416BLL IS65WV102416BLL TRUTH TABLE I/O PIN Mode WE CS1 CS2 OE LB UB I/O0-I/O7 I/O8-I/O15 Vdd Current Not Selected X H X X X X High-Z High-Z Isb1, Isb2 X X L X X X High-Z High-Z Isb1, Isb2 X X X X H H High-Z High-Z Isb1, Isb2 Output Disabled H L H H L X High-Z High-Z Icc H L H H X L High-Z High-Z Icc Read H L H L L H Dout High-Z Icc H L H L H L High-Z Dout H L H L L L Dout Dout Write L L H X L H Din High-Z Icc L L H X H L High-Z Din L L H X L L Din Din ABSOLUTE MAXIMUM RATINGS(1) Symbol Parameter Vterm Terminal Voltage with Respect to GND Vdd Vdd Relates to GND Tstg Storage Temperature Pt Power Dissipation Value Unit –0.5 to Vdd + 0.5 V –0.3 to 4.0 V –65 to +150 °C 1.0 W Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. CAPACITANCE(1,2) Symbol Cin CI/O Parameter Input Capacitance Input/Output Capacitance Conditions Vin = 0V Vout = 0V Max. 6 8 Unit pF pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: Ta = 25°C, f = 1 MHz, Vdd = 3.3V. 4 Integrated Silicon Solution, Inc. — www.issi.com Rev. B 04/22/2015 IS62WV102416ALL IS62WV102416BLL IS65WV102416BLL OPERATING RANGE (Vdd) (IS62WV102416ALL) Range Ambient Temperature Commercial 0°C to +70°C Industrial –40°C to +85°C Automotive –40°C to +125°C Vdd (35 ns) 1.65V-2.2V 1.65V-2.2V 1.65V-2.2V OPERATING RANGE (Vdd) (IS62WV102416BLL)(1) Range Ambient Temperature Commercial 0°C to +70°C Industrial –40°C to +85°C Vdd (25 ns) 2.4V-3.6V 2.4V-3.6V Note: 1. When operated in the range of 2.4V-3.6V, the device meets 10ns. OPERATING RANGE (Vdd) (IS65WV102416BLL) Range Ambient Temperature Automotive –40°C to +125°C Vdd (25 ns) 2.4V-3.6V Integrated Silicon Solution, Inc. — www.issi.com 5 Rev. B 04/22/2015 IS62WV102416ALL IS62WV102416BLL IS65WV102416BLL DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Vdd = 2.4V-3.6V Symbol Voh Vol Vih Vil Ili Ilo Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage(1) Input Leakage Output Leakage Test Conditions Vdd = Min., Ioh = –1.0 mA Vdd = Min., Iol = 1.0 mA GND ≤ Vin ≤ Vdd GND ≤ Vout ≤ Vdd, Outputs Disabled Min. Max. Unit 1.8 — V — 0.4 V 2.0 Vdd + 0.3 V –0.3 0.8 V –1 1 µA –1 1 µA Note: 1. Vil (min.) = –0.3V DC; Vil (min.) = –2.0V AC (pulse width < 10 ns). Not 100% tested. Vih (max.) = Vdd + 0.3V DC; Vih (max.) = Vdd + 2.0V AC (pulse width < 10 ns). Not 100% tested. DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Vdd = 1.65V-2.2V Symbol Voh Vol Vih Vil(1) Ili Ilo Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Output Leakage Test Conditions Vdd Min. Max. Unit Ioh = -0.1 mA 1.65-2.2V Vcc – 0.4V — V Iol = 0.1 mA 1.65-2.2V — 0.2 V 1.65-2.2V 1.4 Vdd + 0.2 V 1.65-2.2V –0.2 0.4 V GND ≤ Vin ≤ Vdd –1 1 µA GND ≤ Vout ≤ Vdd, Outputs Disabled –1 1 µA Notes: 1. Vil (min.) = –0.3V DC; Vil (min.) = –2.0V AC (pulse width < 10ns). Not 100% tested. Vih (max.) = Vdd + 0.3V DC; Vih (max.) = Vdd + 2.0V AC (pulse width < 10ns). Not 100% tested. 6 Integrated Silicon Solution, Inc. — www.issi.com Rev. B 04/22/2015 IS62WV102416ALL IS62WV102416BLL IS65WV102416BLL AC TEST CONDITIONS (HIGH SPEED) Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level (VRef) Output Load Unit Unit (2.4V-3.6V) (1.65V-2.2V) 0.4V to Vdd-0.3V 0.4V to Vdd-0.2V 1.5ns 1.5ns Vdd/2 Vdd/2 See Figures 1 and 2 See Figures 1 and 2 AC TEST LOADS 319 Ω ZO = 50Ω 3.3V 50Ω 1.5V OUTPUT 30 pF Including jig and scope Figure 1. Integrated Silicon Solution, Inc. — www.issi.com Rev. B 04/22/2015 OUTPUT 5 pF Including jig and scope 353 Ω Figure 2. 7 IS62WV102416ALL IS62WV102416BLL IS65WV102416BLL POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter Test Conditions Icc Vdd Dynamic Operating Vdd = Max., Com. Supply Current Iout = 0 mA, f = fmax Ind. Vin = 0.4V or Vdd –0.3V Auto. typ.(2) Icc1 Operating Vdd = Max., Com. Supply Current Iout = 0 mA, f = 0 Ind. Vin = 0.4V or Vdd –0.3V Auto. Isb1 TTL Standby Current Vdd = Max., Com. (TTL Inputs) Vin = Vih or Vil Ind. CS1 ≥ Vih, f = 0 Auto. Isb2 CMOS Standby Vdd = Max., Com. Current (CMOS Inputs) CS1 ≥ Vdd – 0.2V, Ind. Vin ≥ Vdd – 0.2V, or Auto. Vin ≤ 0.2V, f = 0 typ.(2) -25 Min. Max. — 30 — 35 — 60 25 — 20 — 30 — 50 — 15 — 20 — 40 — 0.8 — 1.2 — 2 0.1 -35 Min. Max. Unit — 25 mA — 30 — 60 — — — — — — — — — 20 30 50 15 20 40 0.8 1.2 2 mA mA mA Note: 1. At f = fmax, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. Typical values are measured at Vdd = 3.0V, Ta = 25oC and not 100% tested. 8 Integrated Silicon Solution, Inc. — www.issi.com Rev. B 04/22/2015 IS62WV102416ALL IS62WV102416BLL IS65WV102416BLL READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter trc Read Cycle Time 25 — 35 — ns taa Address Access Time — 25 — 35 ns toha Output Hold Time 3 — 3 — ns tacs1/tacs2 CS1/CS2 Access Time — 25 — 35 ns tdoe OE Access Time — 12 — 15 ns OE to High-Z Output — 8 — 10 ns OE to Low-Z Output 5 — 5 — ns thzcs1/thzcs2 CS1/CS2 to High-Z Output 0 8 0 10 ns tlzcs1/tlzcs2(2) CS1/CS2 to Low-Z Output 10 — 10 — ns tba LB, UB Access Time — 25 — 35 ns thzb LB, UB to High-Z Output 0 8 0 10 ns tlzb LB, UB to Low-Z Output 0 — 0 — ns thzoe(2) tlzoe (2) (2) 25 ns Min. Max. 35 ns Min. Max. Unit Notes: 1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V/1.5V, input pulse levels of 0.4 to Vdd-0.2V/0.4V to Vdd-0.3V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. AC WAVEFORMS READ CYCLE NO. 1(1,2) (Address Controlled) (CS1 = OE = Vil, CS2 = WE = Vih, UB or LB = Vil) tRC ADDRESS tAA tOHA DQ0-D15 PREVIOUS DATA VALID Integrated Silicon Solution, Inc. — www.issi.com Rev. B 04/22/2015 tOHA DATA VALID 9 IS62WV102416ALL IS62WV102416BLL IS65WV102416BLL AC WAVEFORMS READ CYCLE NO. 2(1,3) (CS1, CS2, OE, AND UB/LB Controlled) tRC ADDRESS tAA tOHA OE tHZOE tDOE CS1s tLZOE tACE1/tACE2 CS2s tLZCE1/ tLZCE2 tHZCS1/ tHZCS1 LBs, UBs tLZB DOUT tBA tHZB HIGH-Z DATA VALID Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CS1, UB, or LB = Vil. CS2=WE=Vih. 3. Address is valid prior to or coincident with CS1 LOW transition. 10 Integrated Silicon Solution, Inc. — www.issi.com Rev. B 04/22/2015 IS62WV102416ALL IS62WV102416BLL IS65WV102416BLL WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range) Symbol twc 25ns Min. Max. 25 — 35 ns Min. Max. 35 — Unit ns tscs1/tscs2 CS1/CS2 to Write End 18 — 25 — ns taw Address Setup Time to Write End 15 — 25 — ns tha Address Hold from Write End 0 — 0 — ns tsa Address Setup Time 0 — 0 — ns tpwb LB, UB Valid to End of Write 18 — 25 — ns tpwe WE Pulse Width 18 — 30 — ns tsd Data Setup to Write End 12 — 15 — ns (4) thd Parameter Write Cycle Time Data Hold from Write End 0 — 0 — ­ns (3) thzwe WE LOW to High-Z Output — 12 — 20 ns tlzwe WE HIGH to Low-Z Output 5 — 5 — ns (3) Notes: 1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V/1.5V, input pulse levels of 0.4 to Vdd-0.2V/0.4V to Vdd-0.3V and output loading specified in Figure 1. 2. The internal write time is defined by the overlap of CS1 LOW, CS2 HIGH and UB or LB, and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. 3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 4. tpwe > thzwe + tsd when OE is LOW. AC WAVEFORMS WRITE CYCLE NO. 1(1,2) (CS1 Controlled, OE = HIGH or LOW) tWC ADDRESS tHA tSCS1 CS1 tSCS2 CS2 tAW tPWE WE tPWB LB, UB tSA DOUT DATA UNDEFINED tHZWE tLZWE HIGH-Z tSD DIN tHD DATA-IN VALID Notes: 1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CS1 , CS2 and WE inputs and at least one of the LB and UB inputs being in the LOW state. 2. WRITE = (CS1) [ (LB) = (UB) ] (WE). Integrated Silicon Solution, Inc. — www.issi.com 11 Rev. B 04/22/2015 IS62WV102416ALL IS62WV102416BLL IS65WV102416BLL WRITE CYCLE NO. 2 (WE Controlled: OE is HIGH During Write Cycle) tWC ADDRESS OE tHA tSCS1 CS1 tSCS2 CS2 tAW t PWE WE LB, UB tSA DOUT tHZWE tLZWE HIGH-Z DATA UNDEFINED tSD DIN tHD DATA-IN VALID WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle) tWC ADDRESS OE tHA tSCS1 CS1 tSCS2 CS2 tAW t PWE WE LB, UB tSA DOUT DATA UNDEFINED tHZWE tLZWE HIGH-Z tSD DIN 12 tHD DATA-IN VALID Integrated Silicon Solution, Inc. — www.issi.com Rev. B 04/22/2015 IS62WV102416ALL IS62WV102416BLL IS65WV102416BLL WRITE CYCLE NO. 4 (UB/LB Controlled) t WC ADDRESS t WC ADDRESS 1 ADDRESS 2 OE t SA CS1 LOW CS2 HIGH t HA t SA WE UB, LB t HA t PBW t PBW WORD 1 WORD 2 t HZWE DOUT t LZWE HIGH-Z DATA UNDEFINED t HD t SD DIN DATAIN VALID t HD t SD DATAIN VALID UB_CSWR4.eps Integrated Silicon Solution, Inc. — www.issi.com 13 Rev. B 04/22/2015 IS62WV102416ALL IS62WV102416BLL IS65WV102416BLL DATA RETENTION SWITCHING CHARACTERISTICS  Symbol Parameter Test Condition Min. Vdr Vdd for Data Retention See Data Retention Waveform 1.2 3.6 V Idr Data Retention Current Vdd = 1.2V, CS1 ≥ Vdd – 0.2V Com. Ind. Auto. — — — 0.1 0.1 0.1 0.8 1.2 2 mA tsdr Data Retention Setup Time See Data Retention Waveform 0 — ns trdr Recovery Time trc — ns See Data Retention Waveform Typ.(1) Max. Unit Note: 1. Typical values are measured at Vdd = 3.0V, Ta = 25oC and not 100% tested. DATA RETENTION WAVEFORM (CS1 Controlled) Data Retention Mode tSDR tRDR VDD 1.65V 1.4V VDR CS1 ≥ VDD - 0.2V CS1 GND DATA RETENTION WAVEFORM (CS2 Controlled) Data Retention Mode 3.0 VDD CE2 2.2V tSDR tRDR VDR 0.4V CS2 ≤ 0.2V GND 14 Integrated Silicon Solution, Inc. — www.issi.com Rev. B 04/22/2015 IS62WV102416ALL IS62WV102416BLL IS65WV102416BLL ORDERING INFORMATION Industrial Range: -40°C to +85°C Voltage Range: 2.4V to 3.6V peed (ns) S 25 Order Part No. IS62WV102416BLL-25MI IS62WV102416BLL-25MLI IS62WV102416BLL-25TI IS62WV102416BLL-25TLI Package 48 mini BGA (9mm x 11mm) 48 mini BGA (9mm x 11mm), Lead-free TSOP (Type I) TSOP (Type I), Lead-free Industrial Range: -40°C to +85°C Voltage Range: 1.65V to 2.2V peed (ns) S 35 Order Part No. IS62WV102416ALL-35MI IS62WV102416ALL-35MLI IS62WV102416ALL-35TI IS62WV102416ALL-35TLI Package 48 mini BGA (9mm x 11mm) 48 mini BGA (9mm x 11mm), Lead-free TSOP (Type I) TSOP (Type I), Lead-free Automotive Range: -40°C to +125°C Voltage Range: 2.4V to 3.6V peed (ns) S 25 Order Part No. IS65WV102416BLL-25MA3 IS65WV102416BLL-25MLA3 IS65WV102416BLL-25CTA3 IS65WV102416BLL-25CTLA3 Package 48 mini BGA (9mm x 11mm) 48 mini BGA (9mm x 11mm), Lead-free TSOP (Type I) TSOP (Type I), Lead-free Integrated Silicon Solution, Inc. — www.issi.com 15 Rev. B 04/22/2015 16 Θ 07/06/2006 4. Formed leads shall be planar with respect to one another within 0.1mm at the seating plane after final test. 3. Dimension b does not include dambar protrusion/intrusion. 2. Dimension D1 adn E do not include mold protrusion . 1. Controlling dimension : mm NOTE : Θ IS62WV102416ALL IS62WV102416BLL IS65WV102416BLL PACKAGE INFORMATION Integrated Silicon Solution, Inc. — www.issi.com Rev. B 04/22/2015 Integrated Silicon Solution, Inc. — www.issi.com Rev. B 04/22/2015 1. CONTROLLING DIMENSION : MM . 2. Reference document : JEDEC MO-207 NOTE : 08/21/2008 IS62WV102416ALL IS62WV102416BLL IS65WV102416BLL 17