IS62WV102416DBLL-55TLI

IS62/65WV102416DALL IS62/65WV102416DBLL JANUARY 2015 1Mx16 LOW VOLTAGE, ULTRA LOW POWER & LOW POWER CMOS STATIC RAM KEY FEATURES       DESCRIPTION High-speed access time: 45ns, 55ns. CMOS low power operation – 25 µA (typical) CMOS standby CMOS for optimum speed and power and TTL compatible interface levels Single power supply – 1.65V~1.98V VDD (IS62/65WV102416DALL) – 2.2V~3.6V VDD (IS62/65WV102416DBLL) Fully static operation: no clock or refresh required Industrial and Automotive temperature support The ISSI IS62/65WV102416DALL, IS62/65WV102416DBLL are ULTRA LOW POWER CMOS 16Mbit static RAMs organized as 1M words by 16 bits. It is fabricated using ISSI's highperformance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields high-performance and low power consumption devices. The IS62WV102416DALL/ DBLL and IS65WV102416DALL/DBLL are packaged in 48-Pin TSOP (TYPE I). BLOCK DIAGRAM DECODER A0-19 MEMORY ARRAY (1024KX16) (2048KX8) A20 COLUMN I/O I/O0-7 I/O8-14 I/O15 IO15 CONTROL CIRCUIT , CS2 Copyright © 2014 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc.- www.issi.com Rev. A 12/12/2014 1 IS62/65WV102416DALL IS62/65WV102416DBLL 48-PIN TSOP-I A15 A14 A13 A12 A11 A10 A9 A8 A19 NC CS2 NC A18 A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 Vss I/O15/A20 I/O7 I/O14 I/O6 I/O13 I/O5 I/O12 I/O4 Vcc I/O11 I/O3 I/O10 I/O2 I/O9 I/O1 I/O8 I/O0 Vss A0 PIN DESCRIPTIONS A0-A19 I/O0-I/O14 I/O15/A20 , CS2 NC VDD Vss Address Inputs Data Inputs/Outputs, I/O8 to I/O14 pins are not used in x8 Mode. I/O15, when used in a x16 Mode. A20 when used in a x8 Mode, Chip Enable Input Output Enable Input Write Enable Input Lower-byte Control (I/O0-I/O7). This pin is not used in x8 Mode. Upper-byte Control (I/O8-I/O15). This pin is not used in x8 Mode. pin must be tied to either VDD to use the device as a 1024Kx16 SRAM or GND to use as 2048Kx8 SRAM. In x8 mode, Pin 45 becomes A20, while , and I/O8 to I/O14 pins are not used. No Connection Power Ground *For x8/x16 switchable configuration BGA option, please contact sram@issi.com Integrated Silicon Solution, Inc.- www.issi.com Rev. A 12/12/2014 2 IS62/65WV102416DALL IS62/65WV102416DBLL FUNCTION DESCRIPTION SRAM is one of random access memories. Each byte or word has an address and can be accessed randomly. SRAM has three different modes supported. Each function is described below with Truth Table. STANDBY MODE Device enters standby mode when deselected ( HIGH or CS2 LOW or both and are HIGH). The input and output pins (I/O0-15) are placed in a high impedance state. The current consumption in this mode will be either ISB1 or ISB2 depending on the input level. CMOS input in this mode will maximize saving power. WRITE MODE Write operation issues with Chip selected ( LOW and CS2 HIGH) and Write Enable ( ) input LOW. The input and output pins(I/O0-15) are in data input mode. Output buffers are closed during this time even if is LOW. and enables a byte write feature. By enabling LOW, data from I/O pins (I/O0 through I/O7) are written into the location specified on the address pins. And with being LOW, data from I/O pins (I/O8 through I/O15) are written into the location. READ MODE Read operation issues with Chip selected ( LOW and CS2 HIGH) and Write Enable ( ) input HIGH. When is LOW, output buffer turns on to make data output. Any input to I/O pins during READ mode is not permitted. and enables a byte read feature. By enabling LOW, data from memory appears on I/O0-7. And with being LOW, data from memory appears on I/O8-15. In the READ mode, output buffers can be turned off by pulling HIGH. In this mode, internal device operates as READ but I/Os are in a high impedance state. Since device is in READ mode, active current is used. TRUTH TABLE Mode Not Selected Output Disabled Read Write CS2 H X X L L L L L L L L X L X H H H H H H H H X X X H H H H H L L L Integrated Silicon Solution, Inc.- www.issi.com Rev. A 12/12/2014 X X X H H L L L X X X X X H L X L H L L H L X X H X L H L L H L L I/O0-I/O7 I/O8-I/O15 High-Z High-Z High-Z High-Z High-Z DOUT High-Z DOUT DIN High-Z DIN High-Z High-Z High-Z High-Z High-Z High-Z DOUT DOUT High-Z DIN DIN VDD Current ISB1,ISB2 ICC ICC ICC 3 IS62/65WV102416DALL IS62/65WV102416DBLL ABSOLUTE MAXIMUM RATINGS AND OPERATING RANGE ABSOLUTE MAXIMUM RATINGS(1) Symbol Vter m tBIAS VDD tStg Parameter Terminal Voltage with Respect to GND Temperature Under Bias V DD Related to GND Storage Temperature Value –0.2 to +3.9(VDD+0.3V) –55 to +125 –0.2 to +3.9(VDD+0.3V) –65 to +150 IOUT DC Output Current (LOW) 20 Unit V C V C mA Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. OPERATING RANGE(1) Range Commercial Industrial Automotive Commercial Industrial Automotive Device Marking IS62WV102416DALL IS62WV102416DALL IS65WV102416DALL IS62WV102416DBLL IS62WV102416DBLL IS65WV102416DBLL Ambient Temperature 0C to +70C -40C to +85C -40C to +125C 0C to +70C -40C to +85C -40C to +125C VDD (min) 1.65V 1.65V 1.65V 2.2V 2.2V 2.2V VDD (typ) 1.8V 1.8V 1.8V 3.3V 3.3V 3.3V VDD (max) 1.98V 1.98V 1.98V 3.6V 3.6V 3.6V Note: 1. Full device AC operation assumes a 100 µs ramp time from 0 to Vcc(min) and 200 µs wait time after Vcc stabilization. PIN CAPACITANCE (1) Parameter Input capacitance DQ capacitance (IO0–IO15) Symbol CIN CI/O Test Condition TA = 25°C, f = 1 MHz, VDD = VDD(typ) Max 10 10 Units pF pF Note: 1. These parameters are guaranteed by design and tested by a sample basis only. THERMAL CHARACTERISTICS (1) Parameter Thermal resistance from junction to ambient (airflow = 1m/s) Thermal resistance from junction to case Symbol RθJA RθJC Rating 43.8 7.7 Units °C/W °C/W Note: 1. These parameters are guaranteed by design and tested by a sample basis only. Integrated Silicon Solution, Inc.- www.issi.com Rev. A 12/12/2014 4 IS62/65WV102416DALL IS62/65WV102416DBLL ELECTRICAL CHARACTERISTICS IS62(5)WV102416DALL DC ELECTRICAL CHARACTERISTICS-I (OVER THE OPERATING RANGE) Symbol VOH VOL VIH(1) VIL(1) ILI ILO Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Output Leakage Test Conditions IOH = -0.1 mA IOL = 0.1 mA GND < VIN < VDD GND < VIN < VDD, Output Disabled Min. 1.4 — 1.4 –0.2 –1 –1 Max. — 0.2 VDD + 0.2 0.4 1 1 Unit V V V V µA µA Notes: 1. VILL(min) = -1.0V AC (pulse width < 10ns). Not 100% tested. VIHH (max) = VDD + 1.0V AC (pulse width < 10ns). Not 100% tested. IS62(5)WV102416DBLL DC ELECTRICAL CHARACTERISTICS-I (OVER THE OPERATING RANGE) Symbol VOH Parameter Output HIGH Voltage VOL Output LOW Voltage VIH(1) Input HIGH Voltage VIL(1) Input LOW Voltage ILI ILO Input Leakage Output Leakage Test Conditions 2.2 ≤ VDD < 2.7, IOH = -0.1 mA 2.7 ≤ VDD ≤ 3.6, IOH = -1.0 mA 2.2 ≤ VDD < 2.7, IOL = 0.1 mA 2.7 ≤ VDD ≤ 3.6, IOL = 2.1 mA 2.2 ≤ VDD < 2.7 2.7 ≤ VDD ≤ 3.6 2.2 ≤ VDD < 2.7 2.7 ≤ VDD ≤ 3.6 GND < VIN < VDD GND < VIN < VDD, Output Disabled Min. 2.0 2.4 — — 1.8 2.2 –0.3 –0.3 –1 –1 Max. — — 0.4 0.4 VDD + 0.3 VDD + 0.3 0.6 0.8 1 1 Unit V V V V V V V V µA µA Notes: 1. VILL(min) = -2.0V AC (pulse width < 10ns). Not 100% tested. VIHH (max) = VDD + 2.0V AC (pulse width < 10ns). Not 100% tested. Integrated Silicon Solution, Inc.- www.issi.com Rev. A 12/12/2014 5 IS62/65WV102416DALL IS62/65WV102416DBLL IS62(5)WV102416DALL DC ELECTRICAL CHARACTERISTICS-II FOR POWER (OVER THE OPERATING RANGE) Symbol ICC ICC1 ISB1 Parameter VDD Dynamic Operating Supply Current VDD Static Operating Supply Current CMOS Standby Current (CMOS Inputs) Test Conditions VDD=VDD(max), IOUT=0mA, f=fMAX VDD=VDD(max), IOUT = 0mA, f=0Hz VDD=VDD(max), (1) 0V ≤ CS2 ≤ 0.2V or (2) ≥ VDD - 0.2V, CS2 ≥ VDD - 0.2V or (3) and ≥ VDD- 0.2V ≤ 0.2V, CS2 ≥ VDD - 0.2V Grade Com. Ind. Auto. Com. Ind. Auto. Com. Typ. 6 3 25 Max. 12 12 12 6 6 6 50 Unit mA Ind. - 65 µA Auto. - 165 µA mA µA Note: Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VDD = VDD(typ), TA = 25C IS62(5)WV102416DBLL DC ELECTRICAL CHARACTERISTICS-II FOR POWER (OVER THE OPERATING RANGE) Symbol ICC ICC1 ISB1 Parameter VDD Dynamic Operating Supply Current VDD Static Operating Supply Current CMOS Standby Current (CMOS Inputs) Test Conditions VDD=VDD(max), IOUT=0mA, f=fMAX VDD=VDD(max), IOUT = 0mA, f=0Hz VDD=VDD(max), (1) 0V ≤ CS2 ≤ 0.2V or (2) ≥ VDD - 0.2V, CS2 ≥ VDD - 0.2V or (3) and ≥ VDD- 0.2V ≤ 0.2V, CS2 ≥ VDD - 0.2V Grade Com. Ind. Auto. Com. Ind. Auto. Com. Typ. 6 3 25 Max. 12 12 12 6 6 6 50 Unit mA Ind. - 65 µA Auto. - 165 µA mA µA Note: Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VDD = VDD(typ), TA = 25℃ Integrated Silicon Solution, Inc.- www.issi.com Rev. A 12/12/2014 6 IS62/65WV102416DALL IS62/65WV102416DBLL AC CHARACTERISTICS(6) (OVER OPERATING RANGE) READ CYCLE AC CHARACTERISTICS Parameter Symbol Read Cycle Time Address Access Time Output Hold Time tRC tAA tOHA tACS1/tACS2 tDOE tHZOE tLZOE tHZCS//tHZCS2 tLZCS/tLZCS2 tBA tHZB tLZB , CS2 Access Time Access Time to High-Z Output to Low-Z Output , CS2 to High-Z Output , CS2 to Low-Z Output , Access Time , to High-Z Output , to Low-Z Output 45ns Min 45 8 5 10 10 55ns Max 45 45 22 18 18 45 18 - Min 55 8 5 10 10 Max 55 55 25 18 18 55 18 - unit notes ns ns ns ns ns ns ns ns ns ns ns ns 1,5 1 1 1 1 2 2 2 2 1 2 2 unit notes ns ns ns ns ns ns ns ns ns ns ns 1,3,5 1,3 1,3 1,3 1,3 1,3 1,3,4 1,3 1,3 2,3 2,3 WRITE CYCLE AC CHARACTERISTICS Parameter Symbol Write Cycle Time tWC tSCS1/tSCS2 tAW tHA tSA tPWB tPWE tSD tHD tHZWE tLZWE ,CS2 to Write End Address Setup Time to Write End Address Hold from Write End Address Setup Time ,/ Valid to End of Write Pulse Width Data Setup to Write End Data Hold from Write End LOW to High-Z Output HIGH to Low-Z Output 45ns Min 45 35 35 0 0 35 35 28 0 10 55ns Max 18 - Min 55 40 40 0 0 40 40 28 0 10 Max 18 - Notes: 1. Tested with the load in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. tHZOE, tHZCS, tHZB, and tHZWE transitions are measured when the output enters a high impedance state. Not 100% tested. 3. The internal write time is defined by the overlap of =LOW, CS2=HIGH, ( or )=LOW, and =LOW. All four conditions must be in valid states to initiate a Write, but any condition can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. 4. tPWE > tHZWE + tSD when OE is LOW. 5. Address inputs must meet VIH and VIL SPEC during this period. Any glitch or unknown inputs are not permitted. Unknown input with standby mode is acceptable. 6. Data retention characteristics are defined later in DATA RETENTION CHARACTERISTICS. Integrated Silicon Solution, Inc.- www.issi.com Rev. A 12/12/2014 7 IS62/65WV102416DALL IS62/65WV102416DBLL AC TEST CONDITIONS (OVER THE OPERATING RANGE) Parameter Input Rise Time Input Fall Time Output Timing Reference Level Output Load Conditions Symbol TR TF VREF Conditions 1.0 1.0 ½ VTM Refer to Figure 1 and 2 Units V/ns V/ns V OUTPUT LOAD CONDITIONS FIGURES Figure1 Figure2 R1 R1 VTM VTM OUTPUT OUTPUT 30pF, including jig and scope Parameters R1 R2 VTM R2 VDD=1.65~1.98V 13500Ω 10800Ω VDD Integrated Silicon Solution, Inc.- www.issi.com Rev. A 12/12/2014 5pF, including jig and scope VDD=2.2~2.7V 16667Ω 15385Ω VDD R2 VDD=2.7~3.6V 1103Ω 1554Ω VDD 8 IS62/65WV102416DALL IS62/65WV102416DBLL TIMING DIAGRAM READ CYCLE NO. 1(1,2) (ADDRESS CONTROLLED) ( = =VIL, CS2= =VIH) tRC ADDRESS tAA tOHA tOHA I/O0-15 PREVIOUS DATA VALID READ CYCLE NO. 2(1,3) ( , CS2, Low-Z , AND & DATA VALID Low-Z CONTROLLED) tRC ADDRESS tAA tOHA tHZOE tDOE tLZOE tACS1/tACS2 CS2 tLZCS1/ tLZCS2 tHZCS1/ tHZCS2 , tBA tHZB tLZB I/O0-15 Notes: 1. is HIGH for Read Cycle. 2. The device is continuously selected. , 3. Address is valid prior to or coincident with HIGH-Z , , or =VIL.CS2= LOW transition. Integrated Silicon Solution, Inc.- www.issi.com Rev. A 12/12/2014 DATA VALID LOW-Z =VIH. 9 IS62/65WV102416DALL IS62/65WV102416DBLL WRITE CYCLE NO. 1 ( CONTROLLED, = HIGH OR LOW) tWC ADDRESS tSCS1 tHA tSCS2 CS2 tAW tPWE tPWB , tHZWE tSA DOUT DATA UNDEFINED tLZWE (1) tSD DIN DATA UNDEFINED(2) tHD DATA VALID Notes: 1. tHZWE is based on the assumption when tSA=0nS after READ operation. Actual DOUT for tHZWE may not appear if Write Cycle. tHZOE is the time DOUT goes to High-Z after goes high. 2. During this period the I/Os are in output state. Do not apply input signals. WRITE CYCLE NO. 2 ( CONTROLLED: goes high before IS HIGH DURING WRITE CYCLE) tWC ADDRESS tSCS1 tHA tSCS2 CS2 tAW tPWE tPWB , tHZWE tSA DOUT DATA UNDEFINED (1) tLZWE HIGH-Z tSD DIN DATA UNDEFINED (2) tHD DATA VALID Notes: 1. tHZWE is based on the assumption when tSA=0nS after READ operation. Actual DOUT for tHZWE may not appear if Write Cycle. tHZOE is the time DOUT goes to High-Z after goes high. 2. During this period the I/Os are in output state. Do not apply input signals. Integrated Silicon Solution, Inc.- www.issi.com Rev. A 12/12/2014 goes high before 10 IS62/65WV102416DALL IS62/65WV102416DBLL WRITE CYCLE NO. 3 ( CONTROLLED: IS LOW DURING WRITE CYCLE) tWC ADDRESS (1) LOW tHA tSCS1 tSCS2 CS2 tAW tPWE tPWB , tSA DOUT DATA UNDEFINED tLZWE tHZWE (1) HIGH-Z tSD DIN DATA UNDEFINED (1) tHD DATA VALID Notes: 1. If is low during write cycle, tHZWE must be met in the application. Do not apply input signal during this period. Data output from the previous READ operation will drive IO BUS. Integrated Silicon Solution, Inc.- www.issi.com Rev. A 12/12/2014 11 IS62/65WV102416DALL IS62/65WV102416DBLL WRITE CYCLE NO. 4 ( & CONTROLLED) tWC tWC ADDRESS (2) tSA LOW HIGH CS2 tHA tHA tSA (3) tPWB tPWB , tLZWE tHZWE DOUT DATA UNDEFINED (1) tHD DIN tHD tSD tSD DATA VALID DATA VALID Notes: 1. If is low during write cycle, tHZWE must be met in the application. Do not apply input signal during this period. Data output from the previous READ operation will drive IO BUS. 2. Due to the restriction of note1, is recommended to be HIGH during write period. 3. Note stays LOW in this example. If toggles, tPWE and tHZWE must be considered. Integrated Silicon Solution, Inc.- www.issi.com Rev. A 12/12/2014 12 IS62/65WV102416DALL IS62/65WV102416DBLL DATA RETENTION CHARACTERISTICS Symbol Parameter Test Condition OPTION VDR VDD for Data Retention See Data Retention Waveform IS62(5)WV102416DALL IS62(5)WV102416DBLL Data Retention Current VDD= VDR(min), (1) 0V ≤ CS2 ≤ 0.2V, or (2) ≥ VDD – 0.2V, CS2 ≥ VDD - 0.2V (3) and ≥ VDD -0.2V, ≤ 0.2V, CS2 ≥ VDD - 0.2V See Data Retention Waveform IDR tSDR Data Retention Setup Time tRDR Recovery Time Min. Typ. Max. Unit 1.5 - V 1.5 - V uA Com. - - 50 Ind. - - 65 Auto - - 165 0 - - ns tRC - - ns See Data Retention Waveform Note: Typical values are measured at VDD=VDR(min), TA = 25℃ and not 100% tested. DATA RETENTION WAVEFORM ( CONTROLLED) tSDR DATA RETENTION MODE tRDR VDD VDR CS1 > VDD-0.2V GND DATA RETENTION WAVEFORM (CS2 CONTROLLED) DATA RETENTION MODE VDD CS2 tSDR tRDR VDR CS2 < 0.2V GND Integrated Silicon Solution, Inc.- www.issi.com Rev. A 12/12/2014 13 IS62/65WV102416DALL IS62/65WV102416DBLL ORDERING INFORMATION 1.65V~1.98V Industrial Range (-40C to +85C) Speed (ns) 55 Order Part No IS62WV102416DALL-55TI IS62WV102416DALL-55TLI Package 48pin TSOP (Type I) 48pin TSOP (Type I), Lead-free 1.65V~1.98V Automotive (A3) Range (-40C to +125C) Speed (ns) 55 Order Part No IS65WV102416DALL-55TA3 IS65WV102416DALL-55TLA3 Package 48pin TSOP (Type I) 48pin TSOP (Type I), Lead-free 2.2V~3.6V Industrial Range (-40C to +85C) Speed (ns) 45 55 Order Part No IS62WV102416DBLL-45TI IS62WV102416DBLL-45TLI IS62WV102416DBLL-55TLI Package 48pin TSOP (Type I) 48pin TSOP (Type I), Lead-free 48pin TSOP (Type I), Lead-free 2.2V~3.6V Automotive (A3) Range (-40C to +125C) Speed (ns) 55 Order Part No IS65WV102416DBLL-55CTA3 IS65WV102416DBLL-55CTLA3 Integrated Silicon Solution, Inc.- www.issi.com Rev. A 12/12/2014 Package 48pin TSOP (Type I), Copper Leadframe 48pin TSOP (Type I), Lead-free, Copper Leadframe 14 IS62/65WV102416DALL IS62/65WV102416DBLL Integrated Silicon Solution, Inc.- www.issi.com Rev. A 12/12/2014 15