IS62WV10248BLL-70XI

IS62WV10248BLL 1M x 8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM FEATURES • High-speed access time: 55ns, 70ns • CMOS low power operation: 36 mW (typical) operating 12 µW (typical) CMOS standby • TTL compatible interface levels • Single power supply: 2.5V--3.6V VDD (IS62WV10248BLL) • Fully static operation: no clock or refresh required • Three state outputs • Industrial temperature available • Lead-free available ISSI MARCH 2006 ® DESCRIPTION The ISSI IS62WV10248BLL is a high-speed, 8M bit static RAMs organized as 1M words by 8 bits. It is fabricated using ISSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields high-performance and low power consumption devices. When CS1 is HIGH (deselected) or when CS2 is LOW (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs. The active LOW Write Enable (WE) controls both writing and reading of the memory. The IS62WV10248BLL is packaged in the JEDEC standard 48-pin mini BGA (7.2mm x 8.7mm). FUNCTIONAL BLOCK DIAGRAM A0-A19 DECODER 1M x 8 MEMORY ARRAY VDD GND I/O DATA CIRCUIT I/O0-I/O7 COLUMN I/O CS2 CS1 OE WE Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. CONTROL CIRCUIT Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. C 03/17/06 1 IS62WV10248BLL ISSI ® PIN DESCRIPTIONS A0-A19 CS1 CS2 OE WE I/O0-I/O7 NC VDD GND Address Inputs Chip Enable 1 Input Chip Enable 2 Input Output Enable Input Write Enable Input Input/Output No Connection Power Ground PIN CONFIGURATION 48-pin mini BGA (B) (7.2mm x 8.7mm) 1 A B C D E F G H NC 2 OE 3 A0 4 A1 5 A2 6 CS2 NC NC A3 A4 CS1 NC I/O0 NC A5 A6 NC I/O4 GND I/O1 A17 A7 I/O5 VDD VDD I/O2 NC A16 I/O6 GND I/O3 NC A14 A15 NC I/O7 NC NC A12 A13 WE NC A18 A8 A9 A10 A11 A19 2 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. C 03/17/06 IS62WV10248BLL ISSI CS1 H X L L L CS2 X L H H H OE X X H L X I/O Operation High-Z High-Z High-Z DOUT DIN VDD Current ISB1, ISB2 ISB1, ISB2 ICC ICC ICC ® TRUTH TABLE Mode Not Selected (Power-down) Output Disabled Read Write WE X X H H L ABSOLUTE MAXIMUM RATINGS(1) Symbol VTERM VDD TSTG PT Parameter Terminal Voltage with Respect to GND VDD Related to GND Storage Temperature Power Dissipation Value –0.2 to VDD+0.3 –0.2 to +3.8 –65 to +150 1.0 Unit V V °C W Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. OPERATING RANGE (VDD) Range Commercial Industrial Ambient Temperature 0°C to +70°C –40°C to +85°C IS62WV10248BLL 2.5V - 3.6V 2.5V - 3.6V DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Symbol VOH VOL VIH VIL(1) ILI ILO Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Output Leakage GND ≤ VIN ≤ VDD GND ≤ VOUT ≤ VDD, Outputs Disabled Test Conditions IOH = -1 mA IOL = 2.1 mA VDD 2.5-3.6V 2.5-3.6V 2.5-3.6V 2.5-3.6V Min. 2.2 — 2.2 –0.2 –1 –1 Max. — 0.4 VDD + 0.3 0.6 1 1 Unit V V V V µA µA Notes: 1. VIL (min.) = –1.0V for pulse width less than 10 ns. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. C 03/17/06 3 IS62WV10248BLL ISSI Conditions VIN = 0V VOUT = 0V Max. 8 10 Unit pF pF ® CAPACITANCE(1) Symbol CIN COUT Parameter Input Capacitance Input/Output Capacitance Note: 1. Tested initially and after any design or process changes that may affect these parameters. AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load IS62WV10248BLL (Unit) 0.4 to VDD-0.3V 5 ns VREF See Figures 1 and 2 IS62WV10248BLL 2.5V - 3.6V R1(Ω) R2(Ω) VREF VTM 1029 1728 1.5V 2.8V AC TEST LOADS R1 VTM VTM R1 OUTPUT 30 pF Including jig and scope R2 OUTPUT 5 pF Including jig and scope R2 Figure 1 Figure 2 4 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. C 03/17/06 IS62WV10248BLL ISSI Test Conditions VDD = Max., IOUT = 0 mA, f = fMAX VDD = Max., CS1 = 0.2V WE = VDD -0.2V CS2 = VDD -0.2V, f = 1MHz VDD = Max., VIN = VIH or VIL CS1 = VIH , CS2 = VIL, f = 1 MHZ VDD = Max., CS1 ≥ VDD – 0.2V, CS2 ≤ 0.2V, VIN ≥ VDD – 0.2V, or VIN ≤ 0.2V, f = 0 Com. Ind. Com. Ind. Com. Ind. Max. 55 30 35 5 5 0.3 0.3 Max. 70 25 30 5 5 0.3 0.3 Unit mA mA ® POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) IS62WV10248BLL Symbol Parameter ICC ICC1 VDD Dynamic Operating Supply Current Operating Supply Current TTL Standby Current (TTL Inputs) ISB1 mA ISB2 CMOS Standby Current (CMOS Inputs) Com. Ind. typ.(1) 20 25 3 20 25 3 µA Note: 1. Typical Values are measured at VDD = 3.0V, TA = 25oC and not 100% tested. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. C 03/17/06 5 IS62WV10248BLL READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter Read Cycle Time Address Access Time Output Hold Time CS1/CS2 Access Time OE Access Time (2) ISSI 55 ns Min. Max. 55 — 10 — — — 5 0 10 — 55 — 55 25 20 — 20 — 70 ns Min. Max. 70 — 10 — — — 5 0 10 — 70 — 70 35 25 — 25 — Unit ns ns ns ns ns ns ns ns ns ® tRC tAA tOHA tACS1/tACS2 tDOE tHZOE tLZOE(2) tHZCS1/tHZCS2 tLZCS1/tLZCS2 (2) (2) OE to High-Z Output OE to Low-Z Output CS1/CS2 to High-Z Output CS1/CS2 to Low-Z Output Notes: 1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0.4V to VDD-0.3V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. AC WAVEFORMS READ CYCLE NO. 1(1,2) (Address Controlled) (CS1 = OE = VIL, CS2 = WE = VIH) tRC ADDRESS tAA tOHA tOHA DATA VALID DOUT PREVIOUS DATA VALID 6 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. C 03/17/06 IS62WV10248BLL AC WAVEFORMS READ CYCLE NO. 2(1,3) (CS1, CS2, OE Controlled) tRC ISSI ® ADDRESS tAA tOHA OE tDOE tHZOE CS1 tACS1/tACS2 tLZOE CS2 tLZCS1/ tLZCS2 HIGH-Z tHZCS DATA VALID DOUT Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CS1= VIL. CS2=WE=VIH. 3. Address is valid prior to or coincident with CS1 LOW and CS2 HIGH transition. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. C 03/17/06 7 IS62WV10248BLL ISSI 55 ns Min. Max. 55 45 45 0 0 40 25 0 — 5 — — — — — — — — 25 — 70 ns Min. Max. 70 60 60 0 0 50 30 0 — 5 — — — — — — — — 25 — Unit ns ns ns ns ns ns ns ns ns ns ® WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range) Symbol Parameter Write Cycle Time tWC tSCS1/tSCS2 CS1/CS2 to Write End tAW Address Setup Time to Write End tHA tSA tPWE tSD (4) Address Hold from Write End Address Setup Time WE Pulse Width Data Setup to Write End Data Hold from Write End WE LOW to High-Z Output WE HIGH to Low-Z Output tHD tHZWE(3) tLZWE Notes: (3) 1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0.4V to VDD0.3V and output loading specified in Figure 1. 2. The internal write time is defined by the overlap of CS1 LOW, CS2 HIGH and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. 3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 4. tPWE > tHZWE + tSD when OE is LOW. AC WAVEFORMS WRITE CYCLE NO. 1 (CS1/CS2 Controlled, OE = HIGH or LOW) tWC ADDRESS tSCS1 tHA CS1 tSCS2 CS2 tAW tPWE tSA tHZWE HIGH-Z WE tLZWE DOUT DATA UNDEFINED tSD tHD DIN DATA-IN VALID 8 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. C 03/17/06 IS62WV10248BLL ISSI tWC ® WRITE CYCLE NO. 2 (WE Controlled: OE is HIGH During Write Cycle) ADDRESS OE tSCS1 tHA CS1 tSCS2 CS2 tAW tPWE tSA tHZWE HIGH-Z WE tLZWE DOUT DATA UNDEFINED tSD tHD DIN DATA-IN VALID WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle) tWC ADDRESS OE tSCS1 tHA CS1 tSCS2 CS2 tAW tPWE tSA tHZWE HIGH-Z WE tLZWE DOUT DATA UNDEFINED tSD tHD DIN DATA-IN VALID Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. C 03/17/06 9 IS62WV10248BLL ISSI Test Condition See Data Retention Waveform VDD = 1.2V, CS1 ≥ VDD – 0.2V See Data Retention Waveform See Data Retention Waveform Min. 1.2 — 0 tRC Max. 3.6 20 — — Unit V µA ns ns ® DATA RETENTION SWITCHING CHARACTERISTICS Symbol VDR IDR tSDR tRDR Parameter VDD for Data Retention Data Retention Current Data Retention Setup Time Recovery Time DATA RETENTION WAVEFORM (CS1 Controlled) tSDR VDD 3.0V Data Retention Mode tRDR 2.2V VDR CS1 ≥ VDD CS1 GND - 0.2V DATA RETENTION WAVEFORM (CS2 Controlled) Data Retention Mode VDD 3.0 CS2 2.2V VDR 0.4V GND CS2 ≤ 0.2V tSDR tRDR 10 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. C 03/17/06 IS62WV10248BLL ISSI ® ORDERING INFORMATION: IS62WV10248BLL (2.5V - 3.6V) Industrial Range: –40°C to +85°C Speed (ns) 55 70 70 Order Part No. IS62WV10248BLL-55BI IS62WV10248BLL-55BLI IS62WV10248BLL-70BI IS62WV10248BLL-70XI Package mini BGA (7.2mm x 8.7mm) mini BGA (7.2mm x 8.7mm), Lead-free mini BGA (7.2mm x 8.7mm) DIE Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. C 03/17/06 11 IS62WV10248BLL Mini Ball Grid Array Package Code: B (48-pin) Top View 1 2 3 4 56 6 Bottom View φ b (48x) ISSI ® 5 4 3 2 1 A B C D D E F G H D1 e A B C D E F G H e E E1 A2 SEATING PLANE A1 A mBGA - 7.2mm x 8.7mm MILLIMETERS Sym. N0. Leads A A1 A2 D D1 E E1 e b 7.10 — 0 .24 0.60 8.60 INCHES Min. Typ. Max. Notes: 1. Controlling dimensions are in millimeters. Min. Typ. Max. 48 — — — 8.70 5.25BSC 7.20 7.30 3.75BSC 0.75BSC 0.30 0.35 0.40 1.20 0.30 — 8.80 — 0.009 0.024 — — — 0.047 0.012 — 0.339 0.343 0.346 0.207BSC 0.280 0.283 0.287 0.148BSC 0.030BSC 0.012 0.014 0.016 12 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. C 03/17/06