IS62WV12816EBLL-45BLI-TR

IS62WV12816EALL IS62/65WV12816EBLL MAY 2017 128Kx16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM KEY FEATURES   DESCRIPTION High-speed access time: 45ns, 55ns CMOS low power operation – Operating Current: 18 mA (max) at 85°C – CMOS Standby Current: 5.4uA (typ) at 25°C      TTL compatible interface levels Single power supply –1.65V-2.2V VDD (IS62WV12816EALL) – 2.2V-3.6V VDD (IS62/65WV12816EBLL) Three state outputs Industrial and Automotive temperature support Lead-free available The ISSI IS62/65WV12816EALL/EBLL are high-speed, 2M bit static RAMs organized as 128K words by 16 bits. It is fabricated using ISSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields high-performance and low power consumption devices. When CS1# is HIGH (deselected) or when CS2 is LOW (deselected) or when CS1# is LOW, CS2 is HIGH and both LB# and UB# are HIGH, the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs. The active LOW Write Enable (WE#) controls both writing and reading of the memory. A data byte allows Upper Byte (UB#) and Lower Byte (LB#) access. The IS62/65WV12816EALL/EBLL are packaged in the JEDEC standard 48-pin mini BGA (6mm x 8mm) and 44-Pin TSOP (TYPE II) BLOCK DIAGRAM DECODER A0 – A16 128K x 16 MEMORY ARRAY VDD GND I/O0 – I/O7 Lower Byte I/O8 – I/O15 Upper Byte CS2 CS1# OE# WE# UB# LB# I/O DATA CIRCUIT COLUMN I/O CONTROL CIRCUIT Copyright © 2017 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc.- www.issi.com Rev. C2 05/24/2017 1 IS62WV12816EALL IS62/65WV12816EBLL PIN CONFIGURATIONS 48-Pin mini BGA (6mm x 8mm) (Package Code B) 48-Pin mini BGA (6mm x 8mm) 2 CS Option (Package Code B2) 1 2 3 4 5 6 LB# OE3 A0 A1 A2 NC A B I/O8 UB# A3 A4 CS1# I/O0 C I/O9 I/O10 A5 A6 I/O1 D GND I/O11 NC A7 D VDD I/O12 NC F I/O14 I/O13 G I/O15 H NC A 1 2 3 4 5 6 LB# OE3 A0 A1 A2 CS2 B I/O8 UB# A3 A4 CS1# I/O0 I/O2 C I/O9 I/O10 A5 A6 I/O1 I/O2 I/O3 VDD D GND I/O11 NC A7 I/O3 VDD A16 I/O4 GND D VDD I/O12 NC A16 I/O4 GND A14 A15 I/O5 I/O6 F I/O14 I/O13 A14 A15 I/O5 I/O6 NC A12 A13 WE# I/O7 G I/O15 NC A12 A13 WE# I/O7 A8 A9 A10 A11 NC H NC A8 A9 A10 A11 NC PIN DESCRIPTIONS A0-A16 Address Inputs I/O0-I/O15 CS1#, CS2 OE# WE# LB# Data Inputs/Outputs Chip Enable Input UB# NC VDD GND Output Enable Input Write Enable Input Lower-byte Control (I/O0-I/O7) Upper-byte Control (I/O8-I/O15) No Connection Power Ground Integrated Silicon Solution, Inc.- www.issi.com Rev. C2 05/24/2017 44-Pin mini TSOP (Type II) (Package Code T) A4 1 44 A5 A3 2 43 A6 A2 3 42 A7 A1 4 41 OE# A0 5 40 UB# CS# 6 39 LB# I/O0 7 38 I/O15 I/O1 I/O2 8 9 37 I/O14 36 I/O13 I/O3 10 35 I/O12 VDD 11 34 GND GND 12 I/O4 13 33 32 VDD I/O11 I/O10 I/O9 I/O5 14 I/O6 15 31 30 I/O7 16 29 I/O8 WE# 17 28 NC A16 18 27 A8 A15 19 26 A14 20 25 A9 A10 A13 21 24 A11 A12 22 23 NC 2 IS62WV12816EALL IS62/65WV12816EBLL FUNCTION DESCRIPTION SRAM is one of random access memories. Each byte or word has an address and can be accessed randomly. SRAM has three different modes supported. Each function is described below with Truth Table. STANDBY MODE Device enters standby mode when deselected (CS1# HIGH or CS2 LOW or both UB# and LB# are HIGH). The input and output pins (I/O0-15) are placed in a high impedance state. The current consumption in this mode will be ISB1 or ISB2. CMOS input in this mode will maximize saving power. WRITE MODE Write operation issues with Chip selected (CS1# LOW and CS2 HIGH) and Write Enable (WE#) input LOW. The input and output pins (I/O0-15) are in data input mode. Output buffers are closed during this time even if OE# is LOW. UB# and LB# enables a byte write feature. By enabling LB# LOW, data from I/O pins (I/O0 through I/O7) are written into the location specified on the address pins. And with UB# being LOW, data from I/O pins (I/O8 through I/O15) are written into the location. READ MODE Read operation issues with Chip selected (CS1# LOW and CS2 HIGH) and Write Enable (WE#) input HIGH. When OE# is LOW, output buffer turns on to make data output. Any input to I/O pins during READ mode is not permitted. UB# and LB# enables a byte read feature. By enabling LB# LOW, data from memory appears on I/O0-7. And with UB# being LOW, data from memory appears on I/O8-15. In the READ mode, output buffers can be turned off by pulling OE# HIGH. In this mode, internal device operates as READ but I/Os are in a high impedance state. Since device is in READ mode, active current is used. TRUTH TABLE Mode Not Selected Output Disabled Read Write CS1# CS2 WE# OE# LB# UB# I/O0-I/O7 I/O8-I/O15 H X X L L L L L L L L X L X H H H H H H H H X X X H H H H H L L L X X X H H L L L X X X X X H L X L H L L H L X X H X L H L L H L L High-Z High-Z High-Z High-Z High-Z DOUT High-Z DOUT DIN High-Z DIN High-Z High-Z High-Z High-Z High-Z High-Z DOUT DOUT High-Z DIN DIN Integrated Silicon Solution, Inc.- www.issi.com Rev. C2 05/24/2017 VDD Current ISB1,ISB2 ICC ICC ICC 3 IS62WV12816EALL IS62/65WV12816EBLL ABSOLUTE MAXIMUM RATINGS AND OPERATING RANGE ABSOLUTE MAXIMUM RATINGS (1) Symbol Vt erm tBIAS Parameter Terminal Voltage with Respect to GND Temperature Under Bias Value –0.2 to +3.9(VDD+0.3V) –55 to +125 VDD V DD Related to GND –0.2 to +3.9(VDD+0.3V) Storage Temperature –65 to +150 DC Output Current (LOW) 20 tStg IOUT (2) Unit V C V C mA Notes: 1. 2. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. This condition is not per pin. Total current of all pins must meet this value. OPERATING RANGE (1) Range Device Marking Ambient Temperature VDD Commercial IS62WV12816EALL 0C to +70C 1.65V-2.2V Industrial IS62WV12816EALL -40C to +85C 1.65V-2.2V Commercial IS62WV12816EBLL 0C to +70C 2.2V-3.6V Industrial IS62WV12816EBLL -40C to +85C 2.2V-3.6V Automotive IS65WV12816EBLL -40C to +125C 2.2V-3.6V Note: 1. Full device AC operation assumes a 100 µs ramp time from 0 to Vcc(min) and 200 µs wait time after Vcc stabilization. PIN CAPACITANCE (1) Parameter Symbol Input capacitance DQ capacitance (IO0–IO15) CIN CI/O Test Condition TA = 25°C, f = 1 MHz, VDD = VDD(typ) Max Units 10 10 pF pF Note: 1. These parameters are guaranteed by design and tested by a sample basis only. THERMAL CHARACTERISTICS (1) Parameter Thermal resistance from junction to ambient (airflow = 1m/s) Thermal resistance from junction to pins Thermal resistance from junction to case Symbol RθJA RθJB RθJC Rating TBD TBD TBD Units °C/W °C/W °C/W Note: 1. These parameters are guaranteed by design and tested by a sample basis only. Integrated Silicon Solution, Inc.- www.issi.com Rev. C2 05/24/2017 4 IS62WV12816EALL IS62/65WV12816EBLL AC TEST CONDITIONS (OVER THE OPERATING RANGE) Parameter Unit (1.65V~2.2V) 0V to VDD Input Pulse Level Unit (2.2V~3.6V) 0V to VDD Input Rise and Fall Time 1V/ns 1V/ns Output Timing Reference Level 0.9V ½ VDD R1 13500 1005 R2 10800 820 VTM 1.8V VDD Output Load Conditions Refer to Figure 1 and 2 OUTPUT LOAD CONDITIONS FIGURES FIGURE 1 FIGURE 2 R1 R1 VTM VTM OUTPUT OUTPUT 30pF, Including jig and scope R2 Integrated Silicon Solution, Inc.- www.issi.com Rev. C2 05/24/2017 5pF, Including jig and scope R2 5 IS62WV12816EALL IS62/65WV12816EBLL ELECTRICAL CHARACTERISTICS IS62WV12816EALL DC ELECTRICAL CHARACTERISTICS-I (OVER THE OPERATING RANGE) Symbol VOH VOL VIH(1) VIL(1) ILI ILO Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Output Leakage Test Conditions I OH = -0.1 mA IOL = 0.1 mA GND < VIN < VDD GND < VIN < VDD, Output Disabled Min. 1.4 — 1.4 –0.2 –1 –1 Max. — 0.2 VDD + 0.2 0.4 1 1 Unit V V V V µA µA Notes: 1. VILL(min) = -1.0V AC (pulse width < 10ns). Not 100% tested. VIHH (max) = VDD + 1.0V AC (pulse width < 10ns). Not 100% tested. IS62(5)WV12816EBLL DC ELECTRICAL CHARACTERISTICS-I (OVER THE OPERATING RANGE) Symbol VOH Parameter Output HIGH Voltage VOL Output LOW Voltage VIH(1) Input HIGH Voltage VIL(1) Input LOW Voltage ILI ILO Notes: 1. Input Leakage Output Leakage Test Conditions 2.2 ≤ V DD < 2.7, I OH = -0.1 mA 2.7 ≤ V DD ≤ 3.6, I OH = -1.0 mA 2.2 ≤ V DD < 2.7, IOL = 0.1 mA 2.7 ≤ V DD ≤ 3.6, IOL = 2.1 mA 2.2 ≤ V DD < 2.7 2.7 ≤ V DD ≤ 3.6 2.2 ≤ V DD < 2.7 2.7 ≤ V DD ≤ 3.6 GND < VIN < VDD GND < VIN < VDD, Output Disabled Min. 2.0 2.4 — — 1.8 2.2 –0.3 –0.3 –1 –1 Max. — — 0.4 0.4 VDD + 0.3 VDD + 0.3 0.6 0.8 1 1 Unit V V V V V V V V µA µA VILL(min) = -2.0V AC (pulse width < 10ns). Not 100% tested. VIHH (max) = VDD + 2.0V AC (pulse width < 10ns). Not 100% tested. Integrated Silicon Solution, Inc.- www.issi.com Rev. C2 05/24/2017 6 IS62WV12816EALL IS62/65WV12816EBLL IS62WV12816EALL DC ELECTRICAL CHARACTERISTICS-II FOR POWER (OVER THE OPERATING RANGE) Symbol Parameter ICC VDD Dynamic Operating Supply Current VDD=VDD(max), IOUT=0mA, f = fmax CS1# = VIL, CS2 = VIH VDD Static Operating Supply Current VDD=VDD(max), IOUT = 0mA, f=0 CS1# = VIL, CS2 = VIH ICC1 CMOS Standby Current (CMOS Inputs) ISB2 Test Conditions VDD = VDD(max), f = 0, CS1# ≥ VDD - 0.2V or 0V ≤ CS2 ≤ 0.2V or LB# and UB# ≥ VDD - 0.2V VIN ≤ 0.2V or VIN ≥ VDD - 0.2V Grade Com. 10 15 Ind. - 18 Com. 1 3 Ind. - 3 25°C 5.4 10 45°C 5.6 11 70°C 7.0 13 85°C 7.6 16 Unit mA mA Com. µA Ind. Note: 1. 55ns Typ (1) Max Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VDD = 1.8V IS62(5)WV12816EBLL DC ELECTRICAL CHARACTERISTICS-II FOR POWER (OVER THE OPERATING RANGE) Symbol ICC ICC1 ISB2 Note: 1. Parameter VDD Dynamic Operating Supply Current VDD Static Operating Supply Current CMOS Standby Current (CMOS Inputs) Test Conditions Grade Com. 10 15 Ind. - 18 Auto. - 25 Com. 1 3 Ind. - 3 Auto. - 4 25°C 5.4 10 45°C 5.6 11 70°C 7.0 13 Ind. 85°C 7.6 16 Auto. 125°C 12.6 32 VDD=VDD(max), IOUT=0mA, f = fmax CS1# = VIL, CS2 = VIH VDD=VDD(max), IOUT = 0mA, f=0 CS1# = VIL, CS2 = VIH VDD = VDD(max), f = 0, CS1# ≥ VDD - 0.2V or 0V ≤ CS2 ≤ 0.2V or LB# and UB# ≥ VDD - 0.2V VIN ≤ 0.2V or VIN ≥ VDD - 0.2V 45/55ns Typ(1) Max Com. Unit mA mA µA Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VDD = 3.0V Integrated Silicon Solution, Inc.- www.issi.com Rev. C2 05/24/2017 7 IS62WV12816EALL IS62/65WV12816EBLL AC CHARACTERISTICS (6) (OVER OPERATING RANGE) READ CYCLE AC CHARACTERISTICS Parameter Symbol Read Cycle Time Address Access Time Output Hold Time CS1#, CS2 Access Time 45ns 55ns unit notes 55 55 ns ns ns ns 1,5 1 1 1 5 10 - 25 18 18 55 ns ns ns ns ns ns 1 2 2 2 2 1,7 10 18 - ns ns 2 2 unit notes Min Max Min Max tRC tAA tOHA tACS1/tACS2 45 8 - 45 45 55 8 - OE# Access Time OE# to High-Z Output OE# to Low-Z Output CS1#, CS2 to High-Z Output CS1#, CS2 to Low-Z Output UB#, LB# Access Time tDOE tHZOE tLZOE tHZCS/tHZCS2 tLZCS/tLZCS2 tBA 5 10 - 22 18 18 45 UB#, LB# to High-Z Output UB#, LB# to Low-Z Output tHZB tLZB 10 18 - WRITE CYCLE AC CHARACTERISTICS Parameter Symbol Write Cycle Time CS1#, CS2 to Write End 45ns 55ns Min Max Min Max tWC tSCS1/tSCS2 45 35 - 55 40 - ns ns 1,3,5 1,3 Address Setup Time to Write End Address Hold from Write End Address Setup Time UB#,LB# to Write End WE# Pulse Width Data Setup to Write End tAW tHA tSA tPWB tPWE tSD 35 0 0 35 35 28 - 40 0 0 40 40 28 - ns ns ns ns ns ns 1,3 1,3 1,3 1,3 1,3,4 1,3 Data Hold from Write End WE# LOW to High-Z Output WE# HIGH to Low-Z Output tHD tHZWE tLZWE 0 10 18 - 0 10 18 - ns ns ns 1,3 2,3 2,3 Notes: 1. Tested with the load in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. tHZOE, tHZCS, tHZB, and tHZWE transitions are measured when the output enters a high impedance state. Not 100% tested. 3. The internal write time is defined by the overlap of CS1# = LOW, CS2=HIGH, UB# or LB# = LOW, and WE# = LOW. All four conditions must be in valid states to initiate a Write, but any condition can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. 4. tPWE > tHZWE + tSD when OE# is LOW. 5. Address inputs must meet VIH and VIL SPEC during this period. Any glitch or unknown inputs are not permitted. Unknown input with standby mode is acceptable. 6. Data retention characteristics are defined later in DATA RETENTION CHARACTERISTICS. Integrated Silicon Solution, Inc.- www.issi.com Rev. C2 05/24/2017 8 IS62WV12816EALL IS62/65WV12816EBLL TIMING DIAGRAM READ CYCLE NO. 1(1) (ADDRESS CONTROLLED, CS1# = OE# = UB# = LB# = LOW, CS2 = WE# = HIGH) tRC Address tAA tOHA tOHA DOUT PREVIOUS DATA VALID LOW-Z DATA VALID Note: 1. The device is continuously selected. READ CYCLE NO.2 (1) (OE# CONTROLLED) tRC ADDRESS tAA tOHA tDOE OE# tHZOE tLZOE CS1# tHZCS1/ tHZCS2 tACS1/tACS2 CS2 tLZCS1/ tLZCS2 UB#,LB# tHZB tBA tLZB DOUT Note: 1. HIGH-Z LOW-Z DATA VALID Address is valid prior to or coincident with CS1# LOW or CS2 HIGH transition. Integrated Silicon Solution, Inc.- www.issi.com Rev. C2 05/24/2017 9 IS62WV12816EALL IS62/65WV12816EBLL WRITE CYCLE NO.1 (1, 2) (CS1# , CS2 Controlled, OE# = HIGH or LOW) tWC ADDRESS tSCS1 tSA CS1# tHA tSCS2 CS2 tAW tPWE WE# tPWB UB#, LB# tHZWE DATA UNDEFINED DOUT HIGH-Z (1) tSD DATA UNDEFINED DIN (2) tLZWE tHD DATA IN VALID Notes: 1. tHZWE is based on the assumption when tSA=0nS after READ operation. Actual DOUT for tHZWE may not appear if OE# goes high before Write Cycle. tHZOE is the time DOUT goes to High-Z after OE# goes high. 2. During this period, the I/Os are in output state. Do not apply input signals. WRITE CYCLE NO. 2 (1, 2) (WE# CONTROLLED: OE# IS HIGH DURING WRITE CYCLE) tWC ADDRESS tSCS1 CS1# tSCS2 CS2 WE# tHA tAW tPWE tSA tPWB UB#, LB# OE# DOUT tHZOE DATA UNDEFINED HIGH-Z (1) tSD DIN DATA UNDEFINED (2) tHD DATA IN VALID Notes: 1. tHZOE is the time DOUT goes to High-Z after OE# goes high. 2. During this period, the I/Os are in output state. Do not apply input signals. Integrated Silicon Solution, Inc.- www.issi.com Rev. C2 05/24/2017 10 IS62WV12816EALL IS62/65WV12816EBLL WRITE CYCLE NO. 3 (1) (WE# CONTROLLED: OE# IS LOW DURING WRITE CYCLE) tWC ADDRESS tSCS1 CS1# tHA tSCS2 CS2 tAW WE# tPWE tSA tPWB UB#, LB# tHZWE DOUT DATA UNDEFINED DIN DATA UNDEFINED (1) HIGH-Z tSD (2) tLZWE tHD DATA IN VALID Notes: 3. If OE# is low during write cycle, tHZWE must be met in the application. Do not apply input signal during this period. Data output from the previous READ operation will drive IO BUS. Integrated Silicon Solution, Inc.- www.issi.com Rev. C2 05/24/2017 11 IS62WV12816EALL IS62/65WV12816EBLL WRITE CYCLE NO. 4 (1, 2, 3) (UB# & LB# Controlled, OE# = LOW) tWC tWC ADDRESS ADDRESS 1 ADDRESS 2 CS1#=LOW CS2=HIGH OE#=LOW tSA tHA tSA tHA WE# tPWB UB#, LB# tPWB WORD 1 WORD 2 tHZWE DOUT tLZWE HIGH-Z DATA UNDEFINED tHD tSD DIN DATA IN VALID DATA IN VALID Notes: 1. If OE# is low during write cycle, tHZWE must be met in the application. Do not apply input signal during this period. Data output from the previous READ operation will drive IO BUS. 2. Due to the restriction of note1, OE# is recommended to be HIGH during write period. 3. WE# stays LOW in this example. If WE# toggles, tPWE and tHZWE must be considered. Integrated Silicon Solution, Inc.- www.issi.com Rev. C2 05/24/2017 12 IS62WV12816EALL IS62/65WV12816EBLL DATA RETENTION CHARACTERISTICS Symbol VDR Parameter VDD for Data Retention IDR Data Retention Current tSDR Data Retention Setup Time Recovery Time tRDR Notes: 1. 2. Test Condition OPTION See Data Retention Waveform VDD= VDR(min), CS1# ≥ VDD – 0.2V,(1) or 0V ≤ CS2 ≤ 0.2V, or LB# and UB# ≥ VDD -0.2V, VIN ≤ 0.2V or VIN ≥ VDD - 0.2V Min Typ(2) Max Unit 1.5 - - V Com. - Ind. - Auto A3 - See Data Retention Waveform See Data Retention Waveform 13 5.4 16 uA 32 0 - - ns tRC - - ns If CS1# >VDD–0.2V, all other inputs including CS2 and UB# and LB# must meet this condition. Typical values are measured at VDD= VDR (min), TA = 25C, and not 100% tested. DATA RETENTION WAVEFORM (CS1# CONTROLLED) tSDR Data Retention Mode tRDR VDD VDR CS1# > VDD – 0.2V CS1# GND DATA RETENTION WAVEFORM (CS2 CONTROLLED) tSDR Data Retention Mode tRDR VDD CS2 VDR CS2 < 0.2V GND Integrated Silicon Solution, Inc.- www.issi.com Rev. C2 05/24/2017 13 IS62WV12816EALL IS62/65WV12816EBLL DATA RETENTION WAVEFORM (UB# AND LB# CONTROLLED) tSDR Data Retention Mode tRDR VDD VDR UB#/LB# UB# and LB# > VDD – 0.2V GND Note: 1. CS2 must satisfy either CS2 ≥ VDD -0.2V or CS2 ≤ 0.2V 2. CS1# must satisfy either CS1# ≥ VDD - 0.2V or CS1# ≤ 0.2V Integrated Silicon Solution, Inc.- www.issi.com Rev. C2 05/24/2017 14 IS62WV12816EALL IS62/65WV12816EBLL ORDERING INFORMATION IS62WV12816EALL (1.65V - 2.2V) Industrial Range: –40°C to +85°C Speed (ns) Order Part No. Package 55 IS62WV12816EALL-55TLI TSOP (Type II), Lead-free 55 IS62WV12816EALL-55BI mini BGA (6mm x 8mm) 55 IS62WV12816EALL-55B2I mini BGA (6mm x 8mm), 2 CS Option 55 IS62WV12816EALL-55BLI mini BGA (6mm x 8mm), Lead-free IS62WV12816EBLL (2.2V - 3.6V) Industrial Range: –40°C to +85°C Speed (ns) Order Part No. Package 45 IS62WV12816EBLL-45TLI TSOP (Type II), Lead-free 45 IS62WV12816EBLL-45BLI mini BGA (6mm x 8mm), Lead-free 45 IS62WV12816EBLL-45B2LI mini BGA (6mm x 8mm), 2 CS Option, Lead-free 55 IS62WV12816EBLL-55TLI TSOP (Type II), Lead-free 55 IS62WV12816EBLL-55BI mini BGA (6mm x 8mm) 55 IS62WV12816EBLL-55BLI mini BGA (6mm x 8mm), Lead-free 55 IS62WV12816EBLL-55B2LI mini BGA (6mm x 8mm), 2 CS Option, Lead-free IS65WV12816EBLL (2.2V - 3.6V) Automotive Range (A3): –40°C to +125°C Speed (ns) Order Part No. Package 55 IS65WV12816EBLL-55CTLA3 TSOP (Type II), Lead-free, Copper Leadframe 55 IS65WV12816EBLL-55BLA3 mini BGA (6mm x 8mm), Lead-free Integrated Silicon Solution, Inc.- www.issi.com Rev. C2 05/24/2017 15 IS62WV12816EALL IS62/65WV12816EBLL PACKAGE INFORMATION Integrated Silicon Solution, Inc.- www.issi.com Rev. C2 05/24/2017 16 IS62WV12816EALL IS62/65WV12816EBLL Integrated Silicon Solution, Inc.- www.issi.com Rev. C2 05/24/2017 17