IS62WV20488BLL-25TLI 数据手册
IS62WV20488ALL
IS62WV20488BLL
2M x 8 HIGH-SPEED LOW POWER
CMOS STATIC RAM
FEATURES
• High-speed access times:
25, 35 ns
• High-performance, low-power CMOS process
• Multiple center power and ground pins for greater
noise immunity
• Fully static operation: no clock or refresh
required
• TTL compatible inputs and outputs
• Single power supply
– Vdd 1.65V to 2.2V (IS62WV20488ALL)
speed = 35ns for Vcc = 1.65V to 2.2V
August 2016
DESCRIPTION
The ISSI IS62WV20488ALL/BLL is a high-speed,
low power, 2M-word by 8-bit CMOS static RAM. The
IS62WV20488ALL/BLL is fabricated using ISSI's highperformance CMOS technology. This highly reliable process coupled with innovative circuit design techniques,
yields higher performance and low power consumption
devices.
When CS1 is HIGH (deselected) or when CS2 is LOW
(deselected), the device assumes a standby mode at
which the power dissipation can be reduced down with
CMOS input levels.
The IS62WV20488ALL/BLL operates from a single
power supply and all inputs are TTL-compatible.
– Vdd 2.4V to 3.6V (IS62WV20488BLL)
speed = 25ns for Vcc = 2.4V to 3.6V
• Packages available:
– 48-ball miniBGA (9mm x 11mm)
– 44-pin TSOP (Type II)
• Industrial Temperature Support
• Lead-free available
The IS62WV20488ALL/BLL is available in 48 ball mini
BGA and 44-pin TSOP (Type II) packages.
FUNCTIONAL BLOCK DIAGRAM
A0-A20
DECODER
2M X 8
MEMORY ARRAY
I/O
DATA
CIRCUIT
COLUMN I/O
VDD
GND
I/O0-I/O7
CS2
CS1
OE
CONTROL
CIRCUIT
WE
Copyright © 2016 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the
latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 1
Rev. A1
08/24/16
IS62WV20488ALL
IS62WV20488BLL
PIN CONFIGURATION
48-pin Mini BGA (M ) (9mm x 11mm)
1
2
3
4
5
44-pin TSOP (Type II )
6
A
NC
OE
A0
A1
A2
CS2
B
NC
NC
A3
A4
CS1
I/O0
C
NC
NC
A5
A6
I/O1
I/O2
D
GND
NC
A17
A7
I/O3
VDD
E
VDD
NC
NC
A16
I/O4
GND
F
NC
NC
A14
A15
I/O5
I/O6
G
NC
A19
A12
A13
WE
I/O7
H
A18
A8
A9
A10
A11
A20
NC
NC
A0
A1
A2
A3
A4
CS1
I/O0
I/O1
VDD
GND
I/O2
I/O3
WE
A5
A6
A7
A8
A9
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
NC
NC
A20
A18
A17
A16
A15
OE
I/O7
I/O6
GND
VDD
I/O5
I/O4
A14
A13
A12
A11
A10
A19
NC
NC
PIN DESCRIPTIONS
A0-A20 Address Inputs
CS1, CS2
Chip Enable Input
OE
Output Enable Input
WE
Write Enable Input
I/O0-I/O7 Data Input / Output
Vdd
Power
GND
Ground
NC
No Connection
2
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A1
08/24/2016
IS62WV20488ALL
IS62WV20488BLL
TRUTH TABLE
Mode
WE CS1 CS2 OE
Not Selected X
H
X
X
(Power-down) X
X
L
X
Output Disabled H
L
H
H
Read
H
L
H
L
Write
L
L
H
X
I/O Operation Vdd Current
High-Z
Isb1, Isb2
High-Z
Dout
Din
Icc
Icc
Icc
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter
Vterm
Terminal Voltage with Respect to GND
Vdd
Vdd Relates to GND
Tstg
Storage Temperature
Pt
Power Dissipation
Value
Unit
–0.5 to Vdd + 0.5
V
–0.3 to 4.0
V
–65 to +150
°C
1.0
W
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
CAPACITANCE(1,2)
Symbol
Cin
CI/O
Parameter
Input Capacitance
Input/Output Capacitance
Conditions
Vin = 0V
Vout = 0V
Max.
6
8
Unit
pF
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: Ta = 25°C, f = 1 MHz, Vdd = 3.3V.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 3
Rev. A1
08/24/016
IS62WV20488ALL
IS62WV20488BLL
OPERATING RANGE (Vdd) (IS62WV20488ALL)
Range
Ambient Temperature
Commercial
0°C to +70°C
Industrial
–40°C to +85°C
Vdd (35 ns)
1.65V-2.2V
1.65V-2.2V
OPERATING RANGE (Vdd) (IS62WV20488BLL)(1)
Range
Ambient Temperature
Commercial
0°C to +70°C
Industrial
–40°C to +85°C
Vdd (25 ns)
2.4V-3.6V
2.4V-3.6V
Note:
1. When operated in the range of 2.4V-3.6V, the device meets 25ns. When operated in
the range of 3.3V + 5%, the device meets 15ns.
4
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A1
08/24/2016
IS62WV20488ALL
IS62WV20488BLL
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Vdd = 2.4V-3.6V
Symbol
Voh
Vol
Vih
Vil
Ili
Ilo
Parameter
Test Conditions
Output HIGH Voltage
Vdd = Min., Ioh = –1.0 mA
Output LOW Voltage
Vdd = Min., Iol = 1.0 mA
Input HIGH Voltage
Input LOW Voltage(1)
Input Leakage
GND ≤ Vin ≤ Vdd
Output Leakage
GND ≤ Vout ≤ Vdd, Outputs Disabled
Min.
Max.
Unit
1.8
—
V
—
0.4
V
2.0
Vdd + 0.3
V
–0.3 0.8 V
–1 1 µA
–1
1
µA
Note:
1. Vil (min.) = –0.3V DC; Vil (min.) = –2.0V AC (pulse width 2.0 ns). Not 100% tested.
Vih (max.) = Vdd + 0.3V DC; Vih (max.) = Vdd + 2.0V AC (pulse width 2.0 ns). Not 100% tested.
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Vdd = 1.65V-2.2V
Symbol
Voh
Vol
Vih
Vil(1)
Ili
Ilo
Parameter
Test Conditions
Vdd
Output HIGH Voltage
Ioh = -0.1 mA
1.65-2.2V
Output LOW Voltage
Iol = 0.1 mA
1.65-2.2V
Input HIGH Voltage
1.65-2.2V
Input LOW Voltage
1.65-2.2V
Input Leakage
GND ≤ Vin ≤ Vdd
Output Leakage
GND ≤ Vout ≤ Vdd, Outputs Disabled
Min. Max. Unit
1.4
—
V
—
0.2
V
1.4
Vdd + 0.2
V
–0.2
0.4
V
–1 1 µA
–1
1
µA
Note:
1. Vil (min.) = –0.3V DC; Vil (min.) = –2.0V AC (pulse width 2.0 ns). Not 100% tested.
Vih (max.) = Vdd + 0.3V DC; Vih (max.) = Vdd + 2.0V AC (pulse width 2.0 ns). Not 100% tested.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 5
Rev. A1
08/24/016
IS62WV20488ALL
IS62WV20488BLL
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-25
-35
Symbol Parameter
Test Conditions Min. Max.
Min. Max.
Unit
Icc
Vdd Dynamic Operating Vdd = Max.,
Com.
—
25
—
20
mA
Supply Current
Iout = 0 mA, f = fmax
Ind. — 30
— 25
typ.(2)
20
17
Icc1
Operating
Vdd = Max.,
Com.
—
10
—
10
mA
Supply Current
Iout = 0 mA, f = 0
Ind. — 15
— 15
Isb1
TTL Standby Current
Vdd = Max.,
Com.
—
5
— 5
mA
(TTL Inputs)
Vin = Vih or Vil
Ind. — 6
— 6
CS1 ≥ Vih, f = 0, CS2 = Vil
Isb2
CMOS Standby
Vdd = Max.,
Com.
—
1.5
—
1.5 mA
Current (CMOS Inputs) CS1 ≥ Vdd – 0.2V,
Ind.
—
1.5
—
1.5
CS2 ≤ 0.2V, typ.(2)
0.8
0.5
Vin ≥ Vdd – 0.2V, or
Vin ≤ 0.2V, f = 0
Note:
1. At f = fmax, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
2. Typical values are measured at Vdd = 3.0V, Ta = 25oC and not 100% tested.
6
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A1
08/24/2016
IS62WV20488ALL
IS62WV20488BLL
AC TEST CONDITIONS (LOW POWER)
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Level (VRef)
Output Load
Unit
Unit
(2.4V-3.6V)
(1.65V-2.2V)
0.4V to Vdd-0.3V
0.4V to Vdd-0.2V
1.5ns
1.5ns
Vdd/2 Vdd/2
See Figures 1 and 2
See Figures 1 and 2
AC TEST LOADS
3070
3070
1.8V/3.3V
1.8V/3.3V
OUTPUT
OUTPUT
30 pF
Including
jig and
scope
3150
Figure 1
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A1
08/24/016
5 pF
Including
jig and
scope
3150
Figure 2
7
IS62WV20488ALL
IS62WV20488BLL
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
Symbol
trc
taa
toha
tacs1/tacs2
tdoe
thzoe(2)
tlzoe(2)
thzcs1/thzcs2(2)
tlzcs1/tlzcs2(2)
Parameter
Read Cycle Time
Address Access Time
Output Hold Time
CS1/CS2 Access Time
OE Access Time
OE to High-Z Output
OE to Low-Z Output
CS1/CS2 to High-Z Output
CS1/CS2 to Low-Z Output
25ns 35ns
Min. Max. Min. Max. Unit
25
—
35
—
ns
—
25
—
35
ns
4
—
4
—
ns
—
25
—
35
ns
—
12
—
15
ns
—
8
—
10
ns
5
—
5
—
ns
0
8
0
10
ns
10
—
10
—
ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V/1.5V, input pulse levels of 0.4 to Vdd-0.2V/0.4V to
Vdd-0.3V and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
AC WAVEFORMS
READ CYCLE NO. 1(1,2) (Address Controlled) (CS1 = OE = Vil, CS2 = WE = Vih)
tRC
ADDRESS
tAA
tOHA
DOUT
8
PREVIOUS DATA VALID
tOHA
DATA VALID
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A1
08/24/2016
IS62WV20488ALL
IS62WV20488BLL
AC WAVEFORMS
READ CYCLE NO. 2(1,3) (CS1, CS2, OE Controlled)
tRC
ADDRESS
tAA
tOHA
OE
tDOE
CS1
tHZOE
tLZOE
tACS1/tACS2
CS2
DOUT
tLZCS1/
tLZCS2
HIGH-Z
tHZCS
DATA VALID
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CS1= Vil. CS2=WE=Vih.
3. Address is valid prior to or coincident with CS1 LOW and CS2 HIGH transition.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A1
08/24/016
9
IS62WV20488ALL
IS62WV20488BLL
WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range)
Symbol
Parameter
twc
Write Cycle Time
tscs1/tscs2 CS1/CS2 to Write End
taw
Address Setup Time to Write End
tha
Address Hold from Write End
tsa
Address Setup Time
(4)
tpwe
WE Pulse Width
tsd
Data Setup to Write End
thd
Data Hold from Write End
thzwe(3) WE LOW to High-Z Output
tlzwe(3)
WE HIGH to Low-Z Output
25 ns
Min. Max.
25
—
18
—
15
—
0
—
0
—
18
—
12
—
0
—
—
12
5
—
35 ns
Min. Max.
Unit
35
—
ns
25
—
ns
25
—
ns
0
—
ns
0
—
ns
30
—
ns
15
—
ns
0
— ns
—
20
ns
5
—
ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V/1.5V, input pulse levels of 0.4 to Vdd-0.2V/0.4V
to Vdd-0.3V and output loading specified in Figure 1.
2. The internal write time is defined by the overlap of CS1 LOW, CS2 HIGH and UB or LB, and WE LOW. All signals must be in valid states to initiate a Write, but
any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the
write.
3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
4. tpwe > thzwe + tsd when OE is LOW.
AC WAVEFORMS
WRITE CYCLE NO. 1 (CS1/CS2 Controlled, OE = HIGH or LOW)
tWC
ADDRESS
tHA
tSCS1
CS1
tSCS2
CS2
tAW
tPWE
WE
tSA
DOUT
DATA UNDEFINED
tHZWE
tLZWE
HIGH-Z
tSD
DIN
10
tHD
DATA-IN VALID
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A1
08/24/2016
IS62WV20488ALL
IS62WV20488BLL
AC WAVEFORMS
WRITE CYCLE NO. 2 (WE Controlled: OE is HIGH During Write Cycle)
tWC
ADDRESS
OE
tHA
tSCS1
CS1
tSCS2
CS2
tAW
tPWE
WE
tSA
DOUT
tHZWE
tLZWE
HIGH-Z
DATA UNDEFINED
tSD
DIN
tHD
DATA-IN VALID
WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle)
tWC
ADDRESS
OE
tHA
tSCS1
CS1
tSCS2
CS2
tAW
tPWE
WE
tSA
DOUT
DATA UNDEFINED
tHZWE
tLZWE
HIGH-Z
tSD
DIN
tHD
DATA-IN VALID
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Rev. A1
08/24/016
IS62WV20488ALL
IS62WV20488BLL
DATA RETENTION SWITCHING CHARACTERISTICS
Symbol
Vdr
Idr
tsdr
trdr
Parameter
Vcc for Data Retention
Data Retention Current
Data Retention Setup Time
Recovery Time
Test Condition Min. Typ.(1) Max. Unit
See Data Retention Waveform 1.2
3.6
V
Vcc = 1.2V, CS1/CS2 ≥ Vcc – 0.2V
—
0.5
1.5
mA
See Data Retention Waveform
0
—
ns
See Data Retention Waveform trc — ns
Note:
1. Typical values are measured at Vdd = 3.0V, Ta = 25oC and not 100% tested.
DATA RETENTION WAVEFORM (CS1 Controlled)
Data Retention Mode
tSDR
3.0V
2.2V
tRDR
VCC
VDR
CS1 ≥ VCC
CS1
GND
- 0.2V
DATA RETENTION WAVEFORM (CS2 Controlled)
Data Retention Mode
3.0
VCC
CS2
2.2V
tSDR
tRDR
VDR
0.4V
CS2 ≤ 0.2V
GND
12
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A1
08/24/2016
IS62WV20488ALL
IS62WV20488BLL
ORDERING INFORMATION
Industrial Range: -40°C to +85°C
Voltage Range: 2.4V to 3.6V
peed (ns)
S
25
Order Part No.
IS62WV20488BLL-25MI
IS62WV20488BLL-25MLI
IS62WV20488BLL-25TI
IS62WV20488BLL-25TLI
Package
48 mini BGA (9mm x 11mm)
48 mini BGA (9mm x 11mm), Lead-free
TSOP (Type II)
TSOP (Type II), Lead-free
Industrial Range: -40°C to +85°C
Voltage Range: 1.65V to 2.2V
peed (ns)
S
35
Order Part No.
IS62WV20488ALL-35MI
IS62WV20488ALL-35MLI
IS62WV20488ALL-35TI
IS62WV20488ALL-35TLI
Package
48 mini BGA (9mm x 11mm)
48 mini BGA (9mm x 11mm), Lead-free
TSOP (Type II)
TSOP (Type II), Lead-free
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Rev. A1
08/24/016
14
1. CONTROLLING DIMENSION : MM .
2. Reference document : JEDEC MO-207
NOTE :
08/21/2008
IS62WV20488ALL
IS62WV20488BLL
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A1
08/24/2016
Rev. A1
08/24/016
Package Outline
06/04/2008
3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION/INTRUSION.
2. DIMENSION D AND E1 DO NOT INCLUDE MOLD PROTRUSION.
1. CONTROLLING DIMENSION : MM
NOTE :
IS62WV20488ALL
IS62WV20488BLL
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