IS62WV20488EBLL-45BLI-TR

IS62/65WV20488EALL IS62/65WV20488EBLL JANUARY 2015 2Mx8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM FEATURES       High-speed access time: 45ns, 55ns CMOS low power operation – 30 mW (typical) operating – 12 µW (typical) CMOS standby TTL compatible interface levels Single power supply –1.65V—1.98V Vdd (62/65WV20488EALL) – 2.2V--3.6V Vdd (62/65WV20488EBLL) Fully static operation: no clock or refresh required Industrial (-40oC to +85oC) and Automotive (-40oC to +125oC) temperature support DESCRIPTION The ISSI IS62WV20488EALL/BLL and IS65WV20488EALL/BLL are high-speed, 16M bit static RAMs organized as 2M words by 8 bits. It is fabricated using ISSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields high-performance and low power consumption devices. When is HIGH (deselected) or when CS2 is LOW (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs. The active LOW Write Enable controls both writing and reading of the memory. The IS62WV20488EALL/BLL and IS65WV20488EALL/BLL are packaged in the JEDEC standard 48-pin mini BGA (6mm x 8mm). BLOCK DIAGRAM Copyright © 2014 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc.- www.issi.com Rev. A 12/12/2014 1 IS62/65WV20488EALL IS62/65WV20488EBLL PIN CONFIGURATION (2M x 8 Low Power) 48-pin mini BGA (B) (6mm x 8mm) PIN DESCRIPTIONS A0-A20 Address Inputs Chip Enable 1 Input CS2 Chip Enable 2 Input Output Enable Input Write Enable Input I/O0-I/O7 Input/Output NC No Connection VDD Power GND Ground Integrated Silicon Solution, Inc.- www.issi.com Rev. A 12/12/2014 2 IS62/65WV20488EALL IS62/65WV20488EBLL TRUTH TABLE Mode CS2 I/O Operation VDD Current Not Selected X H X X High-Z ISB1, ISB2 (Power-down) X X L X High-Z ISB1, ISB2 Output Disabled H L H H High-Z Icc Read H L H L Dout Icc Write L L H X Din Icc OPERATING RANGE (VDD) Range Ambient Temperature 1.65V – 1.98V 2.2V - 3.6V Commercial 0°C to +70°C IS62WV20488EALL (55ns) IS62WV20488EBLL (45, 55ns) Industrial –40°C to +85°C IS62WV20488EALL (55ns) IS62WV20488EBLL (45, 55ns) Automotive –40°C to +125°C IS65WV20488EALL (55ns) IS65WV20488EBLL (55ns) Integrated Silicon Solution, Inc.- www.issi.com Rev. A 12/12/2014 3 IS62/65WV20488EALL IS62/65WV20488EBLL ABSOLUTE MAXIMUM RATINGS AND OPERATING RANGE ABSOLUTE MAXIMUM RATINGS(1) Symbol Vter m tBIAS VDD tStg Parameter Terminal Voltage with Respect to GND Temperature Under Bias V DD Related to GND Storage Temperature Value –0.2 to +3.9(VDD+0.3V) –55 to +125 –0.2 to +3.9(VDD+0.3V) –65 to +150 IOUT DC Output Current (LOW) 20 Unit V C V C mA Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. OPERATING RANGE(1) Range Commercial Industrial Automotive Commercial Industrial Automotive Device Marking IS62WV20488EALL IS62WV20488EALL IS65WV20488EALL IS62WV20488EBLL IS62WV20488EBLL IS65WV20488EBLL Ambient Temperature 0C to +70C -40C to +85C -40C to +125C 0C to +70C -40C to +85C -40C to +125C VDD(min) 1.65V 1.65V 1.65V 2.2V 2.2V 2.2V VDD(typ) 1.8V 1.8V 1.8V 3.3V 3.3V 3.3V VDD(max) 1.98V 1.98V 1.98V 3.6V 3.6V 3.6V Note: 1. Full device AC operation assumes a 100 µs ramp time from 0 to Vcc(min) and 200 µs wait time after Vcc stabilization. PIN CAPACITANCE (1) Parameter Input capacitance DQ capacitance (IO0–IO7) Symbol CIN CI/O Test Condition TA = 25°C, f = 1 MHz, VDD = VDD(typ) Max 10 10 Units pF pF Note: 1. These parameters are guaranteed by design and tested by a sample basis only. THERMAL CHARACTERISTICS (1) Parameter Thermal resistance from junction to ambient (airflow = 1m/s) Thermal resistance from junction to case Symbol RθJA RθJC Rating 38.3 6.86 Units °C/W °C/W Note: 1. These parameters are guaranteed by design and tested by a sample basis only. Integrated Silicon Solution, Inc.- www.issi.com Rev. A 12/12/2014 4 IS62/65WV20488EALL IS62/65WV20488EBLL ELECTRICAL CHARACTERISTICS IS62(5)WV20488EALL DC ELECTRICAL CHARACTERISTICS-I (OVER THE OPERATING RANGE) Symbol VOH VOL VIH(1) VIL(1) ILI ILO Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Output Leakage Test Conditions IOH = -0.1 mA IOL = 0.1 mA GND < VIN < VDD GND < VIN < VDD, Output Disabled Min. 1.4 — 1.4 –0.2 –1 –1 Max. — 0.2 VDD + 0.2 0.4 1 1 Unit V V V V µA µA Notes: 1. VILL(min) = -1.0V AC (pulse width < 10ns). Not 100% tested. VIHH (max) = VDD + 1.0V AC (pulse width < 10ns). Not 100% tested. IS62(5)WV20488EBLL DC ELECTRICAL CHARACTERISTICS-I (OVER THE OPERATING RANGE) Symbol VOH Parameter Output HIGH Voltage VOL Output LOW Voltage VIH(1) Input HIGH Voltage VIL(1) Input LOW Voltage ILI ILO Input Leakage Output Leakage Test Conditions 2.2 ≤ VDD < 2.7, IOH = -0.1 mA 2.7 ≤ VDD ≤ 3.6, IOH = -1.0 mA 2.2 ≤ VDD < 2.7, IOL = 0.1 mA 2.7 ≤ VDD ≤ 3.6, IOL = 2.1 mA 2.2 ≤ VDD < 2.7 2.7 ≤ VDD ≤ 3.6 2.2 ≤ VDD < 2.7 2.7 ≤ VDD ≤ 3.6 GND < VIN < VDD GND < VIN < VDD, Output Disabled Min. 2.0 2.4 — — 1.8 2.2 –0.3 –0.3 –1 –1 Max. — — 0.4 0.4 VDD + 0.3 VDD + 0.3 0.6 0.8 1 1 Unit V V V V V V V V µA µA Notes: 1. VILL(min) = -2.0V AC (pulse width < 10ns). Not 100% tested. VIHH (max) = VDD + 2.0V AC (pulse width < 10ns). Not 100% tested. Integrated Silicon Solution, Inc.- www.issi.com Rev. A 12/12/2014 5 IS62/65WV20488EALL IS62/65WV20488EBLL IS62(5)WV20488EALL DC ELECTRICAL CHARACTERISTICS-II FOR POWER (OVER THE OPERATING RANGE) Symbol ICC ICC1 ISB1 Parameter VDD Dynamic Operating Supply Current VDD Static Operating Supply Current CMOS Standby Current (CMOS Inputs) Test Conditions VDD=VDD(max), IOUT=0mA, f=fMAX VDD=VDD(max), IOUT = 0mA, f=0Hz VDD=VDD(max), (1) 0V ≤ CS2 ≤ 0.2V or (2) ≥ VDD - 0.2V, CS2 ≥ VDD - 0.2V Grade Com. Ind. Auto. Com. Ind. Auto. Com. Typ. 6 3 30 Max. 12 12 12 6 6 6 50 Unit mA Ind. - 65 µA Auto. - 165 µA mA µA Note: Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VDD = VDD(typ), TA = 25C IS62(5)WV20488EBLL DC ELECTRICAL CHARACTERISTICS-II FOR POWER (OVER THE OPERATING RANGE) Symbol ICC ICC1 ISB1 Parameter VDD Dynamic Operating Supply Current VDD Static Operating Supply Current CMOS Standby Current (CMOS Inputs) Test Conditions VDD=VDD(max), IOUT=0mA, f=fMAX VDD=VDD(max), IOUT = 0mA, f=0Hz VDD=VDD(max), (1) 0V ≤ CS2 ≤ 0.2V or (2) ≥ VDD - 0.2V, CS2 ≥ VDD - 0.2V Grade Com. Ind. Auto. Com. Ind. Auto. Com. Typ. 6 3 30 Max. 12 12 12 6 6 6 50 Unit mA Ind. - 65 µA Auto. - 165 µA mA µA Note: Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VDD = VDD(typ), TA = 25℃ Integrated Silicon Solution, Inc.- www.issi.com Rev. A 12/12/2014 6 IS62/65WV20488EALL IS62/65WV20488EBLL AC CHARACTERISTICS(6) (OVER OPERATING RANGE) READ CYCLE AC CHARACTERISTICS Parameter Symbol Read Cycle Time Address Access Time Output Hold Time tRC tAA tOHA tACS1/tACS2 tDOE tHZOE tLZOE tHZCS//tHZCS2 tLZCS/tLZCS2 , CS2 Access Time Access Time to High-Z Output to Low-Z Output , CS2 to High-Z Output , CS2 to Low-Z Output 45ns Min 45 8 5 10 55ns Max 45 45 22 18 18 - Min 55 8 5 10 Max 55 55 25 18 18 - unit notes ns ns ns ns ns ns ns ns ns 1,5 1 1 1 1 2 2 2 2 unit notes ns ns ns ns ns ns ns ns ns ns 1,3,5 1,3 1,3 1,3 1,3 1,3,4 1,3 1,3 2,3 2,3 WRITE CYCLE AC CHARACTERISTICS Parameter Symbol Write Cycle Time tWC tSCS1/tSCS2 tAW tHA tSA tPWE tSD tHD tHZWE tLZWE ,CS2 to Write End Address Setup Time to Write End Address Hold from Write End Address Setup Time Pulse Width Data Setup to Write End Data Hold from Write End LOW to High-Z Output HIGH to Low-Z Output 45ns Min 45 35 35 0 0 35 28 0 10 55ns Max 18 - Min 55 40 40 0 0 40 28 0 10 Max 18 - Notes: 1. Tested with the load in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. tHZOE, tHZCS, tHZB, and tHZWE transitions are measured when the output enters a high impedance state. Not 100% tested. 3. The internal write time is defined by the overlap of =LOW, CS2=HIGH, ( or )=LOW, and =LOW. All four conditions must be in valid states to initiate a Write, but any condition can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. 4. tPWE > tHZWE + tSD when OE is LOW. 5. Address inputs must meet VIH and VIL SPEC during this period. Any glitch or unknown inputs are not permitted. Unknown input with standby mode is acceptable. 6. Data retention characteristics are defined later in DATA RETENTION CHARACTERISTICS. Integrated Silicon Solution, Inc.- www.issi.com Rev. A 12/12/2014 7 IS62/65WV20488EALL IS62/65WV20488EBLL AC TEST CONDITIONS (OVER THE OPERATING RANGE) Parameter Input Rise Time Input Fall Time Output Timing Reference Level Output Load Conditions Symbol TR TF VREF Conditions 1.0 1.0 ½ VTM Refer to Figure 1 and 2 Units V/ns V/ns V OUTPUT LOAD CONDITIONS FIGURES Figure1 Figure2 R1 R1 VTM VTM OUTPUT OUTPUT 30pF, including jig and scope Parameters R1 R2 VTM R2 VDD=1.65~1.98V 13500Ω 10800Ω VDD Integrated Silicon Solution, Inc.- www.issi.com Rev. A 12/12/2014 5pF, including jig and scope VDD=2.2~2.7V 16667Ω 15385Ω VDD R2 VDD=2.7~3.6V 1103Ω 1554Ω VDD 8 IS62/65WV20488EALL IS62/65WV20488EBLL TIMING DIAGRAM READ CYCLE NO. 1(1,2) (ADDRESS CONTROLLED) ( = =VIL, CS2= =VIH) tRC ADDRESS tAA tOHA tOHA I/O0-15 PREVIOUS DATA VALID READ CYCLE NO. 2(1,3) ( , CS2, AND Notes: 1. is HIGH for a Read Cycle. 2. The device is continuously selected. , 3. Address is valid prior to or coincident with Low-Z DATA VALID Low-Z CONTROLLED) = Vil. CS2= =VIH. LOW and CS2 HIGH transition. Integrated Silicon Solution, Inc.- www.issi.com Rev. A 12/12/2014 9 IS62/65WV20488EALL IS62/65WV20488EBLL WRITE CYCLE NO. 1 ( CONTROLLED, = HIGH OR LOW) Notes: 1. tHZWE is based on the assumption when tSA=0nS after READ operation. Actual DOUT for tHZWE may not appear if Write Cycle. tHZOE is the time DOUT goes to High-Z after goes high. 2. During this period the I/Os are in output state. Do not apply input signals. WRITE CYCLE NO. 2 ( Controlled: is HIGH During Write Cycle) Notes: 1. tHZWE is based on the assumption when tSA=0nS after READ operation. Actual DOUT for tHZWE may not appear if Write Cycle. tHZOE is the time DOUT goes to High-Z after goes high. 2. During this period the I/Os are in output state. Do not apply input signals. Integrated Silicon Solution, Inc.- www.issi.com Rev. A 12/12/2014 goes high before goes high before 10 IS62/65WV20488EALL IS62/65WV20488EBLL WRITE CYCLE NO. 3 ( CONTROLLED: IS LOW DURING WRITE CYCLE) Notes: If is low during write cycle, tHZWE must be met in the application. Do not apply input signal during this period. Data output from the previous READ operation will drive IO BUS. Integrated Silicon Solution, Inc.- www.issi.com Rev. A 12/12/2014 11 IS62/65WV20488EALL IS62/65WV20488EBLL DATA RETENTION CHARACTERISTICS Symbol Parameter Test Condition OPTION VDR VDD for Data Retention See Data Retention Waveform IS62(5)WV20488EALL IS62(5)WV20488EBLL Data Retention Current VDD= VDR(min), (1) 0V ≤ CS2 ≤ 0.2V, or (2) ≥ VDD – 0.2V, CS2 ≥ VDD - 0.2V IDR Min. Typ.(2) Max. Unit 1.5 - V 1.5 - V uA Com. - - 50 Ind. - - 65 Auto - - 165 tSDR Data Retention Setup Time See Data Retention Waveform 0 - - ns tRDR Recovery Time See Data Retention Waveform tRC - - ns Note: 1. If >VDD–0.2V, all other inputs including CS2 must meet this condition. 2. Typical values are measured at VDD=VDR(min), TA = 25℃ and not 100% tested. DATA RETENTION WAVEFORM ( CONTROLLED) tSDR DATA RETENTION MODE tRDR VDD VDR CS1 > VDD-0.2V GND DATA RETENTION WAVEFORM (CS2 CONTROLLED) DATA RETENTION MODE VDD CS2 tRDR tSDR VDR CS2 < 0.2V GND Integrated Silicon Solution, Inc.- www.issi.com Rev. A 12/12/2014 12 IS62/65WV20488EALL IS62/65WV20488EBLL ORDERING INFORMATION: IS62WV20488EALL 1.65V-1.98V Industrial Range (-40C to +85C) Speed (ns) 55 Order Part No IS62WV20488EALL-55BI IS62WV20488EALL-55BLI Package 48-pin mini BGA (6mmx8mm) 48-pin mini BGA (6mmx8mm), Lead-free ORDERING INFORMATION: IS62WV20488EBLL 2.2V-3.6V Industrial Range (-40C to +85C) Speed (ns) 45 55 Order Part No IS62WV20488EBLL-45BI IS62WV20488EBLL-45BLI IS62WV20488EBLL-55BI IS62WV20488EBLL-55BLI Package 48-pin mini BGA (6mmx8mm) 48-pin mini BGA (6mmx8mm), Lead-free 48-pin mini BGA (6mmx8mm) 48-pin mini BGA (6mmx8mm), Lead-free ORDERING INFORMATION: IS65WV20488EBLL 2.2V-3.6V Automotive Range (-40C to +125C) Speed (ns) 55 Order Part No IS65WV20488EBLL-55BA3 IS65WV20488EBLL-55BLA3 Integrated Silicon Solution, Inc.- www.issi.com Rev. A 12/12/2014 Package 48-pin mini BGA (6mmx8mm) 48-pin mini BGA (6mmx8mm), Lead-free 13 IS62/65WV20488EALL IS62/65WV20488EBLL Integrated Silicon Solution, Inc.- www.issi.com Rev. A 12/12/2014 14