IS62WV20488FBLL-45BLI

IS62WV20488FALL/BLL IS65WV20488FALL/BLL 2Mx8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM KEY FEATURES  High-speed access time: 45ns, 55ns  CMOS low power operation – Operating Current: 35mA (max.) – CMOS standby Current: 5.5uA (typ.)  TTL compatible interface levels  Single power supply –1.65V-2.2V VDD (IS62/65WV20488FALL) – 2.2V-3.6V VDD (IS62/65WV20488FBLL)  Three state outputs  Industrial and Automotive temperature support  Lead-free available MAY 2020 DESCRIPTION The ISSI IS62/65WV20488FALL/BLL are high-speed, 16M bit static RAMs organized as 2M words by 8 bits. It is fabricated using ISSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields highperformance and low power consumption devices. When CS1# is HIGH (deselected) or when CS2 is LOW (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs. The active LOW Write Enable (WE#) controls both writing and reading of the memory. The IS62/65WV20488FALL/BLL are packaged in the JEDEC standard 48-pin mini BGA. FUNCTIONAL BLOCK DIAGRAM DECODER A0 – A20 2M x 8 MEMORY ARRAY VDD GND I/O0 – I/O7 CS2 CS1# OE# WE# I/O DATA CIRCUIT COLUMN I/O CONTROL CIRCUIT Copyright © 2020 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc.- www.issi.com Rev. A5 05/01/2020 1 IS62WV20488FALL IS65WV20488FBLL PIN CONFIGURATIONS 48-Pin mini BGA (6mm x 8mm) 1 2 3 4 5 6 NC OE# A0 A1 A2 CS2 B NC NC A3 A4 CS1# NC C I/O0 NC A5 A6 NC I/O4 D VSS I/O1 A17 A7 I/O5 VDD E VDD I/O2 NC A16 I/O6 VSS F I/O3 NC A14 A15 NC I/O7 G NC A20 A12 A13 WE# NC H A18 A8 A9 A10 A11 A19 A PIN DESCRIPTIONS A0-A20 I/O0-I/O7 CS1#, CS2 OE# WE# NC VDD VSS Address Inputs Data Inputs/Outputs Chip Enable Inputs Output Enable Input Write Enable Input No Connection Power Ground Integrated Silicon Solution, Inc.- www.issi.com Rev. A5 05/01/2020 2 IS62WV20488FALL IS65WV20488FBLL FUNCTION DESCRIPTION SRAM is one of random access memories. SRAM has three different modes supported. Each function is described below with Truth Table. STANDBY MODE Device enters standby mode when deselected (CS1# HIGH or CS2 LOW). The input and output pins (I/O0-7) are placed in a high impedance state. CMOS input in this mode will maximize saving power. WRITE MODE Write operation issues with Chip selected (CS1# LOW and CS2 HIGH) and Write Enable (WE#) input LOW. The input and output pins (I/O0-7) are in data input mode. Output buffers are closed during this time even if OE# is LOW. READ MODE Read operation issues with Chip selected (CS1# LOW and CS2 HIGH) and Write Enable (WE#) input HIGH. When OE# is LOW, output buffer turns on to make data output. Any input to I/O pins during READ mode is not permitted. In the READ mode, output buffers can be turned off by pulling OE# HIGH. In this mode, internal device operates as READ but I/Os are in a high impedance state. Since device is in READ mode, active current is used. TRUTH TABLE Mode Not Selected Output Disabled Write Read CS1# CS2 WE# OE# I/O0-I/O7 VDD Current H X L L L X L H H H X X H L H X X H X L High-Z High-Z High-Z DIN DOUT ISB2 ISB2 ICC,ICC1 ICC,ICC1 ICC,ICC1 Integrated Silicon Solution, Inc.- www.issi.com Rev. A5 05/01/2020 3 IS62WV20488FALL IS65WV20488FBLL ABSOLUTE MAXIMUM RATINGS AND OPERATING RANGE ABSOLUTE MAXIMUM RATINGS(1) Symbol Parameter Vter m Terminal Voltage with Respect to GND VDD V DD Related to GND tStg Storage Temperature Value –0.5 to VDD + 0.5 –0.3 to 4.0 –65 to +150 PT 1.0 Power Dissipation Unit V V C W Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. OPERATING RANGE(1) Range Ambient Temperature Commercial Industrial Automotive Commercial Industrial Automotive Note: 1. 0C to +70C -40C to +85C -40C to +125C 0C to +70C -40C to +85C -40C to +125C PART NUMBER ~ALL ~BLL SPEED (MAX) VDD(MIN) VDD(TYP) VDD(MAX) 55 ns 55 ns 55 ns 45ns 45ns 55ns 1.65V 1.65V 1.65V 2.2V 2.2V 2.2V 1.8V 1.8V 1.8V 3.0V 3.0V 3.0V 2.2V 2.2V 2.2V 3.6V 3.6V 3.6V Full device AC operation assumes a 100 µs ramp time from 0 to Vcc(min) and 200 µs wait time after Vcc stabilization. PIN CAPACITANCE (1) Parameter Input capacitance DQ capacitance (IO0–IO7) Symbol CIN CI/O Test Condition TA = 25°C, f = 1 MHz, VDD = VDD(typ) Max 6 8 Units pF pF Note: 2. These parameters are guaranteed by design and tested by a sample basis only. THERMAL CHARACTERISTICS (1) Parameter Thermal resistance (junction to ambient) Thermal resistance (junction to pins) Thermal resistance (junction to case) Symbol RθJA RθJB RθJC Test Conditions Still air, four-layer printed circuit board 48-ball BGA 48.4 23.3 10.8 Units °C/W °C/W °C/W Note: 1. These parameters are guaranteed by design and tested by a sample basis only. Integrated Silicon Solution, Inc.- www.issi.com Rev. A5 05/01/2020 4 IS62WV20488FALL IS65WV20488FBLL AC TEST CONDITIONS (OVER THE OPERATING RANGE) Parameter Unit (1.65V~2.2V) Input Pulse Level 0V to VDD Unit (2.2V~3.6V) 0V to VDD Input Rise and Fall Time 1V/ns 1V/ns Output Timing Reference Level 0.9V ½ VDD R1 13500 1005 R2 10800 820 VTM 1.8V VDD Output Load Conditions Refer to Figure 1 and 2 OUTPUT LOAD CONDITIONS FIGURES FIGURE 1 FIGURE 2 R1 R1 VTM VTM OUTPUT OUTPUT 30pF, Including jig and scope R2 Integrated Silicon Solution, Inc.- www.issi.com Rev. A5 05/01/2020 5pF, Including jig and scope R2 5 IS62WV20488FALL IS65WV20488FBLL DC ELECTRICAL CHARACTERISTICS IS62(5)WV20488FALL DC ELECTRICAL CHARACTERISTICS- I (OVER THE OPERATING RANGE) VDD = 1.65V ~ 2.2V Symbol VOH VOL VIH(1) VIL(1) ILI ILO Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Output Leakage Test Conditions IOH = -0.1 mA IOL = 0.1 mA Max. — 0.2 VDD + 0.2 0.4 1 1 Unit V V V V µA µA IS62(5)WV20488FBLL DC ELECTRICAL CHARACTERISTICS- I (OVER THE OPERATING RANGE) VDD = 2.2V ~ 3.6V Symbol Parameter Test Conditions Min. Max. VOH Output HIGH Voltage 2.2 ≤ VDD < 2.7, I OH = -0.1 mA 2.0 — 2.7 ≤ VDD ≤ 3.6, IOH = -1.0 mA 2.4 — VOL Output LOW Voltage 2.2 ≤ VDD < 2.7, IOL = 0.1 mA — 0.4 2.7 ≤ VDD ≤ 3.6, IOL = 2.1 mA — 0.4 (1) VIH Input HIGH Voltage 2.2 ≤ VDD < 2.7 1.8 VDD + 0.3 2.7 ≤ VDD ≤ 3.6 2.0 VDD + 0.3 (1) VIL Input LOW Voltage 2.2 ≤ VDD < 2.7 –0.3 0.6 2.7 ≤ VDD ≤ 3.6 –0.3 0.8 ILI Input Leakage GND < VIN < VDD –1 1 ILO Output Leakage GND < VIN < VDD, Output Disabled –1 1 Unit V V V V V V V V µA µA GND < VIN < VDD GND < VIN < VDD, Output Disabled Min. 1.4 — 1.4 –0.2 –1 –1 Notes: 1. VILL(min) = -1.0V AC (pulse width < 10ns). Not 100% tested. VIHH (max) = VDD + 1.0V AC (pulse width < 10ns). Not 100% tested. Notes: 1. VILL(min) = -2.0V AC (pulse width < 10ns). Not 100% tested. VIHH (max) = VDD + 2.0V AC (pulse width < 10ns). Not 100% tested. Integrated Silicon Solution, Inc.- www.issi.com Rev. A5 05/01/2020 6 IS62WV20488FALL IS65WV20488FBLL IS62(5)WV20488FALL DC ELECTRICAL CHARACTERISTICS-II FOR POWER (OVER THE OPERATING RANGE) Symbol Parameter ICC VDD Dynamic Operating Supply Current VDD = VDD(max), IOUT = 0mA, f = fmax, ICC1 VDD Static Operating Supply Current VDD = VDD(max), IOUT = 0mA, f=0 CMOS Standby Current (CMOS Inputs) ISB2 Notes: 1. 2. Grade Typ(1) Max Com. Ind. Auto. A3 Com. Ind. Auto. A3 - 35 35 35 5 5 5 25°C 5.5 9(2) 40°C 6.0 10(2) 70°C 7.5 14 Ind. 85°C 10.5 20 Auto. A3 125°C 25 55 Test Conditions VDD = VDD(max), f = 0, CS1# ≥ VDD - 0.2V or CS2 < 0.2V, VIN ≤ 0.2V or VIN ≥ VDD - 0.2V Com. Unit mA mA µA Typical value indicates the value for the center of distribution at VDD=VDD (Typ.), and not 100% tested. Maximum value at 25°C, 40°C are guaranteed by design, and not 100% tested IS62(5)WV20488FBLL DC ELECTRICAL CHARACTERISTICS-II FOR POWER (OVER THE OPERATING RANGE) Symbol Parameter ICC VDD Dynamic Operating Supply Current VDD = VDD(max), IOUT = 0mA, f = fmax, ICC1 VDD Static Operating Supply Current VDD = VDD(max), IOUT = 0mA, f=0 ISB2 Notes: 1. 2. CMOS Standby Current (CMOS Inputs) Grade Typ(1) Max Com. Ind. Auto. A3 Com. Ind. Auto. A3 - 35 35 35 5 5 5 25°C 5.5 9(2) 40°C 6.0 10(2) 70°C 7.5 14 Ind. 85°C 10.5 20 Auto. A3 125°C 25 55 Test Conditions VDD = VDD(max), f = 0, CS1# ≥ VDD - 0.2V or CS2 < 0.2V, VIN ≤ 0.2V or VIN ≥ VDD - 0.2V Com. Unit mA mA µA Typical value indicates the value for the center of distribution at V DD=VDD (Typ.), and not 100% tested. Maximum value at 25°C, 40°C are guaranteed by design, and not 100% tested. Integrated Silicon Solution, Inc.- www.issi.com Rev. A5 05/01/2020 7 IS62WV20488FALL IS65WV20488FBLL AC CHARACTERISTICS(6) (OVER OPERATING RANGE) READ CYCLE AC CHARACTERISTICS Parameter Symbol Read Cycle Time Address Access Time Output Hold Time CS1#, CS2 Access Time OE# Access Time OE# to High-Z Output OE# to Low-Z Output CS1#, CS2 to High-Z Output CS1#, CS2 to Low-Z Output tRC tAA tOHA tACS1/ACS2 tDOE tHZOE tLZOE tHZCS1/HZCS2 tLZCS/LZCS2 45ns Min Max 45 45 10 45 20 15 5 15 10 - 55ns Min Max 55 55 10 55 25 20 5 20 10 - 45ns Min Max 45 35 35 0 0 35 20 0 15 5 - 55ns Min Min 55 40 40 0 0 40 25 0 20 5 - unit notes ns ns ns ns ns ns ns ns ns 1,5 1 1 1 1 2 2 2 2 unit notes ns ns ns ns ns ns ns ns ns ns 1,3,5 1,3 1,3 1,3 1,3 1,3,4 1,3 1,3 2,3 2,3 WRITE CYCLE AC CHARACTERISTICS Parameter Symbol Write Cycle Time CS1#, CS2 to Write End Address Setup Time to Write End Address Hold from Write End Address Setup Time WE# Pulse Width Data Setup to Write End Data Hold from Write End WE# LOW to High-Z Output WE# HIGH to Low-Z Output tWC tSCS1/SCS2 tAW tHA tSA tPWE tSD tHD tHZWE tLZWE Notes: 1. Tested with the load in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. tHZOE, tHZCS, tHZB, and tHZWE transitions are measured when the output enters a high impedance state. Not 100% tested. 3. The internal write time is defined by the overlap of CS1# = LOW, CS2=HIGH, and WE# = LOW. All four conditions must be in valid states to initiate a Write, but any condition can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. 4. tPWE > tHZWE + tSD when OE# is LOW. 5. Address inputs must meet VIH and VIL SPEC during this period. Any glitch or unknown inputs are not permitted. Unknown input with standby mode is acceptable. 6. Data retention characteristics are defined later in DATA RETENTION CHARACTERISTICS. Integrated Silicon Solution, Inc.- www.issi.com Rev. A5 05/01/2020 8 IS62WV20488FALL IS65WV20488FBLL TIMING DIAGRAM READ CYCLE NO. 1(1) (ADDRESS CONTROLLED) (CS1# = OE# = LOW, CS2 = WE# = HIGH) tRC Address tAA tOHA DQ 0-7 tOHA PREVIOUS DATA VALID LOW-Z DATA VALID Note: 1. The device is continuously selected. READ CYCLE NO. 2(1) (OE# CONTROLLED) tRC ADDRESS tAA tDOE OE# tLZOE tOHA tHZOE CS1# tACS1/tACS2 tHZCS1/ tHZCS2 CS2 tLZCS1/ tLZCS2 DOUT HIGH-Z LOW-Z DATA VALID Note: 1. Address is valid prior to or coincident with CS1# LOW and CS2 HIGH transition. Integrated Silicon Solution, Inc.- www.issi.com Rev. A5 05/01/2020 9 IS62WV20488FALL IS65WV20488FBLL WRITE CYCLE 1(1, 2) (CS1#, CS2 Controlled, OE# = HIGH or LOW) tWC ADDRESS tSCS1 tSA CS1# tHA tSCS2 CS2 tAW tPWE WE# tHZWE DATA UNDEFINED DOUT HIGH-Z (1) tSD DATA UNDEFINED DIN (2) tLZWE tHD DATA IN VALID Notes: 1. tHZWE is based on the assumption when tSA=0nS after READ operation. Actual DOUT for tHZWE may not appear if OE# goes high before Write Cycle. tHZOE is the time DOUT goes to High-Z after OE# goes high 2. During this period the I/Os are in output state. Do not apply input signals. WRITE CYCLE NO. 2(1,2) (WE# CONTROLLED: OE# IS HIGH DURING WRITE CYCLE) tWC ADDRESS tSCS1 CS1# tSCS2 CS2 WE# OE# DOUT tHA tAW tPWE tSA tHZOE DATA UNDEFINED HIGH-Z (1) tSD DIN DATA UNDEFINED (2) tHD DATA IN VALID Notes: 1. tHZOE is the time DOUT goes to High-Z after OE# goes high. 2. During this period the I/Os are in output state. Do not apply input signals. Integrated Silicon Solution, Inc.- www.issi.com Rev. A5 05/01/2020 10 IS62WV20488FALL IS65WV20488FBLL WRITE CYCLE NO. 3(1) (WE# CONTROLLED: OE# IS LOW DURING WRITE CYCLE) tWC ADDRESS tSCS1 CS1# tHA tSCS2 CS2 tAW WE# tPWE tSA tHZWE DOUT DATA UNDEFINED (1) HIGH-Z tSD DIN Note: 1. DATA UNDEFINED (1) tLZWE tHD DATA IN VALID If OE# is low during write cycle, tHZWE must be met in the application. Do not apply input signal during this period. Data output from the previous READ operation will drive IO BUS. Integrated Silicon Solution, Inc.- www.issi.com Rev. A5 05/01/2020 11 IS62WV20488FALL IS65WV20488FBLL DATA RETENTION CHARACTERISTICS Symbol Min. Typ.(1) Max. Unit 1.5 - - V 25°C - 5.5 13 85°C - - 19 125°C - - 52 See Data Retention Waveform 0 - - ns See Data Retention Waveform tRC - - ns Parameter VDR IDR Test Condition VDD for Data Retention See Data Retention Waveform Data Retention Current VDD = VDR (min), CS1# ≥ VDD – 0.2V or CS2 ≤ 0.2V uA VIN ≤ 0.2V or VIN ≥ VDD - 0.2V Data Retention Setup Time Recovery Time tSDR (2) tRDR Notes: 1. 2. Typical value indicates the value for the center of distribution at V DD = VDR (min.), and not 100% tested. VDD power down slope must be longer than 100 us/volt when enter into Data Retention Mode. DATA RETENTION WAVEFORM (CS1# CONTROLLED) tSDR Data Retention Mode tRDR VDD VDR CS1# > VDD – 0.2V CS1# GND DATA RETENTION WAVEFORM (CS2 CONTROLLED) tSDR Data Retention Mode tRDR VDD CS2 VDR CS2 < 0.2V GND Integrated Silicon Solution, Inc.- www.issi.com Rev. A5 05/01/2020 12 IS62WV20488FALL IS65WV20488FBLL ORDERING INFORMATION IS62/65WV20488FALL (1.65V - 2.2V) Industrial Range: –40°C to +85°C Speed (ns) 55 55 Order Part No. Package IS62WV20488FALL-55BI IS62WV20488FALL-55BLI mini BGA (6mm x 8mm) mini BGA (6mm x 8mm), Lead-free AUTOMOTIVE RANGE (A3): –40°C TO +125°C Speed (ns) 55 55 Order Part No. Package IS65WV20488FALL-55BA3 IS65WV20488FALL-55BLA3 mini BGA (6mm x 8mm) mini BGA (6mm x 8mm), Lead-free IS62/65WV20488BLL (2.2V – 3.6V) Industrial Range: –40°C to +85°C Speed (ns) Order Part No. Package 45 45 IS62WV20488FBLL-45BI IS62WV20488FBLL-45BLI mini BGA (6mm x 8mm) mini BGA (6mm x 8mm), Lead-free 55 55 IS62WV20488FBLL-55BI IS62WV20488FBLL-55BLI mini BGA (6mm x 8mm) mini BGA (6mm x 8mm), Lead-free Automotive Range (A3): –40°C to +125°C Speed (ns) 55 55 Order Part No. Package IS65WV20488FBLL-55BA3 IS65WV20488FBLL-55BLA3 mini BGA (6mm x 8mm) mini BGA (6mm x 8mm), Lead-free Integrated Silicon Solution, Inc.- www.issi.com Rev. A5 05/01/2020 13 IS62WV20488FALL IS65WV20488FBLL PACKAGE INFORMATION Integrated Silicon Solution, Inc.- www.issi.com Rev. A5 05/01/2020 14