IS62WV25616ALL

IS62WV25616ALL IS62WV25616BLL 256K x 16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC SRAM FEATURES • High-speed access time: 55ns, 70ns • CMOS low power operation 36 mW (typical) operating 9 µW (typical) CMOS standby • TTL compatible interface levels • Single power supply 1.65V--2.2V VDD (IS62WV25616ALL) 2.5V--3.6V VDD (IS62WV25616BLL) • Fully static operation: no clock or refresh required • Three state outputs • Data control for upper and lower bytes • Industrial temperature available • Lead-free available ISSI MAY 2005 ® DESCRIPTION The ISSI IS62WV25616ALL/IS62WV25616BLL are highspeed, low power, 4M bit SRAMs organized as 256K words by 16 bits. It is fabricated using ISSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields highperformance and low power consumption devices. When CS1 is HIGH (deselected) or when CS1 is LOW and both LB and UB are HIGH, the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs. The active LOW Write Enable (WE) controls both writing and reading of the memory. A data byte allows Upper Byte (UB) and Lower Byte (LB) access. The IS62WV25616ALL/IS62WV25616BLL are packaged in the JEDEC standard 44-Pin TSOP (TYPE II) and 48-pin mini BGA (6mmx8mm). FUNCTIONAL BLOCK DIAGRAM A0-A17 DECODER 256K x 16 MEMORY ARRAY VDD GND I/O0-I/O7 Lower Byte I/O8-I/O15 Upper Byte I/O DATA CIRCUIT COLUMN I/O CS1 OE WE UB LB CONTROL CIRCUIT Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. C 05/02/05 1 IS62WV25616ALL, IS62WV25616BLL PIN CONFIGURATIONS 48- ball mini BGA (6mm x 8mm) (Package Code B) 1 2 3 4 5 6 ISSI 44-Pin mini TSOP (Type II) (Package Code T) A4 A3 A2 A1 A0 CS1 I/O0 I/O1 I/O2 I/O3 VDD GND I/O4 I/O5 I/O6 I/O7 WE A16 A15 A14 A13 A12 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE UB LB I/O15 I/O14 I/O13 I/O12 GND VDD I/O11 I/O10 I/O9 I/O8 NC A8 A9 A10 A11 A17 ® A B C D E F G H LB I/O8 I/O9 GND VDD I/O14 I/O15 NC OE UB I/O10 I/O11 I/O12 I/O13 NC A8 A0 A3 A5 A17 NC A14 A12 A9 A1 A4 A6 A7 A16 A15 A13 A10 A2 CSI I/O1 I/O3 I/O4 I/O5 WE A11 NC I/O0 I/O2 VDD GND I/O6 I/O7 NC PIN DESCRIPTIONS A0-A17 I/O0-I/O15 CS1 OE WE LB UB NC VDD GND Address Inputs Data Inputs/Outputs Chip Enable Input Output Enable Input Write Enable Input Lower-byte Control (I/O0-I/O7) Upper-byte Control (I/O8-I/O15) No Connection Power Ground 2 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. C 05/02/05 IS62WV25616ALL, IS62WV25616BLL TRUTH TABLE Mode Not Selected Output Disabled Read WE X X H H H H H L L L CS1 H X L L L L L L L L OE X X H H L L L X X X LB X H L X L H L L H L UB X H X L H L L H L L I/O PIN I/O0-I/O7 I/O8-I/O15 High-Z High-Z High-Z High-Z DOUT High-Z DOUT DIN High-Z DIN High-Z High-Z High-Z High-Z High-Z DOUT DOUT High-Z DIN DIN ISSI VDD Current ISB1, ISB2 ISB1, ISB2 ICC ICC ICC ® Write ICC ABSOLUTE MAXIMUM RATINGS(1) Symbol VTERM VDD TSTG PT Parameter Terminal Voltage with Respect to GND VDD Related to GND Storage Temperature Power Dissipation Value –0.2 to VDD+0.3 –0.2 to VDD+0.3 –65 to +150 1.0 Unit V V °C W Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. OPERATING RANGE (VDD) Range Commercial Industrial Ambient Temperature 0°C to +70°C –40°C to +85°C IS62WV25616ALL 1.65V - 2.2V 1.65V - 2.2V IS62WV25616BLL 2.5V-3.6V 2.5V-3.6V DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Symbol Parameter VOH VOL VIH VIL(1) ILI ILO Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Output Leakage GND ≤ VIN ≤ VDD GND ≤ VOUT ≤ VDD, Outputs Disabled Test Conditions IOH = -0.1 mA IOH = -1 mA IOL = 0.1 mA IOL = 2.1 mA VDD 1.65-2.2V 2.5-3.6V 1.65-2.2V 2.5-3.6V 1.65-2.2V 2.5-3.6V 1.65-2.2V 2.5-3.6V Min. 1.4 2.2 — — 1.4 2.2 –0.2 –0.2 –1 –1 Max. — — 0.2 0.4 VDD + 0.2 VDD + 0.3 0.4 0.6 1 1 Unit V V V V V V V V µA µA Notes: 1. VIL (min.) = –1.0V for pulse width less than 10 ns. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. C 05/02/05 3 IS62WV25616ALL, IS62WV25616BLL IS62WV25616ALL, POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) Symbol ICC ICC1 Parameter VDD Dynamic Operating Supply Current Operating Supply Current TTL Standby Current (TTL Inputs) Test Conditions VDD = Max., IOUT = 0 mA, f = fMAX VDD = Max., CS1 = 0.2V WE = VDD-0.2V f=1MHZ VDD = Max., VIN = VIH or VIL CS1 = VIH , f = 1 MHZ Com. Ind. Com. Ind. Com. Ind. OR ULB Control ISB2 CMOS Standby Current (CMOS Inputs) VDD = Max., VIN = VIH or VIL CS1 = VIL, f = 0, UB = VIH, LB = VIH VDD = Max., Com. CS1 ≥ VDD – 0.2V, Ind. VIN ≥ VDD – 0.2V, or VIN ≤ 0.2V, f = 0 OR VDD = Max., CS1 = VIL, VIN ≤ 0.2V, f = 0; UB / LB = VDD – 0.2V Max. 70 25 30 10 10 0.35 0.35 ISSI Unit mA mA ® ISB1 mA 15 15 µA ULB Control IS62WV25616BLL, POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) Symbol ICC ICC1 Parameter VDD Dynamic Operating Supply Current Operating Supply Current TTL Standby Current (TTL Inputs) Test Conditions VDD = Max., IOUT = 0 mA, f = fMAX VDD = Max., CS1 = 0.2V WE = VDD-0.2V f=1MHZ VDD = Max., VIN = VIH or VIL CS1 = VIH, f = 1 MHZ Com. Ind. Com. Ind. Com. Ind. OR ULB Control ISB2 CMOS Standby Current (CMOS Inputs) VDD = Max., VIN = VIH or VIL CS1 = VIL, f = 0, UB = VIH, LB = VIH VDD = Max., Com. CS1 ≥ VDD – 0.2V, Ind. VIN ≥ VDD – 0.2V, or VIN ≤ 0.2V, f = 0 OR VDD = Max., CS1 = VIL, VIN ≤ 0.2V, f = 0; UB / LB = VDD – 0.2V Max. 55 40 45 15 15 0.35 0.35 Max. 70 35 40 15 15 0.35 0.35 Unit mA mA ISB1 mA 15 15 15 15 µA ULB Control 4 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. C 05/02/05 IS62WV25616ALL, IS62WV25616BLL CAPACITANCE(1) Symbol CIN COUT Parameter Input Capacitance Input/Output Capacitance Conditions VIN = 0V VOUT = 0V Max. 8 10 Unit pF pF ISSI ® Note: 1. Tested initially and after any design or process changes that may affect these parameters. AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load IS62WV25616ALL (Unit) 0.4V to VDD-0.2V 5 ns VREF See Figures 1 and 2 IS62WV25616BLL (Unit) 0.4V to VDD-0.3V 5ns VREF See Figures 1 and 2 IS62WV25616ALL 1.65V-2.2V R1(Ω) R2(Ω) VREF VTM 3070 3150 0.9V 1.8V IS62WV25616BLL 2.5V - 3.6V 3070 3150 1.5V 2.8V AC TEST LOADS R1 VTM VTM R1 OUTPUT 30 pF Including jig and scope R2 OUTPUT 5 pF Including jig and scope R2 Figure 1 Figure 2 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. C 05/02/05 5 IS62WV25616ALL, IS62WV25616BLL READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter Read Cycle Time Address Access Time Output Hold Time CS1 Access Time OE Access Time (2) ISSI 55 ns Min. Max. 55 — 10 — — — 5 0 10 — 0 0 — 55 — 55 25 20 — 20 — 55 20 — 70 ns Min. Max. 70 — 10 — — — 5 0 10 — 0 0 — 70 — 70 35 25 — 25 — 70 25 — Unit ns ns ns ns ns ns ns ns ns ns ns ns ® tRC tAA tOHA tACS1 tDOE tHZOE tLZOE(2) tHZCS1 tLZCS1 tBA tHZB tLZB OE to High-Z Output OE to Low-Z Output CS1 to High-Z Output CS1 to Low-Z Output LB, UB Access Time LB, UB to High-Z Output LB, UB to Low-Z Output Notes: 1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V/1.5V, input pulse levels of 0.4 to VDD-0.2V/VDD-0.3V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 6 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. C 05/02/05 IS62WV25616ALL, IS62WV25616BLL ISSI ® AC WAVEFORMS READ CYCLE NO. 1(1,2) (Address Controlled) (CS1 = OE = VIL, WE = VIH, UB or LB = VIL) tRC ADDRESS tAA tOHA tOHA DATA VALID DOUT PREVIOUS DATA VALID READ CYCLE NO. 2(1,3) (CS1, OE, AND UB/LB Controlled) tRC ADDRESS tAA tOHA OE tDOE tHZOE CS1 tACE1 tLZOE tLZCE1 tHZCS1 LB, UB tBA tLZB tHZB DOUT HIGH-Z DATA VALID Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CS1, UB, or LB = VIL. WE=VIH. 3. Address is valid prior to or coincident with CS1 LOW transition. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. C 05/02/05 7 IS62WV25616ALL, IS62WV25616BLL WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range) Symbol Parameter Write Cycle Time CS1 to Write End Address Setup Time to Write End Address Hold from Write End Address Setup Time LB, UB Valid to End of Write WE Pulse Width Data Setup to Write End Data Hold from Write End WE LOW to High-Z Output WE HIGH to Low-Z Output Min. 55 45 45 0 0 45 40 25 0 — 5 55 ns Max. — — — — — — — — — 20 — Min. 70 60 60 0 0 60 50 30 0 — 5 70 ns Max. — — — — — — — — — 20 — ISSI Unit ns ns ns ns ns ns ns ns ns ns ns ® tWC tSCS1 tAW tHA tSA tPWB tPWE tSD tHD tHZWE(3) tLZWE(3) Notes: 1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V/1.5V, input pulse levels of 0.4V to VDD-0.2V/VDD-0.3V and output loading specified in Figure 1. 2. The internal write time is defined by the overlap of CS1 LOW and UB or LB, and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. 3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 8 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. C 05/02/05 IS62WV25616ALL, IS62WV25616BLL AC WAVEFORMS WRITE CYCLE NO. 1(1,2) (CS1 Controlled, OE = HIGH or LOW) tWC ISSI ® ADDRESS tSCS1 tHA CS1 tAW WE LB, UB tSA tHZWE tPWE tPWB tLZWE HIGH-Z DOUT DATA UNDEFINED tSD tHD DIN DATA-IN VALID Notes: 1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CS1 and WE inputs and at least one of the LB and UB inputs being in the LOW state. 2. WRITE = (CS1) [ (LB) = (UB) ] (WE). WRITE CYCLE NO. 2 (WE Controlled: OE is HIGH During Write Cycle) tWC ADDRESS OE tSCS1 tHA CS1 tAW WE t PWE LB, UB tSA tHZWE HIGH-Z tLZWE DOUT DATA UNDEFINED tSD tHD DIN DATA-IN VALID Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. C 05/02/05 9 IS62WV25616ALL, IS62WV25616BLL WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle) tWC ISSI ® ADDRESS OE tSCS1 tHA CS1 tAW WE t PWE LB, UB tSA tHZWE HIGH-Z tLZWE DOUT DATA UNDEFINED tSD tHD DIN DATA-IN VALID WRITE CYCLE NO. 4 (UB/LB Controlled) t WC ADDRESS ADDRESS 1 t WC ADDRESS 2 OE t SA CS1 LOW WE t HA t SA t PBW t PBW WORD 2 t HA UB, LB WORD 1 t HZWE DOUT HIGH-Z t LZWE t HD DATAIN VALID DATA UNDEFINED t SD DIN t SD DATAIN VALID t HD UB_CSWR4.eps 10 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. C 05/02/05 IS62WV25616ALL, IS62WV25616BLL DATA RETENTION SWITCHING CHARACTERISTICS Symbol Parameter VDD for Data Retention Data Retention Current Data Retention Setup Time Recovery Time Test Condition See Data Retention Waveform VDD = 1.2V, CS1 ≥ VDD – 0.2V See Data Retention Waveform See Data Retention Waveform Min. 1.2 — 0 Max. 3.6 15 — — Unit V µA ns ns ISSI ® VDR IDR tSDR tRDR tRC DATA RETENTION WAVEFORM (CS1 Controlled) tSDR VDD Data Retention Mode tRDR VDR CS1 ≥ VDD - 0.2V CS1 GND Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. C 05/02/05 11 IS62WV25616ALL, IS62WV25616BLL ORDERING INFORMATION IS62WV25616ALL (1.65V-2.2V) Commercial Range: 0°C to +70°C Speed (ns) 70 Order Part No. IS62WV25616ALL-70T Package TSOP ISSI ® Industrial Range: –40°C to +85°C Speed (ns) 70 70 Order Part No. IS62WV25616ALL-70TI IS62WV25616ALL-70BI Package TSOP mini BGA (6mmx8mm) IS62WV25616BLL (2.5V - 3.6V) Commercial Range: 0°C to +70°C Speed (ns) 55 70 Order Part No. IS62WV25616BLL-55T IS62WV25616BLL-70T Package TSOP TSOP Industrial Range: –40°C to +85°C Speed (ns) 55 55 55 55 Order Part No. IS62WV25616BLL-55TI IS62WV25616BLL-55TLI IS62WV25616BLL-55BI IS62WV25616BLL-55BLI Package TSOP TSOP, Lead-free mini BGA (6mmx8mm) mini BGA (6mmx8mm), Lead-free 12 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. C 05/02/05 PACKAGING INFORMATION Mini Ball Grid Array Package Code: B (48-pin) Top View 1 2 3 4 56 6 ISSI Bottom View φ b (48x) ® 5 4 3 2 1 A B C D D E F G H D1 e A B C D E F G H e E E1 A2 SEATING PLANE A1 A Notes: 1. Controlling dimensions are in millimeters. mBGA - 6mm x 8mm MILLIMETERS Sym. N0. Leads A A1 A2 D D1 E E1 e b — 0.24 0.60 7.90 5.90 mBGA - 8mm x 10mm INCHES Min. Typ. Max. Sym. N0. Leads MILLIMETER Min. Typ. Max. 48 — 0.24 0.60 9.90 7.90 — — — — — 1.20 0.30 — 10.10 8.10 — INCHES Min. Typ. Max. Min. Typ. Max. 48 — — — — — 1.20 0.30 — 8.10 6.10 — 0.009 0.024 0.311 0.232 — — — — — 0.047 0.012 — 0.319 0.240 A A1 A2 D D1 E E1 e b — — — — — 0.047 0.012 — 0.398 0.319 0.009 0.024 0.390 0.311 5.25 BSC 3.75 BSC 0.75 BSC 0.30 0.35 0.40 0.207 BSC 0.148 BSC 0.030 BSC 0.012 0.014 0.016 5.25 BSC 3.75 BSC 0.75 BSC 0.30 0.35 0.40 0.207 BSC 0.148 BSC 0.030 BSC 0.012 0.014 0.016 Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. D 01/15/03 PACKAGING INFORMATION Plastic TSOP Package Code: T (Type II) ISSI Notes: 1. Controlling dimension: millimieters, unless otherwise specified. 2. BSC = Basic lead spacing between centers. 3. Dimensions D and E1 do not include mold flash protrusions and should be measured from the bottom of the package. 4. Formed leads shall be planar with respect to one another within 0.004 inches at the seating plane. ® N N/2+1 E1 E 1 D N/2 SEATING PLANE ZD A . e b L A1 α C Symbol Ref. Std. No. Leads A A1 b C D E1 E e L ZD α Millimeters Min Max Inches Min Max Plastic TSOP (T - Type II) Millimeters Inches Min Max Min Max 44 — 1.20 — 0.047 0.05 0.15 0.002 0.006 0.30 0.45 0.012 0.018 0.12 0.21 0.005 0.008 18.31 18.52 0.721 0.729 10.03 10.29 0.395 0.405 11.56 11.96 0.455 0.471 0.80 BSC 0.032 BSC 0.41 0.60 0.016 0.024 0.81 REF 0.032 REF 0° 5° 0° 5° Millimeters Min Max 50 — 1.20 0.05 0.15 0.30 0.45 0.12 0.21 20.82 21.08 10.03 10.29 11.56 11.96 0.80 BSC 0.40 0.60 0.88 REF 0° 5° Inches Min Max (N) 32 — 1.20 — 0.047 0.05 0.15 0.002 0.006 0.30 0.52 0.012 0.020 0.12 0.21 0.005 0.008 20.82 21.08 0.820 0.830 10.03 10.29 0.391 0.400 11.56 11.96 0.451 0.466 1.27 BSC 0.050 BSC 0.40 0.60 0.016 0.024 0.95 REF 0.037 REF 0° 5° 0° 5° — 0.047 0.002 0.006 0.012 0.018 0.005 0.008 0.820 0.830 0.395 0.405 0.455 0.471 0.031 BSC 0.016 0.024 0.035 REF 0° 5° Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. F 06/18/03