IS62WV2568EBLL-45BLI

IS62WV2568EALL IS62/65WV2568EBLL MARCH 2018 256Kx8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM KEY FEATURES DESCRIPTION  High-speed access time: 45ns, 55ns  CMOS low power operation – Operating Current: 18 mA (max) at 85°C – CMOS Standby Current: 5.4uA (typ) at 25°C  TTL compatible interface levels  Single power supply The ISSI IS62/65WV2568EALL/EBLL are high-speed, 2M bit static RAMs organized as 256K words by 8 bits. It is fabricated using ISSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields highperformance and low power consumption devices. When CS1# is HIGH (deselected) or when CS2 is LOW (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. –1.65V-2.2V VDD (IS62WV2568EALL) – 2.2V-3.6V VDD (IS62/65WV2568EBLL)  Three state outputs  Industrial and Automotive temperature support  Lead-free available Easy memory expansion is provided by using Chip Enable and Output Enable inputs. The active LOW Write Enable (WE#) controls both writing and reading of the memory. The IS62/65WV2568EALL/EBLL are packaged in the JEDEC standard 32-pin TSOP (TYPE I), sTSOP (TYPE I), and 36-pin mini BGA.. FUNCTIONAL BLOCK DIAGRAM DECODER A0 – A17 256K x 8 MEMORY ARRAY VDD GND I/O0 – I/O7 CS2 CS1# OE# WE# I/O DATA CIRCUIT COLUMN I/O CONTROL CIRCUIT Copyright © 2018 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc.- www.issi.com Rev. B3 03/16/2018 1 IS62WV2568EALL IS62/65WV2568EBLL PIN CONFIGURATIONS 36-Pin mini BGA (6mm x 8mm) 1 A B A0 I/O4 C I/O5 D GND E 2 A1 A2 3 CS2 WE# NC 4 A3 A4 32-Pin TSOP (Type I), STSOP (Type I) 5 A6 A7 A5 I/O6 G I/O7 H A9 A8 I/O0 I/O1 VDD VDD F 6 GND NC A17 OE# CS1# A16 A15 I/O3 A10 A11 A12 A13 A14 I/O2 A11 1 32 OE# A9 2 A8 3 31 30 CS1# I/O7 A10 A13 4 29 WE# 5 28 I/O6 CS2 6 27 I/O5 A15 7 26 I/O4 VDD A17 8 9 25 24 I/O3 GND A16 10 23 I/O2 A14 11 22 I/O1 A12 12 21 A7 13 20 I/O0 A0 A6 A5 14 19 14 A4 16 18 17 A1 A2 A3 PIN DESCRIPTIONS A0-A17 I/O0-I/O7 CS1#, CS2 OE# WE# NC Address Inputs Data Inputs/Outputs Chip Enable Input Output Enable Input Write Enable Input No Connection VDD GND Power Ground Integrated Silicon Solution, Inc.- www.issi.com Rev. B3 03/16/2018 2 IS62WV2568EALL IS62/65WV2568EBLL FUNCTION DESCRIPTION SRAM is one of random access memories. SRAM has three different modes supported. Each function is described below with Truth Table. STANDBY MODE Device enters standby mode when deselected (CS1# HIGH or CS2 LOW). The input and output pins (I/O0-7) are placed in a high impedance state. CMOS input in this mode will maximize saving power. WRITE MODE Write operation issues with Chip selected (CS1# LOW and CS2 HIGH) and Write Enable (WE#) input LOW. The input and output pins(I/O0-7) are in data input mode. Output buffers are closed during this time even if OE# is LOW. READ MODE Read operation issues with Chip selected (CS1# LOW and CS2 HIGH) and Write Enable (WE#) input HIGH. When OE# is LOW, output buffer turns on to make data output. Any input to I/O pins during READ mode is not permitted. In the READ mode, output buffers can be turned off by pulling OE# HIGH. In this mode, internal device operates as READ but I/Os are in a high impedance state. Since device is in READ mode, active current is used. TRUTH TABLE Mode Not Selected Output Disabled Write Read CS1# CS2 WE# OE# I/O0-I/O7 H X L L L X L H H H X X H H L X X H L X High-Z High-Z High-Z DIN DOUT Integrated Silicon Solution, Inc.- www.issi.com Rev. B3 03/16/2018 VDD Current ISB2 ICC ICC ICC 3 IS62WV2568EALL IS62/65WV2568EBLL ABSOLUTE MAXIMUM RATINGS AND OPERATING RANGE ABSOLUTE MAXIMUM RATINGS (1) Symbol Vt erm tBIAS Parameter Terminal Voltage with Respect to GND Temperature Under Bias Value –0.2 to +3.9(VDD+0.3V) –55 to +125 VDD V DD Related to GND –0.2 to +3.9(VDD+0.3V) Storage Temperature –65 to +150 DC Output Current (LOW) 20 tStg IOUT (2) Unit V C V C mA Notes: 1. 2. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. This condition is not per pin. Total current of all pins must meet this value. OPERATING RANGE (1) Range Device Marking Ambient Temperature VDD Commercial IS62WV2568EALL 0C to +70C 1.65V-2.2V Industrial IS62WV2568EALL -40C to +85C 1.65V-2.2V Commercial IS62WV2568EBLL 0C to +70C 2.2V-3.6V Industrial IS62WV2568EBLL -40C to +85C 2.2V-3.6V Automotive IS65WV2568EBLL -40C to +125C 2.2V-3.6V Note: 1. Full device AC operation assumes a 100 µs ramp time from 0 to Vcc(min) and 200 µs wait time after Vcc stabilization. PIN CAPACITANCE (1) Parameter Symbol Input capacitance DQ capacitance (IO0–IO7) CIN CI/O Test Condition TA = 25°C, f = 1 MHz, VDD = VDD(typ) Max Units 10 10 pF pF Note: 1. These parameters are guaranteed by design and tested by a sample basis only. THERMAL CHARACTERISTICS (1) Parameter Thermal resistance from junction to ambient (airflow = 1m/s) Thermal resistance from junction to pins Thermal resistance from junction to case Symbol RθJA RθJB RθJC Rating TBD TBD TBD Units °C/W °C/W °C/W Note: 1. These parameters are guaranteed by design and tested by a sample basis only. Integrated Silicon Solution, Inc.- www.issi.com Rev. B3 03/16/2018 4 IS62WV2568EALL IS62/65WV2568EBLL AC TEST CONDITIONS (OVER THE OPERATING RANGE) Parameter Unit (1.65V~2.2V) 0V to VDD Input Pulse Level Unit (2.2V~3.6V) 0V to VDD Input Rise and Fall Time 1V/ns 1V/ns Output Timing Reference Level 0.9V ½ VDD R1 13500 1005 R2 10800 820 VTM 1.8V VDD Output Load Conditions Refer to Figure 1 and 2 OUTPUT LOAD CONDITIONS FIGURES FIGURE 1 FIGURE 2 R1 R1 VTM VTM OUTPUT OUTPUT 30pF, Including jig and scope R2 Integrated Silicon Solution, Inc.- www.issi.com Rev. B3 03/16/2018 5pF, Including jig and scope R2 5 IS62WV2568EALL IS62/65WV2568EBLL ELECTRICAL CHARACTERISTICS IS62WV2568EALL DC ELECTRICAL CHARACTERISTICS-I (OVER THE OPERATING RANGE) VDD = 1.65V ~ 2.2V Symbol VOH VOL VIH(1) VIL(1) ILI ILO Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Output Leakage Test Conditions I OH = -0.1 mA IOL = 0.1 mA GND < VIN < VDD GND < VIN < VDD, Output Disabled Min. 1.4 — 1.4 –0.2 –1 –1 Max. — 0.2 VDD + 0.2 0.4 1 1 Unit V V V V µA µA Note: 1. VILL(min) = -1.0V AC (pulse width < 10ns). Not 100% tested. VIHH (max) = VDD + 1.0V AC (pulse width < 10ns). Not 100% tested. IS62(5)WV2568EBLL DC ELECTRICAL CHARACTERISTICS-I (OVER THE OPERATING RANGE) VDD = 2.2V ~ 3.6V Symbol VOH Parameter Output HIGH Voltage VOL Output LOW Voltage VIH(1) Input HIGH Voltage VIL(1) Input LOW Voltage ILI ILO Notes: 1. Input Leakage Output Leakage Test Conditions 2.2 ≤ V DD < 2.7, I OH = -0.1 mA 2.7 ≤ V DD ≤ 3.6, I OH = -1.0 mA 2.2 ≤ V DD < 2.7, IOL = 0.1 mA 2.7 ≤ V DD ≤ 3.6, IOL = 2.1 mA 2.2 ≤ V DD < 2.7 2.7 ≤ V DD ≤ 3.6 2.2 ≤ V DD < 2.7 2.7 ≤ V DD ≤ 3.6 GND < VIN < VDD GND < VIN < VDD, Output Disabled Min. 2.0 2.4 — — 1.8 2.2 –0.3 –0.3 –1 –1 Max. — — 0.4 0.4 VDD + 0.3 VDD + 0.3 0.6 0.8 1 1 Unit V V V V V V V V µA µA VILL(min) = -2.0V AC (pulse width < 10ns). Not 100% tested. VIHH (max) = VDD + 2.0V AC (pulse width < 10ns). Not 100% tested. Integrated Silicon Solution, Inc.- www.issi.com Rev. B3 03/16/2018 6 IS62WV2568EALL IS62/65WV2568EBLL IS62WV2568EALL DC ELECTRICAL CHARACTERISTICS-II FOR POWER (OVER THE OPERATING RANGE) Symbol Parameter ICC VDD Dynamic Operating Supply Current VDD=VDD(max), IOUT=0mA, f = fmax CS1# = VIL, CS2 = VIH VDD Static Operating Supply Current VDD=VDD(max), IOUT = 0mA, f=0 CS1# = VIL, CS2 = VIH ICC1 CMOS Standby Current (CMOS Inputs) ISB2 Test Conditions VDD = VDD(max), f = 0, CS1# ≥ VDD - 0.2V or 0V ≤ CS2 ≤ 0.2V or VIN ≤ 0.2V or VIN ≥ VDD - 0.2V Grade Com. 10 15 Ind. - 18 Com. 1 3 Ind. - 3 25°C 5.4 10 45°C 5.6 11 70°C 7.0 13 85°C 7.6 16 Unit mA mA Com. µA Ind. Note: 1. 55ns Typ (1) Max Typical values are measured at VDD = 1.8V, and not 100% tested. IS62(65)WV2568EBLL DC ELECTRICAL CHARACTERISTICS-II FOR POWER (OVER THE OPERATING RANGE) Symbol ICC ICC1 Parameter VDD Dynamic Operating Supply Current VDD Static Operating Supply Current Test Conditions Grade Com. 10 15 Ind. - 18 Auto. - 25 Com. 1 3 Ind. - 3 Auto. - 4 25°C 5.4 10 45°C 5.6 11 70°C 7.0 13 Ind. 85°C 7.6 16 Auto. 125°C 12.6 32 VDD=VDD(max), IOUT=0mA, f = fmax CS1# = VIL, CS2 = VIH VDD=VDD(max), IOUT = 0mA, f=0 CS1# = VIL, CS2 = VIH Com. ISB2 Note: 1. CMOS Standby Current (CMOS Inputs) VDD = VDD(max), f = 0, CS1# ≥ VDD - 0.2V or 0V ≤ CS2 ≤ 0.2V or VIN ≤ 0.2V or VIN ≥ VDD - 0.2V 45/55ns Typ (1) Max Unit mA mA µA Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VDD = 3.0V Integrated Silicon Solution, Inc.- www.issi.com Rev. B3 03/16/2018 7 IS62WV2568EALL IS62/65WV2568EBLL AC CHARACTERISTICS (6) (OVER OPERATING RANGE) READ CYCLE AC CHARACTERISTICS Parameter Symbol Read Cycle Time Address Access Time Output Hold Time CS1#, CS2 Access Time OE# Access Time OE# to High-Z Output OE# to Low-Z Output CS1#, CS2 to High-Z Output CS1#, CS2 to Low-Z Output 45ns 55ns unit notes 55 55 ns ns ns ns 1,5 1 1 1 25 18 18 - ns ns ns ns ns 1 2 2 2 2 unit notes Min Max Min Max tRC tAA tOHA tACS1/ACS2 45 8 - 45 45 55 8 - tDOE tHZOE tLZOE tHZCS1/HZCS2 tLZCS/LZCS2 5 10 22 18 18 - 5 10 WRITE CYCLE AC CHARACTERISTICS Parameter Symbol Write Cycle Time CS1#, CS2 to Write End Address Setup Time to Write End 45ns 55ns Min Max Min Max tWC tSCS1/tSCS2 tAW 45 35 35 - 55 40 40 - ns ns ns 1,3,5 1,3 1,3 Address Hold from Write End Address Setup Time WE# Pulse Width Data Setup to Write End Data Hold from Write End WE# LOW to High-Z Output tHA tSA tPWE tSD tHD tHZWE 0 0 35 28 0 - 18 0 0 40 28 0 - 18 ns ns ns ns ns ns 1,3 1,3 1,3,4 1,3 1,3 2,3 WE# HIGH to Low-Z Output tLZWE 10 - 10 - ns 2,3 Notes: 1 2. 3. 4. 5. 6. Tested with the load in Figure 1. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. tHZOE, tHZCS, tHZB, and tHZWE transitions are measured when the output enters a high impedance state. Not 100% tested. The internal write time is defined by the overlap of CS1# = LOW, CS2=HIGH, and WE# = LOW. All four conditions must be in valid states to initiate a Write, but any condition can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. tPWE > tHZWE + tSD when OE# is LOW. Address inputs must meet VIH and VIL SPEC during this period. Any glitch or unknown inputs are not permitted. Unknown input with standby mode is acceptable. Data retention characteristics are defined later in DATA RETENTION CHARACTERISTICS. Integrated Silicon Solution, Inc.- www.issi.com Rev. B3 03/16/2018 8 IS62WV2568EALL IS62/65WV2568EBLL TIMING DIAGRAM READ CYCLE NO. 1(1) (ADDRESS CONTROLLED) (CS1# = OE# = LOW, CS2 = WE# = HIGH) tRC Address tAA tOHA tOHA DOUT Note: 1. PREVIOUS DATA VALID LOW-Z DATA VALID The device is continuously selected. READ CYCLE NO. 2(1) (OE# CONTROLLED) tRC ADDRESS tAA tDOE OE# tOHA tHZOE tLZOE CS1# tHZCS1/ tHZCS2 tACS1/tACS2 CS2 tLZCS1/ tLZCS2 DOUT HIGH-Z LOW-Z DATA VALID Note: 1. Address is valid prior to or coincident with CS1# LOW and CS2 HIGH transition. Integrated Silicon Solution, Inc.- www.issi.com Rev. B3 03/16/2018 9 IS62WV2568EALL IS62/65WV2568EBLL WRITE CYCLE 1 (1, 2) (CS1#, CS2 Controlled, OE# = HIGH or LOW) tWC ADDRESS tSCS1 tSA CS1# tHA tSCS2 CS2 tAW tPWE WE# tHZWE DATA UNDEFINED DOUT HIGH-Z (1) tSD DATA UNDEFINED DIN (2) tLZWE tHD DATA IN VALID Notes: 1 2. tHZWE is based on the assumption when tSA=0nS after READ operation. Actual DOUT for tHZWE may not appear if OE# goes high before Write Cycle. tHZOE is the time DOUT goes to High-Z after OE# goes high During this period, the I/Os are in output state. Do not apply input signals. WRITE CYCLE NO. 2 (1, 2) (WE# Controlled: OE# is HIGH During Write Cycle) tWC ADDRESS tSCS1 CS1# tSCS2 CS2 WE# tHA tAW tPWE tSA tHZWE DOUT DATA UNDEFINED (1) HIGH-Z tSD DIN Notes: 1. 2. DATA UNDEFINED (2) tLZWE tHD DATA IN VALID tHZOE is the time DOUT goes to High-Z after OE# goes high. During this period, the I/Os are in output state. Do not apply input signals. Integrated Silicon Solution, Inc.- www.issi.com Rev. B3 03/16/2018 10 IS62WV2568EALL IS62/65WV2568EBLL WRITE CYCLE NO. 3(1) (WE# CONTROLLED: OE# IS LOW DURING WRITE CYCLE) tWC ADDRESS tSCS1 tHA CS1# tSCS2 CS2 tAW WE# tPWE tSA tHZWE DOUT DATA UNDEFINED (1) HIGH-Z tSD DIN Note: 1. DATA UNDEFINED (2) tLZWE tHD DATA IN VALID If OE# is low during write cycle, tHZWE must be met in the application. Do not apply input signal during this period. Data output from the previous READ operation will drive IO BUS. Integrated Silicon Solution, Inc.- www.issi.com Rev. B3 03/16/2018 11 IS62WV2568EALL IS62/65WV2568EBLL DATA RETENTION CHARACTERISTICS Symbol VDR IDR Parameter VDD for Data Retention Data Retention Current tSDR Data Retention Setup Time tRDR Recovery Time Notes: 1. 2. Test Condition See Data Retention Waveform VDD= VDR(min), CS1# ≥ VDD – 0.2V(1), or 0V ≤ CS2 ≤ 0.2V, or VIN ≤ 0.2V or VIN ≥ VDD - 0.2V See Data Retention Waveform OPTION Typ.(2) Max. Unit 1.5 - V Com. - 5 uA Ind. - 2 12 Auto 0 - 25 - ns tRC - - ns See Data Retention Waveform Min. If CS1# >VDD–0.2V, all other inputs including CS2 must meet this condition. Typical values are measured at VDD= VDR (min), TA = 25℃ and not 100% tested. DATA RETENTION WAVEFORM (CS1# CONTROLLED) tSDR Data Retention Mode tRDR VDD VDR CS1# > VDD – 0.2V CS1# GND DATA RETENTION WAVEFORM (CS2 CONTROLLED) tSDR Data Retention Mode tRDR VDD CS2 VDR CS2 < 0.2V GND Integrated Silicon Solution, Inc.- www.issi.com Rev. B3 03/16/2018 12 IS62WV2568EALL IS62/65WV2568EBLL ORDERING INFORMATION IS62WV2568EALL (1.65V - 2.2V) Industrial Range: –40°C to +85°C Speed (ns) Order Part No. Package 55 IS62WV2568EALL-55TLI TSOP (Type I, 8x20mm), Lead-free 55 IS62WV2568EALL-55BI mini BGA (6mm x 8mm) 55 IS62WV2568EALL-55BLI mini BGA (6mm x 8mm), Lead-free 55 IS62WV2568EALL-55HLI sTSOP (Type I, 8x13.4mm), Lead-free IS62WV2568EBLL (2.2V - 3.6V) Industrial Range: –40°C to +85°C Speed (ns) Order Part No. Package 45 IS62WV2568EBLL-45TLI TSOP (Type I, 8x20mm), Lead-free 45 IS62WV2568EBLL-45BI mini BGA (6mm x 8mm) 45 IS62WV2568EBLL-45BLI mini BGA (6mm x 8mm), Lead-free 45 IS62WV2568EBLL-45HLI sTSOP (Type I, 8x13.4mm), Lead-free IS65WV2568EBLL (2.2V - 3.6V) Automotive Range (A3): –40°C to +125°C Speed (ns) 55 Order Part No. Package IS65WV2568EBLL-55CTLA3 TSOP (Type I, 8x20mm), Lead-free, Copper Leadframe Integrated Silicon Solution, Inc.- www.issi.com Rev. B3 03/16/2018 13 IS62WV2568EALL IS62/65WV2568EBLL PACKAGE INFORMATION Integrated Silicon Solution, Inc.- www.issi.com Rev. B3 03/16/2018 14 IS62WV2568EALL IS62/65WV2568EBLL Integrated Silicon Solution, Inc.- www.issi.com Rev. B3 03/16/2018 15 IS62WV2568EALL IS62/65WV2568EBLL Integrated Silicon Solution, Inc.- www.issi.com Rev. B3 03/16/2018 16