IS62WV51216GBLL-45TLI

IS62WV51216GALL/BLL IS65WV51216GALL/BLL 512Kx16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM KEY FEATURES  High-speed access time: 45ns, 55ns  CMOS low power operation – Operating Current: 35mA (max.) – CMOS standby Current: 5.5uA (typ.)  TTL compatible interface levels  Single power supply –1.65V-2.2V VDD (IS62/65WV51216GALL) – 2.2V-3.6V VDD (IS62/65WV51216GBLL)  Three state outputs  Commercial, Industrial and Automotive temperature support  Lead-free available FEBURARY 2020 DESCRIPTION The ISSI IS62/65WV51216GALL/BLL are high-speed, low power, 8M bit static RAMs organized as 512K words by 16 bits. It is fabricated using ISSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields high-performance and low power consumption devices. When CS1# is HIGH (deselected) or when CS2 is LOW (deselected) or when CS1# is LOW, CS2 is HIGH and both LB# and UB# are HIGH, the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs. The active LOW Write Enable (WE#) controls both writing and reading of the memory. A data byte allows Upper Byte (UB#) and Lower Byte (LB#) access. The IS62/65WV51216GALL/BLL are packaged in the JEDEC standard 48-Pin TSOP (TYPE I). FUNCTIONAL BLOCK DIAGRAM A0 – A18(19) DECODER 512K x 16 MEMORY ARRAY VDD GND I/O0 – I/O7 Lower Byte I/O8 – I/O15 Upper Byte BYTE# CS2 CS1# OE# WE# UB# LB# I/O DATA CIRCUIT COLUMN I/O CONTROL CIRCUIT Copyright © 2020 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc.- www.issi.com Rev. A4 02/11/2020 1 IS62WV51216GALL/BLL IS65WV51216GALL/BLL PIN CONFIGURATIONS 48-Pin TSOP (TYPE I) PIN DESCRIPTIONS 1 48 A16 A14 2 47 BYTE# A13 3 VSS A12 4 46 45 A11 5 44 I/O7 A10 6 7 43 42 I/O14 A9 A15 IO15,A19 I/O6 A8 8 41 I/O13 NC 9 40 I/O5 NC 39 I/O12 WE# 10 11 38 I/O4 CS2 12 37 VDD NC 13 36 I/O11 UB# 14 35 I/O3 LB# 15 34 I/O10 A18 16 33 I/O2 A17 32 I/O9 A7 17 18 31 I/O1 A6 19 30 I/O8 A5 A4 20 29 I/O0 21 28 OE# A3 22 27 VSS A2 23 26 CS1# A1 24 25 A0 Integrated Silicon Solution, Inc.- www.issi.com Rev. A4 02/11/2020 A0-A18 I/O0-I/O14 I/O15/A19 CS1#, CS2 OE# WE# LB# Address Inputs Data Inputs/Outputs I/O15, when used in a x16 mode, A19 when used in a x8 mode. Chip Enable Inputs Output Enable Input NC Write Enable Input Lower-byte Control (I/O0-I/O7) Upper-byte Control (I/O8-I/O15) Must be tied to VDD to use as X16 or VSS to use as X8. UB#,LB#, I/O 8~I/O14 are not used and I/O 15 become A19 in x8 mode. No Connection VDD VSS Power Ground UB# BYTE# 2 IS62WV51216GALL/BLL IS65WV51216GALL/BLL FUNCTION DESCRIPTION SRAM is one of random access memories. Each byte or word has an address and can be accessed randomly. SRAM has three different modes supported. Each function is described below with Truth Table. STANDBY MODE Device enters standby mode when deselected (CS1# HIGH or CS2 LOW or both UB# and LB# are HIGH). The input and output pins (I/O0-15) are placed in a high impedance state. The current consumption in this mode will be ISB1 or ISB2. CMOS input in this mode will maximize saving power. WRITE MODE Write operation issues with Chip selected (CS1# LOW and CS2 HIGH) and Write Enable (WE#) input LOW. The input and output pins (I/O0-15) are in data input mode. Output buffers are closed during this time even if OE# is LOW. UB# and LB# enables a byte write feature. By enabling LB# LOW, data from I/O pins (I/O0 through I/O7) are written into the location specified on the address pins. And with UB# being LOW, data from I/O pins (I/O8 through I/O15) are written into the location. READ MODE Read operation issues with Chip selected (CS1# LOW and CS2 HIGH) and Write Enable (WE#) input HIGH. When OE# is LOW, output buffer turns on to make data output. Any input to I/O pins during READ mode is not permitted. UB# and LB# enables a byte read feature. By enabling LB# LOW, data from memory appears on I/O0-7. And with UB# being LOW, data from memory appears on I/O8-15. In the READ mode, output buffers can be turned off by pulling OE# HIGH. In this mode, internal device operates as READ but I/Os are in a high impedance state. Since device is in READ mode, active current is used. TRUTH TABLE Mode Not Selected Output Disabled Read Write CS1# CS2 WE# OE# LB# UB# I/O0-I/O7 I/O8-I/O15 H X X L L L L L L L L X L X H H H H H H H H X X X H H H H H L L L X X X H H L L L X X X X X H L X L H L L H L X X H X L H L L H L L High-Z High-Z High-Z High-Z High-Z DOUT High-Z DOUT DIN High-Z DIN High-Z High-Z High-Z High-Z High-Z High-Z DOUT DOUT High-Z DIN DIN Integrated Silicon Solution, Inc.- www.issi.com Rev. A4 02/11/2020 VDD Current ISB2 ICC,ICC1 ICC,ICC1 ICC,ICC1 3 IS62WV51216GALL/BLL IS65WV51216GALL/BLL ABSOLUTE MAXIMUM RATINGS AND OPERATING RANGE ABSOLUTE MAXIMUM RATINGS(1) Symbol Vt er m Parameter Terminal Voltage with Respect to GND Value –0.5 to VDD + 0.5V Unit V VDD V DD Related to GND –0.3 to 4.0 V tStg Storage Temperature –65 to +150 PT Power Dissipation 1.0 C W Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. OPERATING RANGE(1) Range Ambient Temperature Commercial 0C to +70C Industrial -40C to +85C Automotive PART NUMBER ~ALL SPEED (MAX) VDD(MIN) VDD(TYP) VDD(MAX) 55 ns 1.65V 1.8V 2.2V 55 ns 1.65V 1.8V 2.2V -40C to +125C 55 ns 1.65V 1.8V 2.2V Commercial 0C to +70C 45ns 2.2V 3.0V 3.6V Industrial -40C to +85C 45ns 2.2V 3.0V 3.6V Automotive -40C to +125C 55ns 2.2V 3.0V 3.6V Note: 1. ~BLL Full device AC operation assumes a 100 µs ramp time from 0 to Vcc(min) and 200 µs wait time after Vcc stabilization. PIN CAPACITANCE (1) Parameter Symbol Input capacitance DQ capacitance (IO0–IO15) CIN CI/O Test Condition TA = 25°C, f = 1 MHz, VDD = VDD(typ) Max Units 6 8 pF pF Note: 1. These parameters are guaranteed by design and tested by a sample basis only. THERMAL CHARACTERISTICS (1) Parameter Thermal resistance from junction to ambient (airflow = 1m/s) Thermal resistance from junction to pins Thermal resistance from junction to case Symbol RθJA RθJB RθJC Rating TBD TBD TBD Units °C/W °C/W °C/W Note: 1. These parameters are guaranteed by design and tested by a sample basis only. Integrated Silicon Solution, Inc.- www.issi.com Rev. A4 02/11/2020 4 IS62WV51216GALL/BLL IS65WV51216GALL/BLL AC TEST CONDITIONS (OVER THE OPERATING RANGE) Parameter Unit Unit (1.65V~2.2V) (2.2V~3.6V) 0V to VDD 0V to VDD 1V/ns 1V/ns 0.9V ½ VDD 13500 1005 10800 820 1.8V VDD Refer to Figure 1 and 2 Input Pulse Level Input Rise and Fall Time Output Timing Reference Level R1 R2 VTM Output Load Conditions OUTPUT LOAD CONDITIONS FIGURES FIGURE 1 FIGURE 2 R1 R1 VTM VTM OUTPUT OUTPUT 30pF, Including jig and scope R2 Integrated Silicon Solution, Inc.- www.issi.com Rev. A4 02/11/2020 5pF, Including jig and scope R2 5 IS62WV51216GALL/BLL IS65WV51216GALL/BLL DC ELECTRICAL CHARACTERISTICS IS62(5)WV51216GALL DC ELECTRICAL CHARACTERISTICS-I (OVER THE OPERATING RANGE) VDD = 1.65V ~ 2.2V Symbol VOH VOL VIH(1) VIL(1) ILI ILO Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Output Leakage Test Conditions I OH = -0.1 mA IOL = 0.1 mA GND < VIN < VDD GND < VIN < VDD, Output Disabled Min. 1.4 — 1.4 –0.2 –1 –1 Max. — 0.2 VDD + 0.2 0.4 1 1 Unit V V V V µA µA Notes: 1. VILL(min) = -1.0V AC (pulse width < 10ns). Not 100% tested. VIHH (max) = VDD + 1.0V AC (pulse width < 10ns). Not 100% tested. IS62(5)WV51216GBLL DC ELECTRICAL CHARACTERISTICS-I (OVER THE OPERATING RANGE) VDD = 2.2V ~ 3.6V Symbol VOH Parameter Output HIGH Voltage VOL Output LOW Voltage VIH(1) Input HIGH Voltage VIL(1) Input LOW Voltage ILI ILO Input Leakage Output Leakage Test Conditions 2.2 ≤ V DD < 2.7, I OH = -0.1 mA 2.7 ≤ V DD ≤ 3.6, I OH = -1.0 mA 2.2 ≤ V DD < 2.7, IOL = 0.1 mA 2.7 ≤ V DD ≤ 3.6, IOL = 2.1 mA 2.2 ≤ V DD < 2.7 2.7 ≤ V DD ≤ 3.6 2.2 ≤ V DD < 2.7 2.7 ≤ V DD ≤ 3.6 GND < VIN < VDD GND < VIN < VDD, Output Disabled Min. 2.0 2.4 — — 1.8 2.0 –0.3 –0.3 –1 –1 Max. — — 0.4 0.4 VDD + 0.3 VDD + 0.3 0.6 0.8 1 1 Unit V V V V V V V V µA µA Notes: 1. VILL(min) = -2.0V AC (pulse width < 10ns). Not 100% tested. VIHH (max) = VDD + 2.0V AC (pulse width < 10ns). Not 100% tested. Integrated Silicon Solution, Inc.- www.issi.com Rev. A4 02/11/2020 6 IS62WV51216GALL/BLL IS65WV51216GALL/BLL IS62(5)WV51216GALL DC ELECTRICAL CHARACTERISTICS-II FOR POWER (OVER THE OPERATING RANGE) Symbol Parameter ICC VDD Dynamic Operating Supply Current VDD = VDD(max), IOUT = 0mA, f = fmax, ICC1 VDD Static Operating Supply Current VDD = VDD(max), IOUT = 0mA, f=0 CMOS Standby Current (CMOS Inputs) VDD = VDD(max), f = 0, CS1# ≥ VDD - 0.2V or CS2 < 0.2V or (LB# and UB#) ≥ VDD - 0.2V, VIN ≤ 0.2V or VIN ≥ VDD - 0.2V ISB2 Notes: 1. 2. Grade Typ(1) Max Com. Ind. Auto. A3 Com. Ind. Auto. A3 - 35 35 35 5 5 5 25°C 5.5 9(2) 40°C 6.0 10(2) 70°C 7.5 14 Ind. 85°C 10.5 20 Auto. A3 125°C 25 55 Test Conditions Com. Unit mA mA µA Typical value indicates the value for the center of distribution at V DD=VDD (Typ.), and not 100% tested. Maximum value at 25°C, 40°C are guaranteed by design, and not 100% tested. IS62(5)WV51216GBLL DC ELECTRICAL CHARACTERISTICS-II FOR POWER (OVER THE OPERATING RANGE) Symbol Parameter ICC VDD Dynamic Operating Supply Current VDD = VDD(max), IOUT = 0mA, f = fmax, ICC1 VDD Static Operating Supply Current VDD = VDD(max), IOUT = 0mA, f=0 ISB2 Notes: 1. 2. CMOS Standby Current (CMOS Inputs) Grade Typ(1) Max Com. Ind. Auto. A3 Com. Ind. Auto. A3 - 35 35 35 5 5 5 25°C 5.5 9(2) 40°C 6.0 10(2) 70°C 7.5 14 Ind. 85°C 10.5 20 Auto. A3 125°C 25 55 Test Conditions VDD = VDD(max), f = 0, CS1# ≥ VDD - 0.2V or CS2 < 0.2V or (LB# and UB#) ≥ VDD - 0.2V, VIN ≤ 0.2V or VIN ≥ VDD - 0.2V Com. Unit mA mA µA Typical value indicates the value for the center of distribution at V DD=VDD (Typ.), and not 100% tested. Maximum value at 25°C, 40°C are guaranteed by design, and not 100% tested. Integrated Silicon Solution, Inc.- www.issi.com Rev. A4 02/11/2020 7 IS62WV51216GALL/BLL IS65WV51216GALL/BLL AC CHARACTERISTICS(6) (OVER OPERATING RANGE) READ CYCLE AC CHARACTERISTICS 45ns Max 55ns Min Max Parameter Symbol Read Cycle Time Address Access Time Output Hold Time CS1#, CS2 Access Time UB#, LB# Access Time OE# Access Time tRC tAA tOHA tACS1/ACS2 tBA tDOE 45 10 - 45 45 45 20 55 10 - OE# to High-Z Output OE# to Low-Z Output CS1#, CS2 to High-Z Output CS1#, CS2 to Low-Z Output UB#, LB# to High-Z Output UB#, LB# to Low-Z Output tHZOE tLZOE tHZCS tLZCS tHZB tLZB 5 10 10 15 15 15 - 5 10 10 Min unit notes 55 55 55 25 ns ns ns ns ns ns 1,5 1 1 1 1 1 20 20 20 - ns ns ns ns ns ns 2 2 2 2 2 2 unit notes WRITE CYCLE AC CHARACTERISTICS Parameter Symbol Write Cycle Time CS1#, CS2 to Write End Address Setup Time to Write End UB#,LB# to Write End Address Hold from Write End Address Setup Time WE# Pulse Width Data Setup to Write End Data Hold from Write End WE# LOW to High-Z Output WE# HIGH to Low-Z Output 45ns 55ns Min Max Min Min tWC tSCS1/SCS2 tAW tPWB tHA 45 35 35 35 0 - 55 40 40 40 0 - ns ns ns ns ns 1,3,5 1,3 1,3 1,3 1,3 tSA tPWE tSD tHD tHZWE tLZWE 0 35 20 0 5 15 - 0 40 25 0 5 20 - ns ns ns ns ns ns 1,3 1,3,4 1,3 1,3 2,3 2,3 Notes: 1. Tested with the load in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. tHZOE, tHZCS, tHZB, and tHZWE transitions are measured when the output enters a high impedance state. Not 100% tested. 3. The internal write time is defined by the overlap of CS1# = LOW, CS2=HIGH, UB# or LB# = LOW, and WE# = LOW. All four conditions must be in valid states to initiate a Write, but any condition can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. 4. tPWE > tHZWE + tSD when OE# is LOW. 5. Address inputs must meet VIH and VIL SPEC during this period. Any glitch or unknown inputs are not permitted. Unknown input with standby mode is acceptable. 6. Data retention characteristics are defined later in DATA RETENTION CHARACTERISTICS. Integrated Silicon Solution, Inc.- www.issi.com Rev. A4 02/11/2020 8 IS62WV51216GALL/BLL IS65WV51216GALL/BLL Timing Diagram READ CYCLE NO. 1(1) (ADDRESS CONTROLLED, CS1# = OE# = UB# = LB# = LOW, CS2 = WE# = HIGH) tRC ADDRESS tAA tOHA tOHA I/O0-15 PREVIOUS DATA VALID Low-Z DATA VALID Low-Z Notes: 1. The device is continuously selected. READ CYCLE NO.2(1) (OE# CONTROLLED, WE# = HIGH) tRC ADDRESS tAA tOHA tDOE OE# tHZOE tLZOE CS1# tHZCS1/ tHZCS2 tACS1/tACS2 CS2 tLZCS1/ tLZCS2 UB#,LB# tHZB tBA tLZB DOUT HIGH-Z LOW-Z DATA VALID Notes: 1. Address is valid prior to or coincident with CS1# LOW or CS2 HIGH transition. Integrated Silicon Solution, Inc.- www.issi.com Rev. A4 02/11/2020 9 IS62WV51216GALL/BLL IS65WV51216GALL/BLL WRITE CYCLE NO.1(1,2) (CS1#, CS2 CONTROLLED, OE# = HIGH OR LOW) tWC ADDRESS tSCS1 tSA CS1# tHA tSCS2 CS2 tAW tPWE WE# tPWB UB#, LB# tHZWE DATA UNDEFINED DOUT HIGH-Z (1) tSD DATA UNDEFINED DIN (2) tLZWE tHD DATA IN VALID Notes: 1. tHZWE is based on the assumption when tSA=0nS after READ operation. Actual DOUT for tHZWE may not appear if OE# goes high before Write Cycle. tHZOE is the time DOUT goes to High-Z after OE# goes high. 2. During this period the I/Os are in output state. Do not apply input signals. WRITE CYCLE NO. 2(1,2) (WE# CONTROLLED: OE# IS HIGH DURING WRITE CYCLE) tWC ADDRESS tSCS1 CS1# tSCS2 CS2 WE# tHA tAW tPWE tSA tPWB UB#, LB# OE# DOUT tHZOE DATA UNDEFINED HIGH-Z (1) tSD DIN DATA UNDEFINED (2) tHD DATA IN VALID Notes: 1. tHZOE is the time DOUT goes to High-Z after OE# goes high. 2. During this period the I/Os are in output state. Do not apply input signals. Integrated Silicon Solution, Inc.- www.issi.com Rev. A4 02/11/2020 10 IS62WV51216GALL/BLL IS65WV51216GALL/BLL WRITE CYCLE NO. 3(1) (WE# CONTROLLED: OE# IS LOW DURING WRITE CYCLE) tWC ADDRESS tSCS1 CS1# tHA tSCS2 CS2 tAW WE# tPWE tSA tPWB UB#, LB# tHZWE DOUT DATA UNDEFINED (1) HIGH-Z tSD DIN DATA UNDEFINED (2) tLZWE tHD DATA IN VALID Notes: 1. If OE# is low during write cycle, tHZWE must be met in the application. Do not apply input signal during this period. Data output from the previous READ operation will drive IO BUS. Integrated Silicon Solution, Inc.- www.issi.com Rev. A4 02/11/2020 11 IS62WV51216GALL/BLL IS65WV51216GALL/BLL WRITE CYCLE NO. 4(1,2,3) (UB# & LB# Controlled, OE# = LOW) tWC tWC ADDRESS ADDRESS 1 ADDRESS 2 CS1#=LOW CS2=HIGH OE#=LOW tSA tHA tSA tHA WE# tPWB UB#, LB# tPWB WORD 1 WORD 2 tHZWE DOUT tLZWE HIGH-Z DATA UNDEFINED tHD tSD DIN DATA IN VALID DATA IN VALID Notes: 1. If OE# is low during write cycle, tHZWE must be met in the application. Do not apply input signal during this period. Data output from the previous READ operation will drive IO BUS. 2. Due to the restriction of note1, OE# is recommended to be HIGH during write period. 3. WE# stays LOW in this example. If WE# toggles, tPWE and tHZWE must be considered. Integrated Silicon Solution, Inc.- www.issi.com Rev. A4 02/11/2020 12 IS62WV51216GALL/BLL IS65WV51216GALL/BLL DATA RETENTION CHARACTERISTICS Symbol VDR IDR Typ.(1) Max. Unit 1.5 - - V 25°C - 5.5 13 85°C - - 19 125°C - - 52 See Data Retention Waveform 0 - - ns See Data Retention Waveform tRC - - ns Test Condition VDD for Data Retention See Data Retention Waveform Data Retention Current VDD = VDR (min), CS1# ≥ VDD – 0.2V or CS2 ≤ 0.2V or (LB# and UB#) ≥ VDD - 0.2V, VIN ≤ 0.2V or VIN ≥ VDD - 0.2V Data Retention Setup Time Recovery Time tSDR (2) tRDR Notes: 1. 2. Min. Parameter uA Typical value indicates the value for the center of distribution at VDD = VDR (min.), and not 100% tested. VDD power down slope must be longer than 100 us/volt when enter into Data Retention Mode. DATA RETENTION WAVEFORM (CS1# CONTROLLED) tSDR Data Retention Mode tRDR VDD VDR CS1# > VDD – 0.2V CS1# GND DATA RETENTION WAVEFORM (CS2 CONTROLLED) tSDR Data Retention Mode tRDR VDD CS2 VDR CS2 < 0.2V VSS Integrated Silicon Solution, Inc.- www.issi.com Rev. A4 02/11/2020 13 IS62WV51216GALL/BLL IS65WV51216GALL/BLL DATA RETENTION WAVEFORM (UB# AND LB# CONTROLLED) tSDR Data Retention Mode tRDR VDD VDR UB#/LB# UB# and LB# > VDD – 0.2V GND Integrated Silicon Solution, Inc.- www.issi.com Rev. A4 02/11/2020 14 IS62WV51216GALL/BLL IS65WV51216GALL/BLL ORDERING INFORMATION IS62/65WV51216GALL (1.65V - 2.2V) Industrial Range: -40°C to +85°C Speed (ns) 55 Order Part No. Package IS62WV51216GALL-55TLI TSOP (Type I), Lead-free AUTOMOTIVE RANGE (A3): –40°C TO +125°C Speed (ns) 55 Order Part No. Package IS65WV51216GALL-55CTLA3 TSOP (Type I), Copper Leadframe, Lead-free IS62/65WV51216GBLL (2.2V - 3.6V) Industrial Range: -40°C to +85°C Speed (ns) 45 Order Part No. Package IS62WV51216GBLL-45TLI TSOP (Type I), Lead-free AUTOMOTIVE RANGE (A3): –40°C TO +125°C Speed (ns) 55 Order Part No. Package IS65WV51216GBLL-45CTLA3 TSOP (Type I), Copper Leadframe, Lead-free Integrated Silicon Solution, Inc.- www.issi.com Rev. A4 02/11/2020 15 IS62WV51216GALL/BLL IS65WV51216GALL/BLL PACKAGE INFORMATION Integrated Silicon Solution, Inc.- www.issi.com Rev. A4 02/11/2020 16